From 2fe0e50942e22db6c726f95afb25c8db06fb1cf1 Mon Sep 17 00:00:00 2001
From: Redo <A509DCFC@cock.li>
Date: Thu, 3 Nov 2022 13:00:20 -0600
Subject: [PATCH] add bitshifts, make 8bit loads update zero flag
---
instructionList.txt | 72 +++++++----
rom-8608-defs.lua | 293 +++++++++++++++++++++++++-------------------
2 files changed, 212 insertions(+), 153 deletions(-)
diff --git a/instructionList.txt b/instructionList.txt
index af89023..89c6470 100644
--- a/instructionList.txt
+++ b/instructionList.txt
@@ -49,6 +49,11 @@ and imm8 74 2 A&=imm8, set zero flag
ior imm8 75 2 A|=imm8, set zero flag
xor imm8 76 2 A^=imm8, set zero flag
ann imm8 77 2 A&=~imm8, set zero flag
+shl imm8 D0 2 A<<=imm8, set zero flag
+shr imm8 D1 2 A>>=imm8, set zero flag
+rol imm8 D2 2 A<<<=imm8, set zero flag
+ror imm8 D3 2 A>>>=imm8, set zero flag
+sra imm8 D4 2 A>>a=imm8, set zero flag
add *s+imm8 AE 3 A+=*(S+imm8), set flags
adb *s+imm8 9B 3 B+=*(S+imm8), set flags
adc *s+imm8 9C 3 C+=*(S+imm8), set flags
@@ -62,6 +67,11 @@ and *s+imm8 B1 3 A&=*(S+imm8), set zero flag
ior *s+imm8 B2 3 A|=*(S+imm8), set zero flag
xor *s+imm8 B3 3 A^=*(S+imm8), set zero flag
ann *s+imm8 B4 3 A&=~*(S+imm8), set zero flag
+shl *s+imm8 D5 3 A<<=*(S+imm8), set zero flag
+shr *s+imm8 D6 3 A<<=*(S+imm8), set zero flag
+rol *s+imm8 D7 3 A<<<=*(S+imm8), set zero flag
+ror *s+imm8 D8 3 A>>>=*(S+imm8), set zero flag
+sra *s+imm8 D9 3 A>>a=*(S+imm8), set zero flag
add b A0 1 A+=B, set flags
adc b 9F 1 C+=B, set flags
sub b A1 1 A-=B, set flags
@@ -73,6 +83,11 @@ and b A3 1 A&=B, set zero flag
ior b A4 1 A|=B, set zero flag
xor b A5 1 A^=B, set zero flag
ann b A6 1 A&=~B, set zero flag
+shl b DA 1 A<<=B, set zero flag
+shr b DB 1 A>>=B, set zero flag
+rol b DC 1 A<<<=B, set zero flag
+ror b DD 1 A>>>=B, set zero flag
+sra b DE 1 A>>a=B, set zero flag
add c A7 1 A+=C, set flags
adb c BD 1 B+=C, set flags
sub c A8 1 A-=C, set flags
@@ -84,6 +99,11 @@ and c AA 1 A&=C, set zero flag
ior c AB 1 A|=C, set zero flag
xor c AC 1 A^=C, set zero flag
ann c AD 1 A&=~C, set zero flag
+shl c DF 1 A<<=C, set zero flag
+shr c 4D 1 A>>=C, set zero flag
+rol c 3E 1 A<<<=C, set zero flag
+ror c 3F 1 A>>>=C, set zero flag
+sra c 2F 1 A>>a=C, set zero flag
adb a BE 1 B+=A, set flags
sbb a BF 1 B-=A, set flags
adc a 4E 1 C+=A, set flags
@@ -117,18 +137,18 @@ ppp 43 3 P=*(----S)
ppq 49 3 Q=*(----S)
8-bit Load/Store (B):
-lda imm8 20 2 A=imm8
-ldb imm8 26 2 B=imm8
-ldc imm8 27 2 C=imm8
-lda *s+imm8 28 3 A=*s+imm8
-ldb *s+imm8 29 3 B=*s+imm8
-ldc *s+imm8 2A 3 C=*s+imm8
+lda imm8 20 2 A=imm8, update zero flag
+ldb imm8 26 2 B=imm8, update zero flag
+ldc imm8 27 2 C=imm8, update zero flag
+lda *s+imm8 28 3 A=*s+imm8, update zero flag
+ldb *s+imm8 29 3 B=*s+imm8, update zero flag
+ldc *s+imm8 2A 3 C=*s+imm8, update zero flag
sta *s+imm8 96 3 *s+imm8=A
stb *s+imm8 97 3 *s+imm8=B
stc *s+imm8 98 3 *s+imm8=C
-lda *imm16 51 4 A=*imm16
-ldb *imm16 56 4 B=*imm16
-ldc *imm16 57 4 C=*imm16
+lda *imm16 51 4 A=*imm16, update zero flag
+ldb *imm16 56 4 B=*imm16, update zero flag
+ldc *imm16 57 4 C=*imm16, update zero flag
sta *imm16 50 4 *imm16=A
stb *imm16 58 4 *imm16=B
stc *imm16 59 4 *imm16=C
@@ -138,24 +158,24 @@ stc *p 5B 2 *P=C
sta *q 54 2 *Q=A
stb *q 5C 2 *Q=B
stc *q 5D 2 *Q=C
-lda *p 53 2 A=*P
-ldb *p 5E 2 B=*P
-ldc *p 5F 2 C=*P
-lda *q 55 2 A=*Q
-ldb *q 61 2 B=*Q
-ldc *q 62 2 C=*Q
+lda *p 53 2 A=*P, update zero flag
+ldb *p 5E 2 B=*P, update zero flag
+ldc *p 5F 2 C=*P, update zero flag
+lda *q 55 2 A=*Q, update zero flag
+ldb *q 61 2 B=*Q, update zero flag
+ldc *q 62 2 C=*Q, update zero flag
sta *p++ C0 2 *P++=A
stb *p++ C1 2 *P++=B
stc *p++ C2 2 *P++=C
sta *q++ C3 2 *Q++=A
stb *q++ C4 2 *Q++=B
stc *q++ C5 2 *Q++=C
-lda *p++ C6 2 A=*P++
-ldb *p++ C7 2 B=*P++
-ldc *p++ C8 2 C=*P++
-lda *q++ C9 2 A=*Q++
-ldb *q++ CA 2 B=*Q++
-ldc *q++ CB 2 C=*Q++
+lda *p++ C6 2 A=*P++, update zero flag
+ldb *p++ C7 2 B=*P++, update zero flag
+ldc *p++ C8 2 C=*P++, update zero flag
+lda *q++ C9 2 A=*Q++, update zero flag
+ldb *q++ CA 2 B=*Q++, update zero flag
+ldc *q++ CB 2 C=*Q++, update zero flag
16-bit Load/Store (W):
ldp imm16 21 3 P=imm16
@@ -201,13 +221,13 @@ ldq p 8E 1 Q=P
lds p 8F 1 S=P
ldv p 90 1 V=P
-Opcodes used: 187/255
+Opcodes used: 207/255
0123456789ABCDEF
00 | C---------------
10 | UUIIUIIUUUUUUUUU
-20 | BWWWAWBBBBBUUUU-
-30 | JJJJJJJ---------
-40 | SSSSSSSSSSXXX-AA
+20 | BWWWAWBBBBBUUUUA
+30 | JJJJJJJ-------AA
+40 | SSSSSSSSSSXXXAAA
50 | BBBBBBBBBBBBBBBB
60 | JBBJJJJJWWWWWWWW
70 | AAAAAAAAAAWWWWWW
@@ -216,6 +236,6 @@ Opcodes used: 187/255
A0 | AAAAAAAAAAAAAAAA
B0 | AAAAAAAAAAAAAAAA
C0 | BBBBBBBBBBBBWWWW
-D0 | ----------------
+D0 | AAAAAAAAAAAAAAAA
E0 | ----------------
F0 | CCCCC-----------
diff --git a/rom-8608-defs.lua b/rom-8608-defs.lua
index a2b148d..047451a 100644
--- a/rom-8608-defs.lua
+++ b/rom-8608-defs.lua
@@ -17,13 +17,15 @@ roms = {
} },
{ pos = {-34, 16, 17}, size = {32, 32, 32}, signals = {
"_", "_", "_", "_", "_", "_", "_", "_",
- "_", "_", "_", "instrPre", "instrLoadPre", "always1", "instrLoad", "adrOut",
+ "_", "_", "memSaveNZ", "instrPre", "instrLoadPre", "always1", "instrLoad", "adrOut",
"memWriteAlur", "memSave", "instrNext0NZ", "instrNext0Z", "instrNext0NC", "instrNext0C", "instrLoadSub", "instrLoad",
"instrNext2", "instrNext1", "instrNext0", "memSaveU", "memSaveT", "memSaveC", "memSaveB", "memSaveA",
} },
- { pos = {66, 16, 0}, size = {32, 32, 16}, signals = {
+ { pos = {66, 16, 0}, size = {32, 32, 32}, signals = {
"adrr1", "adrrm1", "adrrm2", "adrr2", "adwrm1", "adwrm2", "adwr2", "adwr1",
"memRead", "memWrite", "runFlgVal", "runFlgClk", "intFlgVal", "intFlgClk", "irqFlgClk", "always1",
+ "aluShiftArith", "aluShiftRoll", "aluShiftRight", "aluShift", "_", "_", "_", "_",
+ "_", "_", "_", "_", "_", "_", "_", "_",
} },
},
@@ -72,6 +74,7 @@ operations = {
store162 = {"adrInc","storeReg"},
loadUTU = {"adrrUT","loadReg","memSaveU"},
storeUT = {"adrrUT","storeReg"},
+ memSaveFlags = {"memSaveNZ"},
adwrUT = {"adwrhU","adwrlT"},
adrrUT = {"adrrhU","adrrlT"},
@@ -92,12 +95,28 @@ operations = {
jmpAbsQ = {"jmpAbs","adrlQ"},
saveRetAddr = {"adwlI","adwInc","adwSaveQ"},
- aluMove = {"aluAdd","aluRun"},
- aluA = {"alulA","aluSaveA","aluRun"},
- aluB = {"alulB","aluSaveB","aluRun"},
- aluC = {"alulC","aluSaveC","aluRun"},
- aluT = {"alulT","aluSaveT","aluRun"},
- aluU = {"alulU","aluSaveU","aluRun"},
+ aluA = {"alulA","aluSaveA"},
+ aluB = {"alulB","aluSaveB"},
+ aluC = {"alulC","aluSaveC"},
+ aluT = {"alulT","aluSaveT"},
+ aluU = {"alulU","aluSaveU"},
+ aluOpAdd = {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ" },
+ aluOpAddC= {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ", "aluCinC" },
+ aluOpSub = {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ","aluRInv","aluCinOn"},
+ aluOpSubC= {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ","aluRInv","aluCinC" },
+ aluOpAnd = {"aluRun","aluAnd" , "aluSaveNZ"},
+ aluOpIor = {"aluRun","aluIor" , "aluSaveNZ"},
+ aluOpXor = {"aluRun","aluXor" , "aluSaveNZ"},
+ aluOpAnn = {"aluRun","aluAnd","aluRInv", "aluSaveNZ"},
+ aluOpCmp = {"aluOpSub"},
+ aluOpInc = {"aluOpAdd", "aluCinOn"},
+ aluOpDec = {"aluOpAdd","aluRInv","aluCinOn"},
+ aluOpMov = {"aluAdd","aluSaveNZ"},
+ aluOpShl = {"aluShift" ,"aluSaveNZ"},
+ aluOpShr = {"aluShift","aluShiftRight" ,"aluSaveNZ"},
+ aluOpRol = {"aluShift", "aluShiftRoll" ,"aluSaveNZ"},
+ aluOpRor = {"aluShift","aluShiftRight","aluShiftRoll" ,"aluSaveNZ"},
+ aluOpSra = {"aluShift","aluShiftRight", "aluShiftArith","aluSaveNZ"},
},
instructions = {
@@ -116,22 +135,22 @@ instructions = {
{ mnem="dcq" , opcode=0x16, {"adwlQ","adwrm1","adwSaveQ","instrNext"}, desc="Q--" },
{ category = "8-bit Unary", catlet="U" },
- { mnem="inc a" , opcode=0x10, {"aluA","alur1", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A++, set flags" },
- { mnem="dec a" , opcode=0x11, {"aluA","alurm1", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A--, set flags" },
- { mnem="icc a" , opcode=0x1B, {"aluA", "aluCinC", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=CF, set flags" },
- { mnem="inc b" , opcode=0x19, {"aluB","alur1", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B++, set flags" },
- { mnem="dec b" , opcode=0x1A, {"aluB","alurm1", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B--, set flags" },
- { mnem="icc b" , opcode=0x1C, {"aluB", "aluCinC", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B+=CF, set flags" },
- { mnem="inc c" , opcode=0x17, {"aluC","alur1", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C++, set flags" },
- { mnem="dec c" , opcode=0x18, {"aluC","alurm1", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C--, set flags" },
- { mnem="icc c" , opcode=0x1D, {"aluC", "aluCinC", "aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C+=CF, set flags" },
- { mnem="tst a" , opcode=0x14, {"alulA","aluRun","aluRInv","aluCinOn","aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="Set flags according to A-0" },
- { mnem="tst b" , opcode=0x1E, {"alulB","aluRun","aluRInv","aluCinOn","aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="Set flags according to B-0" },
- { mnem="tst c" , opcode=0x1F, {"alulC","aluRun","aluRInv","aluCinOn","aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="Set flags according to C-0" },
- { mnem="inc *s+imm8", opcode=0x2B, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alur1", "aluAdd","aluSaveCarry","aluSaveNZ","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)++, set flags" },
- { mnem="dec *s+imm8", opcode=0x2C, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alurm1", "aluAdd","aluSaveCarry","aluSaveNZ","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)--, set flags" },
- { mnem="icc *s+imm8", opcode=0x2D, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU", "aluCinC", "aluAdd","aluSaveCarry","aluSaveNZ","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)+=CF, set flags" },
- { mnem="tst *s+imm8", opcode=0x2E, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"alulU","aluRun","aluRInv","aluCinOn","aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="Set flags according to *(S+imm8)-0" },
+ { mnem="inc a" , opcode=0x10, {"aluA","alur1" ,"aluOpAdd" ,"instrNext"}, desc="A++, set flags" },
+ { mnem="dec a" , opcode=0x11, {"aluA","alurm1","aluOpAdd" ,"instrNext"}, desc="A--, set flags" },
+ { mnem="icc a" , opcode=0x1B, {"aluA", "aluOpAddC","instrNext"}, desc="A+=CF, set flags" },
+ { mnem="inc b" , opcode=0x19, {"aluB","alur1" ,"aluOpAdd" ,"instrNext"}, desc="B++, set flags" },
+ { mnem="dec b" , opcode=0x1A, {"aluB","alurm1","aluOpAdd" ,"instrNext"}, desc="B--, set flags" },
+ { mnem="icc b" , opcode=0x1C, {"aluB", "aluOpAddC","instrNext"}, desc="B+=CF, set flags" },
+ { mnem="inc c" , opcode=0x17, {"aluC","alur1" ,"aluOpAdd" ,"instrNext"}, desc="C++, set flags" },
+ { mnem="dec c" , opcode=0x18, {"aluC","alurm1","aluOpAdd" ,"instrNext"}, desc="C--, set flags" },
+ { mnem="icc c" , opcode=0x1D, {"aluC", "aluOpAddC","instrNext"}, desc="C+=CF, set flags" },
+ { mnem="tst a" , opcode=0x14, {"alulA", "aluOpCmp" ,"instrNext"}, desc="Set flags according to A-0" },
+ { mnem="tst b" , opcode=0x1E, {"alulB", "aluOpCmp" ,"instrNext"}, desc="Set flags according to B-0" },
+ { mnem="tst c" , opcode=0x1F, {"alulC", "aluOpCmp" ,"instrNext"}, desc="Set flags according to C-0" },
+ { mnem="inc *s+imm8", opcode=0x2B, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alur1" ,"aluOpAdd" ,"instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)++, set flags" },
+ { mnem="dec *s+imm8", opcode=0x2C, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alurm1","aluOpAdd" ,"instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)--, set flags" },
+ { mnem="icc *s+imm8", opcode=0x2D, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU", "aluOpAddC","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)+=CF, set flags" },
+ { mnem="tst *s+imm8", opcode=0x2E, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"alulU", "aluOpCmp" ,"instrNext"}, desc="Set flags according to *(S+imm8)-0" },
{ category = "16-bit Arithmetic", catlet = "X"},
{ mnem="adp imm8" , opcode=0x4A, {"loadImmedT","instrSub1"}, {"adwP","adwrTX","instrNext"}, desc="P+=imm8 signed"},
@@ -139,58 +158,78 @@ instructions = {
{ mnem="ads imm8" , opcode=0x4C, {"loadImmedT","instrSub1"}, {"adwS","adwrTX","instrNext"}, desc="S+=imm8 signed"},
{ category = "8-bit Arithmetic/Logic", catlet="A" },
- { mnem="add imm8" , opcode=0x24, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=imm8, set flags" },
- { mnem="adb imm8" , opcode=0x72, {"loadImmedT","instrSub1"}, {"aluB", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="B+=imm8, set flags" },
- { mnem="adc imm8" , opcode=0x73, {"loadImmedT","instrSub1"}, {"aluC", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="C+=imm8, set flags" },
- { mnem="sub imm8" , opcode=0x70, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=imm8, set flags" },
- { mnem="sbb imm8" , opcode=0x99, {"loadImmedT","instrSub1"}, {"aluB", "alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B-=imm8, set flags" },
- { mnem="sbc imm8" , opcode=0x9A, {"loadImmedT","instrSub1"}, {"aluC", "alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C-=imm8, set flags" },
- { mnem="acc imm8" , opcode=0x78, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAdd", "aluCinC", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=imm8+CF, set flags" },
- { mnem="scc imm8" , opcode=0x79, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAdd","aluRInv","aluCinC" ,"aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=imm8+CF, set flags" },
- { mnem="cmp imm8" , opcode=0x71, {"loadImmedT","instrSub1"}, {"alulA","aluRun","alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="set flags according to A-imm8" },
- { mnem="and imm8" , opcode=0x74, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAnd", "aluSaveNZ","instrNext"}, desc="A&=imm8, set zero flag" },
- { mnem="ior imm8" , opcode=0x75, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluIor", "aluSaveNZ","instrNext"}, desc="A|=imm8, set zero flag" },
- { mnem="xor imm8" , opcode=0x76, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluXor", "aluSaveNZ","instrNext"}, desc="A^=imm8, set zero flag" },
- { mnem="ann imm8" , opcode=0x77, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAnd","aluRInv", "aluSaveNZ","instrNext"}, desc="A&=~imm8, set zero flag" },
- { mnem="add *s+imm8", opcode=0xAE, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=*(S+imm8), set flags" },
- { mnem="adb *s+imm8", opcode=0x9B, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="B+=*(S+imm8), set flags" },
- { mnem="adc *s+imm8", opcode=0x9C, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="C+=*(S+imm8), set flags" },
- { mnem="sub *s+imm8", opcode=0xAF, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=*(S+imm8), set flags" },
- { mnem="sbb *s+imm8", opcode=0x9D, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B-=*(S+imm8), set flags" },
- { mnem="sbc *s+imm8", opcode=0x9E, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C-=*(S+imm8), set flags" },
- { mnem="acc *s+imm8", opcode=0xB5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluAdd", "aluCinC", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=*(S+imm8)+CF, set flags" },
- { mnem="scc *s+imm8", opcode=0xB7, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluAdd","aluRInv","aluCinC", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=*(S+imm8)+CF, set flags" },
- { mnem="cmp *s+imm8", opcode=0xB0, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"alulA","aluRun","alurT","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="set flags according to A-*(S+imm8)" },
- { mnem="and *s+imm8", opcode=0xB1, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluAnd", "aluSaveNZ","instrNext"}, desc="A&=*(S+imm8), set zero flag" },
- { mnem="ior *s+imm8", opcode=0xB2, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluIor", "aluSaveNZ","instrNext"}, desc="A|=*(S+imm8), set zero flag" },
- { mnem="xor *s+imm8", opcode=0xB3, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluXor", "aluSaveNZ","instrNext"}, desc="A^=*(S+imm8), set zero flag" },
- { mnem="ann *s+imm8", opcode=0xB4, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluAnd","aluRInv", "aluSaveNZ","instrNext"}, desc="A&=~*(S+imm8), set zero flag" },
- { mnem="add b" , opcode=0xA0, {"aluA", "alurB","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=B, set flags" },
- { mnem="adc b" , opcode=0x9F, {"aluC", "alurB","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="C+=B, set flags" },
- { mnem="sub b" , opcode=0xA1, {"aluA", "alurB","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=B, set flags" },
- { mnem="sbc b" , opcode=0xB6, {"aluC", "alurB","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C-=B, set flags" },
- { mnem="acc b" , opcode=0xB8, {"aluA", "alurB","aluAdd", "aluCinC", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=B+CF, set flags" },
- { mnem="scc b" , opcode=0xB9, {"aluA", "alurB","aluAdd","aluRInv","aluCinC", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=B+CF, set flags" },
- { mnem="cmp b" , opcode=0xA2, {"alulA","aluRun","alurB","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="set flags according to A-B" },
- { mnem="and b" , opcode=0xA3, {"aluA", "alurB","aluAnd", "aluSaveNZ","instrNext"}, desc="A&=B, set zero flag" },
- { mnem="ior b" , opcode=0xA4, {"aluA", "alurB","aluIor", "aluSaveNZ","instrNext"}, desc="A|=B, set zero flag" },
- { mnem="xor b" , opcode=0xA5, {"aluA", "alurB","aluXor", "aluSaveNZ","instrNext"}, desc="A^=B, set zero flag" },
- { mnem="ann b" , opcode=0xA6, {"aluA", "alurB","aluAnd","aluRInv", "aluSaveNZ","instrNext"}, desc="A&=~B, set zero flag" },
- { mnem="add c" , opcode=0xA7, {"aluA", "alurC","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=C, set flags" },
- { mnem="adb c" , opcode=0xBD, {"aluB", "alurC","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="B+=C, set flags" },
- { mnem="sub c" , opcode=0xA8, {"aluA", "alurC","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=C, set flags" },
- { mnem="sbb c" , opcode=0xBC, {"aluB", "alurC","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B-=C, set flags" },
- { mnem="acc c" , opcode=0xBA, {"aluA", "alurC","aluAdd", "aluCinC", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=C+CF, set flags" },
- { mnem="scc c" , opcode=0xBB, {"aluA", "alurC","aluAdd","aluRInv","aluCinC" ,"aluSaveCarry","aluSaveNZ","instrNext"}, desc="A-=C+CF, set flags" },
- { mnem="cmp c" , opcode=0xA9, {"alulA","aluRun","alurC","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="set flags according to A-C" },
- { mnem="and c" , opcode=0xAA, {"aluA", "alurC","aluAnd", "aluSaveNZ","instrNext"}, desc="A&=C, set zero flag" },
- { mnem="ior c" , opcode=0xAB, {"aluA", "alurC","aluIor", "aluSaveNZ","instrNext"}, desc="A|=C, set zero flag" },
- { mnem="xor c" , opcode=0xAC, {"aluA", "alurC","aluXor", "aluSaveNZ","instrNext"}, desc="A^=C, set zero flag" },
- { mnem="ann c" , opcode=0xAD, {"aluA", "alurC","aluAnd","aluRInv", "aluSaveNZ","instrNext"}, desc="A&=~C, set zero flag" },
- { mnem="adb a" , opcode=0xBE, {"aluB", "alurA","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="B+=A, set flags" },
- { mnem="sbb a" , opcode=0xBF, {"aluB", "alurA","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="B-=A, set flags" },
- { mnem="adc a" , opcode=0x4E, {"aluC", "alurA","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="C+=A, set flags" },
- { mnem="sbc a" , opcode=0x4F, {"aluC", "alurA","aluAdd","aluRInv","aluCinOn","aluSaveCarry","aluSaveNZ","instrNext"}, desc="C-=A, set flags" },
+ { mnem="add imm8" , opcode=0x24, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpAdd" ,"instrNext"}, desc="A+=imm8, set flags" },
+ { mnem="adb imm8" , opcode=0x72, {"loadImmedT","instrSub1"}, {"aluB", "alurT","aluOpAdd" ,"instrNext"}, desc="B+=imm8, set flags" },
+ { mnem="adc imm8" , opcode=0x73, {"loadImmedT","instrSub1"}, {"aluC", "alurT","aluOpAdd" ,"instrNext"}, desc="C+=imm8, set flags" },
+ { mnem="sub imm8" , opcode=0x70, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpSub" ,"instrNext"}, desc="A-=imm8, set flags" },
+ { mnem="sbb imm8" , opcode=0x99, {"loadImmedT","instrSub1"}, {"aluB", "alurT","aluOpSub" ,"instrNext"}, desc="B-=imm8, set flags" },
+ { mnem="sbc imm8" , opcode=0x9A, {"loadImmedT","instrSub1"}, {"aluC", "alurT","aluOpSub" ,"instrNext"}, desc="C-=imm8, set flags" },
+ { mnem="acc imm8" , opcode=0x78, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpAddC","instrNext"}, desc="A+=imm8+CF, set flags" },
+ { mnem="scc imm8" , opcode=0x79, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpSubC","instrNext"}, desc="A-=imm8+CF, set flags" },
+ { mnem="cmp imm8" , opcode=0x71, {"loadImmedT","instrSub1"}, {"alulA","alurT","aluOpSub" ,"instrNext"}, desc="set flags according to A-imm8" },
+ { mnem="and imm8" , opcode=0x74, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpAnd" ,"instrNext"}, desc="A&=imm8, set zero flag" },
+ { mnem="ior imm8" , opcode=0x75, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpIor" ,"instrNext"}, desc="A|=imm8, set zero flag" },
+ { mnem="xor imm8" , opcode=0x76, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpXor" ,"instrNext"}, desc="A^=imm8, set zero flag" },
+ { mnem="ann imm8" , opcode=0x77, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpAnn" ,"instrNext"}, desc="A&=~imm8, set zero flag" },
+ { mnem="shl imm8" , opcode=0xD0, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpShl" ,"instrNext"}, desc="A<<=imm8, set zero flag" },
+ { mnem="shr imm8" , opcode=0xD1, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpShr" ,"instrNext"}, desc="A>>=imm8, set zero flag" },
+ { mnem="rol imm8" , opcode=0xD2, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpRol" ,"instrNext"}, desc="A<<<=imm8, set zero flag" },
+ { mnem="ror imm8" , opcode=0xD3, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpRor" ,"instrNext"}, desc="A>>>=imm8, set zero flag" },
+ { mnem="sra imm8" , opcode=0xD4, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluOpSra" ,"instrNext"}, desc="A>>a=imm8, set zero flag" },
+ { mnem="add *s+imm8", opcode=0xAE, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAdd" ,"instrNext"}, desc="A+=*(S+imm8), set flags" },
+ { mnem="adb *s+imm8", opcode=0x9B, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluOpAdd" ,"instrNext"}, desc="B+=*(S+imm8), set flags" },
+ { mnem="adc *s+imm8", opcode=0x9C, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluOpAdd" ,"instrNext"}, desc="C+=*(S+imm8), set flags" },
+ { mnem="sub *s+imm8", opcode=0xAF, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSub" ,"instrNext"}, desc="A-=*(S+imm8), set flags" },
+ { mnem="sbb *s+imm8", opcode=0x9D, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluOpSub" ,"instrNext"}, desc="B-=*(S+imm8), set flags" },
+ { mnem="sbc *s+imm8", opcode=0x9E, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluOpSub" ,"instrNext"}, desc="C-=*(S+imm8), set flags" },
+ { mnem="acc *s+imm8", opcode=0xB5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAddC","instrNext"}, desc="A+=*(S+imm8)+CF, set flags" },
+ { mnem="scc *s+imm8", opcode=0xB7, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSubC","instrNext"}, desc="A-=*(S+imm8)+CF, set flags" },
+ { mnem="cmp *s+imm8", opcode=0xB0, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"alulA","alurT","aluOpSub" ,"instrNext"}, desc="set flags according to A-*(S+imm8)" },
+ { mnem="and *s+imm8", opcode=0xB1, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAnd" ,"instrNext"}, desc="A&=*(S+imm8), set zero flag" },
+ { mnem="ior *s+imm8", opcode=0xB2, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpIor" ,"instrNext"}, desc="A|=*(S+imm8), set zero flag" },
+ { mnem="xor *s+imm8", opcode=0xB3, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpXor" ,"instrNext"}, desc="A^=*(S+imm8), set zero flag" },
+ { mnem="ann *s+imm8", opcode=0xB4, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAnn" ,"instrNext"}, desc="A&=~*(S+imm8), set zero flag" },
+ { mnem="shl *s+imm8", opcode=0xD5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpShl" ,"instrNext"}, desc="A<<=*(S+imm8), set zero flag" },
+ { mnem="shr *s+imm8", opcode=0xD6, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpShr" ,"instrNext"}, desc="A<<=*(S+imm8), set zero flag" },
+ { mnem="rol *s+imm8", opcode=0xD7, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpRol" ,"instrNext"}, desc="A<<<=*(S+imm8), set zero flag" },
+ { mnem="ror *s+imm8", opcode=0xD8, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpRor" ,"instrNext"}, desc="A>>>=*(S+imm8), set zero flag" },
+ { mnem="sra *s+imm8", opcode=0xD9, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSra" ,"instrNext"}, desc="A>>a=*(S+imm8), set zero flag" },
+ { mnem="add b" , opcode=0xA0, {"aluA", "alurB","aluOpAdd" ,"instrNext"}, desc="A+=B, set flags" },
+ { mnem="adc b" , opcode=0x9F, {"aluC", "alurB","aluOpAdd" ,"instrNext"}, desc="C+=B, set flags" },
+ { mnem="sub b" , opcode=0xA1, {"aluA", "alurB","aluOpSub" ,"instrNext"}, desc="A-=B, set flags" },
+ { mnem="sbc b" , opcode=0xB6, {"aluC", "alurB","aluOpSub" ,"instrNext"}, desc="C-=B, set flags" },
+ { mnem="acc b" , opcode=0xB8, {"aluA", "alurB","aluOpAddC","instrNext"}, desc="A+=B+CF, set flags" },
+ { mnem="scc b" , opcode=0xB9, {"aluA", "alurB","aluOpSubC","instrNext"}, desc="A-=B+CF, set flags" },
+ { mnem="cmp b" , opcode=0xA2, {"alulA","alurB","aluOpSub" ,"instrNext"}, desc="set flags according to A-B" },
+ { mnem="and b" , opcode=0xA3, {"aluA", "alurB","aluOpAnd" ,"instrNext"}, desc="A&=B, set zero flag" },
+ { mnem="ior b" , opcode=0xA4, {"aluA", "alurB","aluOpIor" ,"instrNext"}, desc="A|=B, set zero flag" },
+ { mnem="xor b" , opcode=0xA5, {"aluA", "alurB","aluOpXor" ,"instrNext"}, desc="A^=B, set zero flag" },
+ { mnem="ann b" , opcode=0xA6, {"aluA", "alurB","aluOpAnn" ,"instrNext"}, desc="A&=~B, set zero flag" },
+ { mnem="shl b" , opcode=0xDA, {"aluA", "alurB","aluOpShl" ,"instrNext"}, desc="A<<=B, set zero flag" },
+ { mnem="shr b" , opcode=0xDB, {"aluA", "alurB","aluOpShr" ,"instrNext"}, desc="A>>=B, set zero flag" },
+ { mnem="rol b" , opcode=0xDC, {"aluA", "alurB","aluOpRol" ,"instrNext"}, desc="A<<<=B, set zero flag" },
+ { mnem="ror b" , opcode=0xDD, {"aluA", "alurB","aluOpRor" ,"instrNext"}, desc="A>>>=B, set zero flag" },
+ { mnem="sra b" , opcode=0xDE, {"aluA", "alurB","aluOpSra" ,"instrNext"}, desc="A>>a=B, set zero flag" },
+ { mnem="add c" , opcode=0xA7, {"aluA", "alurC","aluOpAdd" ,"instrNext"}, desc="A+=C, set flags" },
+ { mnem="adb c" , opcode=0xBD, {"aluB", "alurC","aluOpAdd" ,"instrNext"}, desc="B+=C, set flags" },
+ { mnem="sub c" , opcode=0xA8, {"aluA", "alurC","aluOpSub" ,"instrNext"}, desc="A-=C, set flags" },
+ { mnem="sbb c" , opcode=0xBC, {"aluB", "alurC","aluOpSub" ,"instrNext"}, desc="B-=C, set flags" },
+ { mnem="acc c" , opcode=0xBA, {"aluA", "alurC","aluOpAddC","instrNext"}, desc="A+=C+CF, set flags" },
+ { mnem="scc c" , opcode=0xBB, {"aluA", "alurC","aluOpSubC","instrNext"}, desc="A-=C+CF, set flags" },
+ { mnem="cmp c" , opcode=0xA9, {"alulA","alurC","aluOpSub" ,"instrNext"}, desc="set flags according to A-C" },
+ { mnem="and c" , opcode=0xAA, {"aluA", "alurC","aluOpAnd" ,"instrNext"}, desc="A&=C, set zero flag" },
+ { mnem="ior c" , opcode=0xAB, {"aluA", "alurC","aluOpIor" ,"instrNext"}, desc="A|=C, set zero flag" },
+ { mnem="xor c" , opcode=0xAC, {"aluA", "alurC","aluOpXor" ,"instrNext"}, desc="A^=C, set zero flag" },
+ { mnem="ann c" , opcode=0xAD, {"aluA", "alurC","aluOpAnn" ,"instrNext"}, desc="A&=~C, set zero flag" },
+ { mnem="shl c" , opcode=0xDF, {"aluA", "alurC","aluOpShl" ,"instrNext"}, desc="A<<=C, set zero flag" },
+ { mnem="shr c" , opcode=0x4D, {"aluA", "alurC","aluOpShr" ,"instrNext"}, desc="A>>=C, set zero flag" },
+ { mnem="rol c" , opcode=0x3E, {"aluA", "alurC","aluOpRol" ,"instrNext"}, desc="A<<<=C, set zero flag" },
+ { mnem="ror c" , opcode=0x3F, {"aluA", "alurC","aluOpRor" ,"instrNext"}, desc="A>>>=C, set zero flag" },
+ { mnem="sra c" , opcode=0x2F, {"aluA", "alurC","aluOpSra" ,"instrNext"}, desc="A>>a=C, set zero flag" },
+ { mnem="adb a" , opcode=0xBE, {"aluB", "alurA","aluOpAdd" ,"instrNext"}, desc="B+=A, set flags" },
+ { mnem="sbb a" , opcode=0xBF, {"aluB", "alurA","aluOpSub" ,"instrNext"}, desc="B-=A, set flags" },
+ { mnem="adc a" , opcode=0x4E, {"aluC", "alurA","aluOpAdd" ,"instrNext"}, desc="C+=A, set flags" },
+ { mnem="sbc a" , opcode=0x4F, {"aluC", "alurA","aluOpSub" ,"instrNext"}, desc="C-=A, set flags" },
{ category = "Jumps", catlet="J" },
{ mnem="jmp imm16" , opcode=0x60, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"jmpAbsUT" }, desc="I=imm16" },
@@ -220,45 +259,45 @@ instructions = {
{ mnem="ppq" , opcode=0x49, {"pop161","instrSub1"}, {"pop162","instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*(----S)" },
{ category = "8-bit Load/Store", catlet="B" },
- { mnem="lda imm8" , opcode=0x20, {"loadImmed", "memSaveA","instrSub1"}, {"instrNext"}, desc="A=imm8" },
- { mnem="ldb imm8" , opcode=0x26, {"loadImmed", "memSaveB","instrSub1"}, {"instrNext"}, desc="B=imm8" },
- { mnem="ldc imm8" , opcode=0x27, {"loadImmed", "memSaveC","instrSub1"}, {"instrNext"}, desc="C=imm8" },
- { mnem="lda *s+imm8", opcode=0x28, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveA","instrSub2"}, {"instrNext"}, desc="A=*s+imm8" },
- { mnem="ldb *s+imm8", opcode=0x29, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveB","instrSub2"}, {"instrNext"}, desc="B=*s+imm8" },
- { mnem="ldc *s+imm8", opcode=0x2A, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveC","instrSub2"}, {"instrNext"}, desc="C=*s+imm8" },
+ { mnem="lda imm8" , opcode=0x20, {"loadImmed", "memSaveA","memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=imm8, update zero flag" },
+ { mnem="ldb imm8" , opcode=0x26, {"loadImmed", "memSaveB","memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=imm8, update zero flag" },
+ { mnem="ldc imm8" , opcode=0x27, {"loadImmed", "memSaveC","memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=imm8, update zero flag" },
+ { mnem="lda *s+imm8", opcode=0x28, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveA","memSaveFlags","instrSub2"}, {"instrNext"}, desc="A=*s+imm8, update zero flag" },
+ { mnem="ldb *s+imm8", opcode=0x29, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveB","memSaveFlags","instrSub2"}, {"instrNext"}, desc="B=*s+imm8, update zero flag" },
+ { mnem="ldc *s+imm8", opcode=0x2A, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveC","memSaveFlags","instrSub2"}, {"instrNext"}, desc="C=*s+imm8, update zero flag" },
{ mnem="sta *s+imm8", opcode=0x96, {"loadImmedT","instrSub1"}, {"storeStackRel","alurA","instrSub2"}, {"instrNext"}, desc="*s+imm8=A" },
{ mnem="stb *s+imm8", opcode=0x97, {"loadImmedT","instrSub1"}, {"storeStackRel","alurB","instrSub2"}, {"instrNext"}, desc="*s+imm8=B" },
{ mnem="stc *s+imm8", opcode=0x98, {"loadImmedT","instrSub1"}, {"storeStackRel","alurC","instrSub2"}, {"instrNext"}, desc="*s+imm8=C" },
- { mnem="lda *imm16" , opcode=0x51, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveA","instrSub3"}, {"instrNext"}, desc="A=*imm16" },
- { mnem="ldb *imm16" , opcode=0x56, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveB","instrSub3"}, {"instrNext"}, desc="B=*imm16" },
- { mnem="ldc *imm16" , opcode=0x57, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveC","instrSub3"}, {"instrNext"}, desc="C=*imm16" },
+ { mnem="lda *imm16" , opcode=0x51, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveA","memSaveFlags","instrSub3"}, {"instrNext"}, desc="A=*imm16, update zero flag" },
+ { mnem="ldb *imm16" , opcode=0x56, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveB","memSaveFlags","instrSub3"}, {"instrNext"}, desc="B=*imm16, update zero flag" },
+ { mnem="ldc *imm16" , opcode=0x57, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveC","memSaveFlags","instrSub3"}, {"instrNext"}, desc="C=*imm16, update zero flag" },
{ mnem="sta *imm16" , opcode=0x50, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurA","instrSub3"}, {"instrNext"}, desc="*imm16=A" },
{ mnem="stb *imm16" , opcode=0x58, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurB","instrSub3"}, {"instrNext"}, desc="*imm16=B" },
{ mnem="stc *imm16" , opcode=0x59, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurC","instrSub3"}, {"instrNext"}, desc="*imm16=C" },
- { mnem="sta *p" , opcode=0x52, {"adrlP","storeReg","alurA", "instrSub1"}, {"instrNext"}, desc="*P=A" },
- { mnem="stb *p" , opcode=0x5A, {"adrlP","storeReg","alurB", "instrSub1"}, {"instrNext"}, desc="*P=B" },
- { mnem="stc *p" , opcode=0x5B, {"adrlP","storeReg","alurC", "instrSub1"}, {"instrNext"}, desc="*P=C" },
- { mnem="sta *q" , opcode=0x54, {"adrlQ","storeReg","alurA", "instrSub1"}, {"instrNext"}, desc="*Q=A" },
- { mnem="stb *q" , opcode=0x5C, {"adrlQ","storeReg","alurB", "instrSub1"}, {"instrNext"}, desc="*Q=B" },
- { mnem="stc *q" , opcode=0x5D, {"adrlQ","storeReg","alurC", "instrSub1"}, {"instrNext"}, desc="*Q=C" },
- { mnem="lda *p" , opcode=0x53, {"adrlP","loadReg","memSaveA", "instrSub1"}, {"instrNext"}, desc="A=*P" },
- { mnem="ldb *p" , opcode=0x5E, {"adrlP","loadReg","memSaveB", "instrSub1"}, {"instrNext"}, desc="B=*P" },
- { mnem="ldc *p" , opcode=0x5F, {"adrlP","loadReg","memSaveC", "instrSub1"}, {"instrNext"}, desc="C=*P" },
- { mnem="lda *q" , opcode=0x55, {"adrlQ","loadReg","memSaveA", "instrSub1"}, {"instrNext"}, desc="A=*Q" },
- { mnem="ldb *q" , opcode=0x61, {"adrlQ","loadReg","memSaveB", "instrSub1"}, {"instrNext"}, desc="B=*Q" },
- { mnem="ldc *q" , opcode=0x62, {"adrlQ","loadReg","memSaveC", "instrSub1"}, {"instrNext"}, desc="C=*Q" },
- { mnem="sta *p++" , opcode=0xC0, {"adrlP","storeReg","alurA", "incP","instrSub1"}, {"instrNext"}, desc="*P++=A" },
- { mnem="stb *p++" , opcode=0xC1, {"adrlP","storeReg","alurB", "incP","instrSub1"}, {"instrNext"}, desc="*P++=B" },
- { mnem="stc *p++" , opcode=0xC2, {"adrlP","storeReg","alurC", "incP","instrSub1"}, {"instrNext"}, desc="*P++=C" },
- { mnem="sta *q++" , opcode=0xC3, {"adrlQ","storeReg","alurA", "incQ","instrSub1"}, {"instrNext"}, desc="*Q++=A" },
- { mnem="stb *q++" , opcode=0xC4, {"adrlQ","storeReg","alurB", "incQ","instrSub1"}, {"instrNext"}, desc="*Q++=B" },
- { mnem="stc *q++" , opcode=0xC5, {"adrlQ","storeReg","alurC", "incQ","instrSub1"}, {"instrNext"}, desc="*Q++=C" },
- { mnem="lda *p++" , opcode=0xC6, {"adrlP","loadReg","memSaveA","incP","instrSub1"}, {"instrNext"}, desc="A=*P++" },
- { mnem="ldb *p++" , opcode=0xC7, {"adrlP","loadReg","memSaveB","incP","instrSub1"}, {"instrNext"}, desc="B=*P++" },
- { mnem="ldc *p++" , opcode=0xC8, {"adrlP","loadReg","memSaveC","incP","instrSub1"}, {"instrNext"}, desc="C=*P++" },
- { mnem="lda *q++" , opcode=0xC9, {"adrlQ","loadReg","memSaveA","incQ","instrSub1"}, {"instrNext"}, desc="A=*Q++" },
- { mnem="ldb *q++" , opcode=0xCA, {"adrlQ","loadReg","memSaveB","incQ","instrSub1"}, {"instrNext"}, desc="B=*Q++" },
- { mnem="ldc *q++" , opcode=0xCB, {"adrlQ","loadReg","memSaveC","incQ","instrSub1"}, {"instrNext"}, desc="C=*Q++" },
+ { mnem="sta *p" , opcode=0x52, {"adrlP","storeReg","alurA", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P=A" },
+ { mnem="stb *p" , opcode=0x5A, {"adrlP","storeReg","alurB", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P=B" },
+ { mnem="stc *p" , opcode=0x5B, {"adrlP","storeReg","alurC", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P=C" },
+ { mnem="sta *q" , opcode=0x54, {"adrlQ","storeReg","alurA", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q=A" },
+ { mnem="stb *q" , opcode=0x5C, {"adrlQ","storeReg","alurB", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q=B" },
+ { mnem="stc *q" , opcode=0x5D, {"adrlQ","storeReg","alurC", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q=C" },
+ { mnem="lda *p" , opcode=0x53, {"adrlP","loadReg","memSaveA", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*P, update zero flag" },
+ { mnem="ldb *p" , opcode=0x5E, {"adrlP","loadReg","memSaveB", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*P, update zero flag" },
+ { mnem="ldc *p" , opcode=0x5F, {"adrlP","loadReg","memSaveC", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*P, update zero flag" },
+ { mnem="lda *q" , opcode=0x55, {"adrlQ","loadReg","memSaveA", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*Q, update zero flag" },
+ { mnem="ldb *q" , opcode=0x61, {"adrlQ","loadReg","memSaveB", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*Q, update zero flag" },
+ { mnem="ldc *q" , opcode=0x62, {"adrlQ","loadReg","memSaveC", "memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*Q, update zero flag" },
+ { mnem="sta *p++" , opcode=0xC0, {"adrlP","storeReg","alurA", "incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P++=A" },
+ { mnem="stb *p++" , opcode=0xC1, {"adrlP","storeReg","alurB", "incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P++=B" },
+ { mnem="stc *p++" , opcode=0xC2, {"adrlP","storeReg","alurC", "incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P++=C" },
+ { mnem="sta *q++" , opcode=0xC3, {"adrlQ","storeReg","alurA", "incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q++=A" },
+ { mnem="stb *q++" , opcode=0xC4, {"adrlQ","storeReg","alurB", "incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q++=B" },
+ { mnem="stc *q++" , opcode=0xC5, {"adrlQ","storeReg","alurC", "incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q++=C" },
+ { mnem="lda *p++" , opcode=0xC6, {"adrlP","loadReg","memSaveA","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*P++, update zero flag" },
+ { mnem="ldb *p++" , opcode=0xC7, {"adrlP","loadReg","memSaveB","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*P++, update zero flag" },
+ { mnem="ldc *p++" , opcode=0xC8, {"adrlP","loadReg","memSaveC","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*P++, update zero flag" },
+ { mnem="lda *q++" , opcode=0xC9, {"adrlQ","loadReg","memSaveA","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*Q++, update zero flag" },
+ { mnem="ldb *q++" , opcode=0xCA, {"adrlQ","loadReg","memSaveB","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*Q++, update zero flag" },
+ { mnem="ldc *q++" , opcode=0xCB, {"adrlQ","loadReg","memSaveC","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*Q++, update zero flag" },
{ category = "16-bit Load/Store", catlet="W" },
{ mnem="ldp imm16" , opcode=0x21, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=imm16" },
@@ -285,24 +324,24 @@ instructions = {
{ mnem="stq *p++" , opcode=0xCF, {"adrlP","store161","alurQH","instrSub1"}, {"adrlP","store162","alurQL","instrSub2","incP2"}, {"instrNext"}, desc="*P++++=Q" },
{ category = "Moves", catlet="M" },
- { mnem="lda b" , opcode=0x80, {"alurB" ,"aluAdd","aluSaveA","instrNext"}, desc="A=B" },
- { mnem="lda c" , opcode=0x81, {"alurC" ,"aluAdd","aluSaveA","instrNext"}, desc="A=C" },
- { mnem="ldb a" , opcode=0x82, {"alurA" ,"aluAdd","aluSaveB","instrNext"}, desc="B=A" },
- { mnem="ldb c" , opcode=0x83, {"alurC" ,"aluAdd","aluSaveB","instrNext"}, desc="B=C" },
- { mnem="ldc a" , opcode=0x84, {"alurA" ,"aluAdd","aluSaveC","instrNext"}, desc="C=A" },
- { mnem="ldc b" , opcode=0x85, {"alurB" ,"aluAdd","aluSaveC","instrNext"}, desc="C=B" },
- { mnem="lda pl" , opcode=0x86, {"alurPL","aluAdd","aluSaveA","instrNext"}, desc="A=P&FF" },
- { mnem="lda ph" , opcode=0x87, {"alurPH","aluAdd","aluSaveA","instrNext"}, desc="A=P>>8" },
- { mnem="lda ql" , opcode=0x88, {"alurQL","aluAdd","aluSaveA","instrNext"}, desc="A=Q&FF" },
- { mnem="lda qh" , opcode=0x89, {"alurQH","aluAdd","aluSaveA","instrNext"}, desc="A=Q>>8" },
- { mnem="ldp q" , opcode=0x8A, {"adwlQ" ,"adwSaveP","instrNext"}, desc="P=Q" },
- { mnem="ldp s" , opcode=0x8B, {"adwlS" ,"adwSaveP","instrNext"}, desc="P=S" },
- { mnem="ldp v" , opcode=0x8C, {"adwlV" ,"adwSaveP","instrNext"}, desc="P=V" },
- { mnem="ldp i" , opcode=0x8D, {"adwlI" ,"adwSaveP","instrNext"}, desc="P=I" },
- { mnem="ldp cb" , opcode=0x91, {"adwrCB","adwSaveP","instrNext"}, desc="P=C<<8+B" },
- { mnem="ldq p" , opcode=0x8E, {"adwlP" ,"adwSaveQ","instrNext"}, desc="Q=P" },
- { mnem="lds p" , opcode=0x8F, {"adwlP" ,"adwSaveS","instrNext"}, desc="S=P" },
- { mnem="ldv p" , opcode=0x90, {"adwlP" ,"adwSaveV","instrNext"}, desc="V=P" },
+ { mnem="lda b" , opcode=0x80, {"alurB" ,"aluOpMov","aluSaveA","instrNext"}, desc="A=B" },
+ { mnem="lda c" , opcode=0x81, {"alurC" ,"aluOpMov","aluSaveA","instrNext"}, desc="A=C" },
+ { mnem="ldb a" , opcode=0x82, {"alurA" ,"aluOpMov","aluSaveB","instrNext"}, desc="B=A" },
+ { mnem="ldb c" , opcode=0x83, {"alurC" ,"aluOpMov","aluSaveB","instrNext"}, desc="B=C" },
+ { mnem="ldc a" , opcode=0x84, {"alurA" ,"aluOpMov","aluSaveC","instrNext"}, desc="C=A" },
+ { mnem="ldc b" , opcode=0x85, {"alurB" ,"aluOpMov","aluSaveC","instrNext"}, desc="C=B" },
+ { mnem="lda pl" , opcode=0x86, {"alurPL","aluOpMov","aluSaveA","instrNext"}, desc="A=P&FF" },
+ { mnem="lda ph" , opcode=0x87, {"alurPH","aluOpMov","aluSaveA","instrNext"}, desc="A=P>>8" },
+ { mnem="lda ql" , opcode=0x88, {"alurQL","aluOpMov","aluSaveA","instrNext"}, desc="A=Q&FF" },
+ { mnem="lda qh" , opcode=0x89, {"alurQH","aluOpMov","aluSaveA","instrNext"}, desc="A=Q>>8" },
+ { mnem="ldp q" , opcode=0x8A, {"adwlQ" , "adwSaveP","instrNext"}, desc="P=Q" },
+ { mnem="ldp s" , opcode=0x8B, {"adwlS" , "adwSaveP","instrNext"}, desc="P=S" },
+ { mnem="ldp v" , opcode=0x8C, {"adwlV" , "adwSaveP","instrNext"}, desc="P=V" },
+ { mnem="ldp i" , opcode=0x8D, {"adwlI" , "adwSaveP","instrNext"}, desc="P=I" },
+ { mnem="ldp cb" , opcode=0x91, {"adwrCB", "adwSaveP","instrNext"}, desc="P=C<<8+B" },
+ { mnem="ldq p" , opcode=0x8E, {"adwlP" , "adwSaveQ","instrNext"}, desc="Q=P" },
+ { mnem="lds p" , opcode=0x8F, {"adwlP" , "adwSaveS","instrNext"}, desc="S=P" },
+ { mnem="ldv p" , opcode=0x90, {"adwlP" , "adwSaveV","instrNext"}, desc="V=P" },
},
}