278 lines
9.2 KiB
Plaintext
278 lines
9.2 KiB
Plaintext
instructionList.txt
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List of all instructions in the 8608 architecture.
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Instructions are encoded as the opcode, followed by any immediate values.
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16-bit immediates are encoded in big-endian byte order.
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Each instruction is described in order of: Mnemonic, Opcode, Clock cycles, Description
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Control (C):
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rst 00 1 Clear all registers and set I=0
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hlt F0 1 Halt non-interrupt execution
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run F1 1 Resume non-interrupt execution
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brk F3 1 Trigger interrupt
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irt F4 1 Return from interrupt
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nop FF 1 Do nothing
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ien F5 1 Enbale interrupts
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idi F6 1 Disable interrupts
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16-bit Inc/Dec (I):
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inc p 12 1 P++
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dec p 15 1 P--
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inc q 13 1 Q++
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dec q 16 1 Q--
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8-bit Unary (U):
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inc a 10 1 A++, set flags
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dec a 11 1 A--, set flags
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icc a 1B 1 A+=CF, set flags
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inc b 19 1 B++, set flags
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dec b 1A 1 B--, set flags
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icc b 1C 1 B+=CF, set flags
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inc c 17 1 C++, set flags
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dec c 18 1 C--, set flags
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icc c 1D 1 C+=CF, set flags
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tst a 14 1 Set flags according to A-0
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tst b 1E 1 Set flags according to B-0
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tst c 1F 1 Set flags according to C-0
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inc *s+imm8 2B 4 *(S+imm8)++, set flags
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dec *s+imm8 2C 4 *(S+imm8)--, set flags
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icc *s+imm8 2D 4 *(S+imm8)+=CF, set flags
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tst *s+imm8 2E 3 Set flags according to *(S+imm8)-0
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16-bit Arithmetic (X):
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adp imm8 4A 2 P+=imm8 signed
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adq imm8 4B 2 Q+=imm8 signed
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ads imm8 4C 2 S+=imm8 signed
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adp b E6 1 P+=B signed
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adq b E7 1 Q+=B signed
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ads b E8 1 S+=B signed
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8-bit Arithmetic/Logic (A):
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add imm8 24 2 A+=imm8, set flags
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adb imm8 72 2 B+=imm8, set flags
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adc imm8 73 2 C+=imm8, set flags
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acc imm8 78 2 A+=imm8+CF, set flags
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cmp imm8 71 2 set flags according to A-imm8
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and imm8 74 2 A&=imm8, set zero flag
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ior imm8 75 2 A|=imm8, set zero flag
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xor imm8 76 2 A^=imm8, set zero flag
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shl imm8 D0 2 A<<=imm8, set zero flag
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shr imm8 D1 2 A>>=imm8, set zero flag
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rol imm8 D2 2 A<<<=imm8, set zero flag
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ror imm8 D3 2 A>>>=imm8, set zero flag
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sra imm8 D4 2 A>>a=imm8, set zero flag
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add *s+imm8 AE 3 A+=*(S+imm8), set flags
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adb *s+imm8 9B 3 B+=*(S+imm8), set flags
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adc *s+imm8 9C 3 C+=*(S+imm8), set flags
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sub *s+imm8 AF 3 A-=*(S+imm8), set flags
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sbb *s+imm8 9D 3 B-=*(S+imm8), set flags
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sbc *s+imm8 9E 3 C-=*(S+imm8), set flags
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acc *s+imm8 B5 3 A+=*(S+imm8)+CF, set flags
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scc *s+imm8 B7 3 A-=*(S+imm8)+CF, set flags
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cmp *s+imm8 B0 3 set flags according to A-*(S+imm8)
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and *s+imm8 B1 3 A&=*(S+imm8), set zero flag
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ior *s+imm8 B2 3 A|=*(S+imm8), set zero flag
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xor *s+imm8 B3 3 A^=*(S+imm8), set zero flag
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shl *s+imm8 D5 3 A<<=*(S+imm8), set zero flag
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shr *s+imm8 D6 3 A<<=*(S+imm8), set zero flag
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rol *s+imm8 D7 3 A<<<=*(S+imm8), set zero flag
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ror *s+imm8 D8 3 A>>>=*(S+imm8), set zero flag
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sra *s+imm8 D9 3 A>>a=*(S+imm8), set zero flag
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add b A0 1 A+=B, set flags
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adc b 9F 1 C+=B, set flags
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sub b A1 1 A-=B, set flags
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sbc b B6 1 C-=B, set flags
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acc b B8 1 A+=B+CF, set flags
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scc b B9 1 A-=B+CF, set flags
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cmp b A2 1 set flags according to A-B
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and b A3 1 A&=B, set zero flag
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ior b A4 1 A|=B, set zero flag
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xor b A5 1 A^=B, set zero flag
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shl b DA 1 A<<=B, set zero flag
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shr b DB 1 A>>=B, set zero flag
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rol b DC 1 A<<<=B, set zero flag
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ror b DD 1 A>>>=B, set zero flag
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sra b DE 1 A>>a=B, set zero flag
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add c A7 1 A+=C, set flags
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adb c BD 1 B+=C, set flags
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sub c A8 1 A-=C, set flags
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sbb c BC 1 B-=C, set flags
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acc c BA 1 A+=C+CF, set flags
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scc c BB 1 A-=C+CF, set flags
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cmp c A9 1 set flags according to A-C
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and c AA 1 A&=C, set zero flag
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ior c AB 1 A|=C, set zero flag
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xor c AC 1 A^=C, set zero flag
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shl c DF 1 A<<=C, set zero flag
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shr c 4D 1 A>>=C, set zero flag
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rol c 3E 1 A<<<=C, set zero flag
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ror c 3F 1 A>>>=C, set zero flag
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sra c 2F 1 A>>a=C, set zero flag
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adb a BE 1 B+=A, set flags
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sbb a BF 1 B-=A, set flags
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adc a 4E 1 C+=A, set flags
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sbc a 4F 1 C-=A, set flags
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Jumps (J):
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jmp imm16 60 3 I=imm16
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jsr imm16 63 3 I=imm16, Q=I
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jss imm16 E2 5 I=imm16, *(S++++)=I-1
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jmp p 64 1 I=P
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jmp q 66 1 I=Q
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jsr p 65 1 I=P, Q=I
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jsr q 67 1 I=Q, Q=I
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jss p E4 3 I=P, *(S++++)=I-1
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jss q E5 3 I=Q, *(S++++)=I-1
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rts E1 3 I=*(----S)+1
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jpr imm8 31 2 I+=imm8
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jnz imm8 30 2 I+=imm8 if !Zero
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jpz imm8 32 2 I+=imm8 if Zero
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jlt imm8 33 2 I+=imm8 if !Carry
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jge imm8 34 2 I+=imm8 if Carry
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jgt imm8 35 2 I+=imm8 if !Zero & Carry
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jle imm8 36 2 I+=imm8 if Zero | !Carry
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Stack (S):
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psh a 40 2 *(S++)=A
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psh b 44 2 *(S++)=B
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psh c 45 2 *(S++)=C
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psh f E9 2 *(S++)=F
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psh p 41 3 *(S++++)=P
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psh q 46 3 *(S++++)=Q
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pop a 42 2 A=*(--S)
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pop b 47 2 B=*(--S)
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pop c 48 2 C=*(--S)
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pop f EA 2 F=*(--S)
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pop p 43 3 P=*(----S)
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pop q 49 3 Q=*(----S)
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psh imm8 3B 3 *(S++)=imm8
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phw imm16 3C 5 *(S++++)=imm16
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8-bit Load/Store (B):
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lda imm8 20 2 A=imm8, update zero flag
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ldb imm8 26 2 B=imm8, update zero flag
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ldc imm8 27 2 C=imm8, update zero flag
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lda *s+imm8 28 3 A=*s+imm8, update zero flag
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ldb *s+imm8 29 3 B=*s+imm8, update zero flag
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ldc *s+imm8 2A 3 C=*s+imm8, update zero flag
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sta *s+imm8 96 3 *s+imm8=A
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stb *s+imm8 97 3 *s+imm8=B
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stc *s+imm8 98 3 *s+imm8=C
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lda *imm16 51 4 A=*imm16, update zero flag
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ldb *imm16 56 4 B=*imm16, update zero flag
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ldc *imm16 57 4 C=*imm16, update zero flag
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sta *imm16 50 4 *imm16=A
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stb *imm16 58 4 *imm16=B
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stc *imm16 59 4 *imm16=C
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lda *p+imm16 01 4 A=*P+imm16, update zero flag
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ldb *p+imm16 F7 4 B=*P+imm16, update zero flag
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ldc *p+imm16 FE 4 C=*P+imm16, update zero flag
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lda *q+imm16 EB 4 A=*Q+imm16, update zero flag
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ldb *q+imm16 08 4 B=*Q+imm16, update zero flag
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ldc *q+imm16 09 4 C=*Q+imm16, update zero flag
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sta *p+imm16 0A 4 *P+imm16=A
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stb *p+imm16 0B 4 *P+imm16=B
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stc *p+imm16 0C 4 *P+imm16=C
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sta *q+imm16 0D 4 *Q+imm16=A
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stb *q+imm16 0E 4 *Q+imm16=B
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stc *q+imm16 0F 4 *Q+imm16=C
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lda *p 53 2 A=*P, update zero flag
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ldb *p 5E 2 B=*P, update zero flag
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ldc *p 5F 2 C=*P, update zero flag
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lda *q 55 2 A=*Q, update zero flag
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ldb *q 61 2 B=*Q, update zero flag
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ldc *q 62 2 C=*Q, update zero flag
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sta *p 52 2 *P=A
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stb *p 5A 2 *P=B
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stc *p 5B 2 *P=C
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sta *q 54 2 *Q=A
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stb *q 5C 2 *Q=B
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stc *q 5D 2 *Q=C
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lda *p++ C6 2 A=*P++, update zero flag
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ldb *p++ C7 2 B=*P++, update zero flag
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ldc *p++ C8 2 C=*P++, update zero flag
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lda *q++ C9 2 A=*Q++, update zero flag
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ldb *q++ CA 2 B=*Q++, update zero flag
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ldc *q++ CB 2 C=*Q++, update zero flag
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sta *p++ C0 2 *P++=A
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stb *p++ C1 2 *P++=B
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stc *p++ C2 2 *P++=C
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sta *q++ C3 2 *Q++=A
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stb *q++ C4 2 *Q++=B
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stc *q++ C5 2 *Q++=C
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16-bit Load/Store (W):
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ldp imm16 21 3 P=imm16
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ldq imm16 23 3 Q=imm16
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lds imm16 25 3 S=imm16
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ldv imm16 22 3 V=imm16
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ldp *s+imm8 7A 4 P=*S+imm8
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ldq *s+imm8 7B 4 Q=*S+imm8
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stp *s+imm8 7E 4 *S+imm8=P
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stq *s+imm8 7F 4 *S+imm8=Q
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ldp *imm16 68 5 P=*imm16
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ldq *imm16 6A 5 Q=*imm16
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stp *imm16 6C 5 *imm16=P
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stq *imm16 6E 5 *imm16=Q
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ldp *p+imm16 EC 5 P=*P+imm16
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ldq *p+imm16 EE 5 Q=*P+imm16
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ldp *q+imm16 F8 5 P=*Q+imm16
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ldq *q+imm16 FA 5 Q=*Q+imm16
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stq *p+imm16 06 5 *P+imm16=Q
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stp *q+imm16 FC 5 *Q+imm16=P
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ldp *p 92 3 P=*P
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ldq *p 93 3 Q=*P
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ldp *q 94 3 P=*Q
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ldq *q 95 3 Q=*Q
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stp *q 7C 3 *Q=P
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stq *p 7D 3 *P=Q
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ldq *p++ CC 3 Q=*P++++
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ldp *q++ CD 3 P=*Q++++
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stp *q++ CE 3 *Q++++=P
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stq *p++ CF 3 *P++++=Q
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Moves (M):
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lda b 80 1 A=B
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lda c 81 1 A=C
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ldb a 82 1 B=A
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ldb c 83 1 B=C
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ldc a 84 1 C=A
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ldc b 85 1 C=B
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lda pl 86 1 A=P&FF
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lda ph 87 1 A=P>>8
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lda ql 88 1 A=Q&FF
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lda qh 89 1 A=Q>>8
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ldb pl 37 1 B=P&FF
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ldc ph 38 1 C=P>>8
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ldb ql 39 1 B=Q&FF
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ldc qh 3A 1 C=Q>>8
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ldp q 8A 1 P=Q
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ldp s 8B 1 P=S
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ldp v 8C 1 P=V
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ldp i 8D 1 P=I
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ldp cb 91 1 P=(C<<8)+B
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ldq cb E0 1 Q=(C<<8)+B
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ldq p 8E 1 Q=P
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lds p 8F 1 S=P
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ldv p 90 1 V=P
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Opcodes used: 244/255
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0123456789ABCDEF
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00 | CB----WWBBBBBBBB
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10 | UUIIUIIUUUUUUUUU
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20 | BWWWAWBBBBBUUUUA
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30 | JJJJJJJMMMMSSSAA
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40 | SSSSSSSSSSXXXAAA
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50 | BBBBBBBBBBBBBBBB
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60 | JBBJJJJJWWWWWWWW
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70 | -AAAAAA-A-WWWWWW
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80 | MMMMMMMMMMMMMMMM
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90 | MMWWWWBBB--AAAAA
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A0 | AAAAAA-AAAAAA-AA
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B0 | AAAA-AAAAAAAAAAA
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C0 | BBBBBBBBBBBBWWWW
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D0 | AAAAAAAAAAAAAAAA
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E0 | MJJJJJXXXSSBWWWW
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F0 | CCCCCCCBWWWWWWBC
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