fixed pixel to use new callback system
This commit is contained in:
@ -1,179 +1,179 @@
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datablock fxDTSBrickData(LogicGate_8bitAdder_Data)
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{
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brickFile = $LuaLogic::Path @ "bricks/blb/8bitAdder.blb";
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category = "Logic Bricks";
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subCategory = "Math";
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uiName = "8bit Adder";
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iconName = $LuaLogic::Path @ "icons/8bit Adder";
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hasPrint = 1;
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printAspectRatio = "Logic";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicUIName = "8bit Adder";
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logicUIDesc = "";
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logicUpdate = "return function(gate) local c = bool_to_int[gate.ports[17].state] " @
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"local a = 0 " @
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"local b = 0 " @
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"for i = 1, 8 do " @
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"a = bool_to_int[gate.ports[i].state] " @
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"b = bool_to_int[gate.ports[i+8].state] " @
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"gate.ports[i+17]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
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"c = bit.bor(bit.band(a, b), bit.band(c, bit.bor(a, b))) " @
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"end " @
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"gate.ports[26]:setstate(c == 1) end";
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numLogicPorts = 26;
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logicPortType[0] = 1;
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logicPortPos[0] = "-1 -1 0";
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logicPortDir[0] = 3;
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logicPortCauseUpdate[0] = true;
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logicPortUIName[0] = "A0";
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logicPortType[1] = 1;
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logicPortPos[1] = "-3 -1 0";
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logicPortDir[1] = 3;
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logicPortCauseUpdate[1] = true;
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logicPortUIName[1] = "A1";
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logicPortType[2] = 1;
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logicPortPos[2] = "-5 -1 0";
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logicPortDir[2] = 3;
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logicPortCauseUpdate[2] = true;
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logicPortUIName[2] = "A2";
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logicPortType[3] = 1;
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logicPortPos[3] = "-7 -1 0";
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logicPortDir[3] = 3;
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logicPortCauseUpdate[3] = true;
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logicPortUIName[3] = "A3";
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logicPortType[4] = 1;
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logicPortPos[4] = "-9 -1 0";
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logicPortDir[4] = 3;
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logicPortCauseUpdate[4] = true;
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logicPortUIName[4] = "A4";
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logicPortType[5] = 1;
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logicPortPos[5] = "-11 -1 0";
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logicPortDir[5] = 3;
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logicPortCauseUpdate[5] = true;
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logicPortUIName[5] = "A5";
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logicPortType[6] = 1;
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logicPortPos[6] = "-13 -1 0";
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logicPortDir[6] = 3;
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logicPortCauseUpdate[6] = true;
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logicPortUIName[6] = "A6";
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logicPortType[7] = 1;
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logicPortPos[7] = "-15 -1 0";
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logicPortDir[7] = 3;
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logicPortCauseUpdate[7] = true;
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logicPortUIName[7] = "A7";
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logicPortType[8] = 1;
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logicPortPos[8] = "15 -1 0";
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logicPortDir[8] = 3;
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logicPortCauseUpdate[8] = true;
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logicPortUIName[8] = "B0";
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logicPortType[9] = 1;
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logicPortPos[9] = "13 -1 0";
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logicPortDir[9] = 3;
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logicPortCauseUpdate[9] = true;
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logicPortUIName[9] = "B1";
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logicPortType[10] = 1;
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logicPortPos[10] = "11 -1 0";
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logicPortDir[10] = 3;
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logicPortCauseUpdate[10] = true;
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logicPortUIName[10] = "B2";
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logicPortType[11] = 1;
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logicPortPos[11] = "9 -1 0";
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logicPortDir[11] = 3;
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logicPortCauseUpdate[11] = true;
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logicPortUIName[11] = "B3";
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logicPortType[12] = 1;
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logicPortPos[12] = "7 -1 0";
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logicPortDir[12] = 3;
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logicPortCauseUpdate[12] = true;
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logicPortUIName[12] = "B4";
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logicPortType[13] = 1;
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logicPortPos[13] = "5 -1 0";
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logicPortDir[13] = 3;
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logicPortCauseUpdate[13] = true;
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logicPortUIName[13] = "B5";
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logicPortType[14] = 1;
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logicPortPos[14] = "3 -1 0";
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logicPortDir[14] = 3;
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logicPortCauseUpdate[14] = true;
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logicPortUIName[14] = "B6";
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logicPortType[15] = 1;
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logicPortPos[15] = "1 -1 0";
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logicPortDir[15] = 3;
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logicPortCauseUpdate[15] = true;
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logicPortUIName[15] = "B7";
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logicPortType[16] = 1;
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logicPortPos[16] = "15 -1 0";
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logicPortDir[16] = 2;
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logicPortCauseUpdate[16] = true;
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logicPortUIName[16] = "Carry In";
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logicPortType[17] = 0;
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logicPortPos[17] = "15 1 0";
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logicPortDir[17] = 1;
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logicPortUIName[17] = "Sum0";
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logicPortType[18] = 0;
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logicPortPos[18] = "13 1 0";
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logicPortDir[18] = 1;
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logicPortUIName[18] = "Sum1";
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logicPortType[19] = 0;
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logicPortPos[19] = "11 1 0";
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logicPortDir[19] = 1;
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logicPortUIName[19] = "Sum2";
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logicPortType[20] = 0;
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logicPortPos[20] = "9 1 0";
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logicPortDir[20] = 1;
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logicPortUIName[20] = "Sum3";
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logicPortType[21] = 0;
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logicPortPos[21] = "7 1 0";
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logicPortDir[21] = 1;
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logicPortUIName[21] = "Sum4";
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logicPortType[22] = 0;
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logicPortPos[22] = "5 1 0";
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logicPortDir[22] = 1;
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logicPortUIName[22] = "Sum5";
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logicPortType[23] = 0;
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logicPortPos[23] = "3 1 0";
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logicPortDir[23] = 1;
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logicPortUIName[23] = "Sum6";
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logicPortType[24] = 0;
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logicPortPos[24] = "1 1 0";
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logicPortDir[24] = 1;
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logicPortUIName[24] = "Sum7";
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logicPortType[25] = 0;
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logicPortPos[25] = "-15 -1 0";
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logicPortDir[25] = 0;
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logicPortUIName[25] = "Carry Out";
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};
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lualogic_registergatedefinition("LogicGate_8bitAdder_Data");
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datablock fxDTSBrickData(LogicGate_8bitAdder_Data)
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{
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brickFile = $LuaLogic::Path @ "bricks/blb/8bitAdder.blb";
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category = "Logic Bricks";
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subCategory = "Math";
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uiName = "8bit Adder";
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iconName = $LuaLogic::Path @ "icons/8bit Adder";
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hasPrint = 1;
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printAspectRatio = "Logic";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicUIName = "8bit Adder";
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logicUIDesc = "";
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logicUpdate = "return function(gate) local c = bool_to_int[gate.ports[17].state] " @
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"local a = 0 " @
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"local b = 0 " @
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"for i = 1, 8 do " @
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"a = bool_to_int[gate.ports[i].state] " @
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"b = bool_to_int[gate.ports[i+8].state] " @
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"gate.ports[i+17]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
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"c = bit.bor(bit.band(a, b), bit.band(c, bit.bor(a, b))) " @
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"end " @
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"gate.ports[26]:setstate(c == 1) end";
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numLogicPorts = 26;
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logicPortType[0] = 1;
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logicPortPos[0] = "-1 -1 0";
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logicPortDir[0] = 3;
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logicPortCauseUpdate[0] = true;
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logicPortUIName[0] = "A0";
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logicPortType[1] = 1;
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logicPortPos[1] = "-3 -1 0";
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logicPortDir[1] = 3;
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logicPortCauseUpdate[1] = true;
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logicPortUIName[1] = "A1";
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logicPortType[2] = 1;
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logicPortPos[2] = "-5 -1 0";
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logicPortDir[2] = 3;
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logicPortCauseUpdate[2] = true;
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logicPortUIName[2] = "A2";
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logicPortType[3] = 1;
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logicPortPos[3] = "-7 -1 0";
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logicPortDir[3] = 3;
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logicPortCauseUpdate[3] = true;
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logicPortUIName[3] = "A3";
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logicPortType[4] = 1;
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logicPortPos[4] = "-9 -1 0";
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logicPortDir[4] = 3;
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logicPortCauseUpdate[4] = true;
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logicPortUIName[4] = "A4";
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logicPortType[5] = 1;
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logicPortPos[5] = "-11 -1 0";
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logicPortDir[5] = 3;
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logicPortCauseUpdate[5] = true;
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logicPortUIName[5] = "A5";
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logicPortType[6] = 1;
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logicPortPos[6] = "-13 -1 0";
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logicPortDir[6] = 3;
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logicPortCauseUpdate[6] = true;
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logicPortUIName[6] = "A6";
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logicPortType[7] = 1;
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logicPortPos[7] = "-15 -1 0";
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logicPortDir[7] = 3;
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logicPortCauseUpdate[7] = true;
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logicPortUIName[7] = "A7";
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logicPortType[8] = 1;
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logicPortPos[8] = "15 -1 0";
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logicPortDir[8] = 3;
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logicPortCauseUpdate[8] = true;
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logicPortUIName[8] = "B0";
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logicPortType[9] = 1;
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logicPortPos[9] = "13 -1 0";
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logicPortDir[9] = 3;
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logicPortCauseUpdate[9] = true;
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logicPortUIName[9] = "B1";
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logicPortType[10] = 1;
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logicPortPos[10] = "11 -1 0";
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logicPortDir[10] = 3;
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logicPortCauseUpdate[10] = true;
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logicPortUIName[10] = "B2";
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logicPortType[11] = 1;
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logicPortPos[11] = "9 -1 0";
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logicPortDir[11] = 3;
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logicPortCauseUpdate[11] = true;
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logicPortUIName[11] = "B3";
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logicPortType[12] = 1;
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logicPortPos[12] = "7 -1 0";
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logicPortDir[12] = 3;
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logicPortCauseUpdate[12] = true;
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logicPortUIName[12] = "B4";
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logicPortType[13] = 1;
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logicPortPos[13] = "5 -1 0";
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logicPortDir[13] = 3;
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logicPortCauseUpdate[13] = true;
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logicPortUIName[13] = "B5";
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logicPortType[14] = 1;
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logicPortPos[14] = "3 -1 0";
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logicPortDir[14] = 3;
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logicPortCauseUpdate[14] = true;
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logicPortUIName[14] = "B6";
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logicPortType[15] = 1;
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logicPortPos[15] = "1 -1 0";
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logicPortDir[15] = 3;
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logicPortCauseUpdate[15] = true;
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logicPortUIName[15] = "B7";
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logicPortType[16] = 1;
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logicPortPos[16] = "15 -1 0";
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logicPortDir[16] = 2;
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logicPortCauseUpdate[16] = true;
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logicPortUIName[16] = "Carry In";
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logicPortType[17] = 0;
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logicPortPos[17] = "15 1 0";
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logicPortDir[17] = 1;
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logicPortUIName[17] = "Sum0";
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logicPortType[18] = 0;
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logicPortPos[18] = "13 1 0";
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logicPortDir[18] = 1;
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logicPortUIName[18] = "Sum1";
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logicPortType[19] = 0;
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logicPortPos[19] = "11 1 0";
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logicPortDir[19] = 1;
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logicPortUIName[19] = "Sum2";
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logicPortType[20] = 0;
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logicPortPos[20] = "9 1 0";
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logicPortDir[20] = 1;
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logicPortUIName[20] = "Sum3";
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logicPortType[21] = 0;
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logicPortPos[21] = "7 1 0";
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logicPortDir[21] = 1;
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logicPortUIName[21] = "Sum4";
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logicPortType[22] = 0;
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logicPortPos[22] = "5 1 0";
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logicPortDir[22] = 1;
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logicPortUIName[22] = "Sum5";
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logicPortType[23] = 0;
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logicPortPos[23] = "3 1 0";
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logicPortDir[23] = 1;
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logicPortUIName[23] = "Sum6";
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logicPortType[24] = 0;
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logicPortPos[24] = "1 1 0";
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logicPortDir[24] = 1;
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logicPortUIName[24] = "Sum7";
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logicPortType[25] = 0;
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logicPortPos[25] = "-15 -1 0";
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logicPortDir[25] = 0;
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logicPortUIName[25] = "Carry Out";
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};
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lualogic_registergatedefinition("LogicGate_8bitAdder_Data");
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|
@ -1,218 +1,218 @@
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datablock fxDTSBrickData(LogicGate_8bitDivider_Data)
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{
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brickFile = $LuaLogic::Path @ "bricks/blb/8bitMultiplier.blb";
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category = "Logic Bricks";
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subCategory = "Math";
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uiName = "8bit Divider";
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iconName = $LuaLogic::Path @ "icons/8bit Divider";
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hasPrint = 1;
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printAspectRatio = "Logic";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicUIName = "8bit Divider";
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logicUIDesc = "Divides A by B";
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logicUpdate = "return function(gate) local a, b, n = 0, 0 " @
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"for i = 1, 8 do " @
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"local n = 2^(i-1) " @
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"a = a + bool_to_int[gate.ports[i].state] * n " @
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"b = b + bool_to_int[gate.ports[i+8].state] * n " @
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"end " @
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"if b ~= 0 then " @
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"local q = math.floor(a/b) " @
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"local r = a-q*b " @
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"for i = 1, 8 do " @
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"local n = 2^(i-1) " @
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"gate.ports[i+16]:setstate(bit.band(q, n) > 0) " @
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"gate.ports[i+24]:setstate(bit.band(r, n) > 0) " @
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"end " @
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"else " @
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"for i = 1, 8 do " @
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"gate.ports[i+16]:setstate(false) " @
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"gate.ports[i+24]:setstate(false) " @
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"end " @
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"end end";
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numLogicPorts = 32;
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logicPortType[0] = 1;
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logicPortPos[0] = "-1 -1 0";
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logicPortDir[0] = 3;
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logicPortCauseUpdate[0] = true;
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logicPortUIName[0] = "A0";
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logicPortType[1] = 1;
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logicPortPos[1] = "-3 -1 0";
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logicPortDir[1] = 3;
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logicPortCauseUpdate[1] = true;
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logicPortUIName[1] = "A1";
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logicPortType[2] = 1;
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logicPortPos[2] = "-5 -1 0";
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logicPortDir[2] = 3;
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logicPortCauseUpdate[2] = true;
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logicPortUIName[2] = "A2";
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logicPortType[3] = 1;
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logicPortPos[3] = "-7 -1 0";
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logicPortDir[3] = 3;
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logicPortCauseUpdate[3] = true;
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logicPortUIName[3] = "A3";
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logicPortType[4] = 1;
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logicPortPos[4] = "-9 -1 0";
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logicPortDir[4] = 3;
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logicPortCauseUpdate[4] = true;
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logicPortUIName[4] = "A4";
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logicPortType[5] = 1;
|
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logicPortPos[5] = "-11 -1 0";
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logicPortDir[5] = 3;
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logicPortCauseUpdate[5] = true;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
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logicPortType[6] = 1;
|
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logicPortPos[6] = "-13 -1 0";
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logicPortDir[6] = 3;
|
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logicPortCauseUpdate[6] = true;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
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logicPortType[7] = 1;
|
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logicPortPos[7] = "-15 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortCauseUpdate[7] = true;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortCauseUpdate[8] = true;
|
||||
logicPortUIName[8] = "B0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortCauseUpdate[9] = true;
|
||||
logicPortUIName[9] = "B1";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortCauseUpdate[10] = true;
|
||||
logicPortUIName[10] = "B2";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortUIName[11] = "B3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortCauseUpdate[12] = true;
|
||||
logicPortUIName[12] = "B4";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortCauseUpdate[13] = true;
|
||||
logicPortUIName[13] = "B5";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortCauseUpdate[14] = true;
|
||||
logicPortUIName[14] = "B6";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortCauseUpdate[15] = true;
|
||||
logicPortUIName[15] = "B7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 1 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Q0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Q1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Q2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Q3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Q4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Q5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Q6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Q7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "R0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 1 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "R1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 1 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "R2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 1 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "R3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 1 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "R4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 1 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "R5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 1 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "R6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 1 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "R7";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_8bitDivider_Data");
|
||||
datablock fxDTSBrickData(LogicGate_8bitDivider_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/8bitMultiplier.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "8bit Divider";
|
||||
iconName = $LuaLogic::Path @ "icons/8bit Divider";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "8bit Divider";
|
||||
logicUIDesc = "Divides A by B";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b, n = 0, 0 " @
|
||||
"for i = 1, 8 do " @
|
||||
"local n = 2^(i-1) " @
|
||||
"a = a + bool_to_int[gate.ports[i].state] * n " @
|
||||
"b = b + bool_to_int[gate.ports[i+8].state] * n " @
|
||||
"end " @
|
||||
"if b ~= 0 then " @
|
||||
"local q = math.floor(a/b) " @
|
||||
"local r = a-q*b " @
|
||||
"for i = 1, 8 do " @
|
||||
"local n = 2^(i-1) " @
|
||||
"gate.ports[i+16]:setstate(bit.band(q, n) > 0) " @
|
||||
"gate.ports[i+24]:setstate(bit.band(r, n) > 0) " @
|
||||
"end " @
|
||||
"else " @
|
||||
"for i = 1, 8 do " @
|
||||
"gate.ports[i+16]:setstate(false) " @
|
||||
"gate.ports[i+24]:setstate(false) " @
|
||||
"end " @
|
||||
"end end";
|
||||
|
||||
numLogicPorts = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-3 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-5 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-7 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortCauseUpdate[3] = true;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-9 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortCauseUpdate[4] = true;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-11 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortCauseUpdate[5] = true;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-13 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortCauseUpdate[6] = true;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-15 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortCauseUpdate[7] = true;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortCauseUpdate[8] = true;
|
||||
logicPortUIName[8] = "B0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortCauseUpdate[9] = true;
|
||||
logicPortUIName[9] = "B1";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortCauseUpdate[10] = true;
|
||||
logicPortUIName[10] = "B2";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortUIName[11] = "B3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortCauseUpdate[12] = true;
|
||||
logicPortUIName[12] = "B4";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortCauseUpdate[13] = true;
|
||||
logicPortUIName[13] = "B5";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortCauseUpdate[14] = true;
|
||||
logicPortUIName[14] = "B6";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortCauseUpdate[15] = true;
|
||||
logicPortUIName[15] = "B7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 1 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Q0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Q1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Q2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Q3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Q4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Q5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Q6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Q7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "R0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 1 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "R1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 1 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "R2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 1 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "R3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 1 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "R4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 1 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "R5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 1 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "R6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 1 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "R7";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_8bitDivider_Data");
|
||||
|
@ -1,208 +1,208 @@
|
||||
datablock fxDTSBrickData(LogicGate_8bitMultiplier_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/8bitMultiplier.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "8bit Multiplier";
|
||||
iconName = $LuaLogic::Path @ "icons/8bit Multiplier";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "8bit Multiplier";
|
||||
logicUIDesc = "Multiplies A by B";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b = 0, 0 " @
|
||||
"local sum = 0 " @
|
||||
"for i = 1, 8 do " @
|
||||
"a = a + bool_to_int[gate.ports[i].state] * 2^(i-1) " @
|
||||
"b = b + bool_to_int[gate.ports[i+8].state] * 2^(i-1) " @
|
||||
"end " @
|
||||
"local sum = a * b " @
|
||||
"for i = 1, 16 do " @
|
||||
"gate.ports[i+16]:setstate(bit.band(sum, 2^(i-1)) > 0) " @
|
||||
"end end";
|
||||
|
||||
numLogicPorts = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-3 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-5 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-7 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortCauseUpdate[3] = true;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-9 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortCauseUpdate[4] = true;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-11 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortCauseUpdate[5] = true;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-13 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortCauseUpdate[6] = true;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-15 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortCauseUpdate[7] = true;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortCauseUpdate[8] = true;
|
||||
logicPortUIName[8] = "B0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortCauseUpdate[9] = true;
|
||||
logicPortUIName[9] = "B1";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortCauseUpdate[10] = true;
|
||||
logicPortUIName[10] = "B2";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortUIName[11] = "B3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortCauseUpdate[12] = true;
|
||||
logicPortUIName[12] = "B4";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortCauseUpdate[13] = true;
|
||||
logicPortUIName[13] = "B5";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortCauseUpdate[14] = true;
|
||||
logicPortUIName[14] = "B6";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortCauseUpdate[15] = true;
|
||||
logicPortUIName[15] = "B7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 1 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 1 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 1 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 1 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 1 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 1 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 1 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 1 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_8bitMultiplier_Data");
|
||||
datablock fxDTSBrickData(LogicGate_8bitMultiplier_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/8bitMultiplier.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "8bit Multiplier";
|
||||
iconName = $LuaLogic::Path @ "icons/8bit Multiplier";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "8bit Multiplier";
|
||||
logicUIDesc = "Multiplies A by B";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b = 0, 0 " @
|
||||
"local sum = 0 " @
|
||||
"for i = 1, 8 do " @
|
||||
"a = a + bool_to_int[gate.ports[i].state] * 2^(i-1) " @
|
||||
"b = b + bool_to_int[gate.ports[i+8].state] * 2^(i-1) " @
|
||||
"end " @
|
||||
"local sum = a * b " @
|
||||
"for i = 1, 16 do " @
|
||||
"gate.ports[i+16]:setstate(bit.band(sum, 2^(i-1)) > 0) " @
|
||||
"end end";
|
||||
|
||||
numLogicPorts = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-3 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-5 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-7 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortCauseUpdate[3] = true;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-9 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortCauseUpdate[4] = true;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-11 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortCauseUpdate[5] = true;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-13 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortCauseUpdate[6] = true;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-15 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortCauseUpdate[7] = true;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortCauseUpdate[8] = true;
|
||||
logicPortUIName[8] = "B0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortCauseUpdate[9] = true;
|
||||
logicPortUIName[9] = "B1";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortCauseUpdate[10] = true;
|
||||
logicPortUIName[10] = "B2";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortUIName[11] = "B3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortCauseUpdate[12] = true;
|
||||
logicPortUIName[12] = "B4";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortCauseUpdate[13] = true;
|
||||
logicPortUIName[13] = "B5";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortCauseUpdate[14] = true;
|
||||
logicPortUIName[14] = "B6";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortCauseUpdate[15] = true;
|
||||
logicPortUIName[15] = "B7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 1 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 1 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 1 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 1 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 1 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 1 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 1 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 1 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_8bitMultiplier_Data");
|
||||
|
@ -1,179 +1,179 @@
|
||||
datablock fxDTSBrickData(LogicGate_8bitSubtractor_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/8bitAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "8bit Subtractor";
|
||||
iconName = $LuaLogic::Path @ "icons/8bit Subtractor";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "8bit Subtractor";
|
||||
logicUIDesc = "Subtracts B from A";
|
||||
|
||||
logicUpdate = "return function(gate) local c = bool_to_int[gate.ports[17].state] " @
|
||||
"local a = 0 " @
|
||||
"local b = 0 " @
|
||||
"for i = 1, 8 do " @
|
||||
"a = bool_to_int[gate.ports[i].state] " @
|
||||
"b = bool_to_int[gate.ports[i+8].state] " @
|
||||
"gate.ports[i+17]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
|
||||
"c = bit.bor(bit.bor(bit.band(bool_to_int[a == 0], b), bit.band(bool_to_int[a == 0], c)), bit.band(b, c)) " @
|
||||
"end " @
|
||||
"gate.ports[26]:setstate(c == 1) end";
|
||||
|
||||
numLogicPorts = 26;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-3 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-5 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-7 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortCauseUpdate[3] = true;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-9 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortCauseUpdate[4] = true;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-11 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortCauseUpdate[5] = true;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-13 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortCauseUpdate[6] = true;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-15 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortCauseUpdate[7] = true;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortCauseUpdate[8] = true;
|
||||
logicPortUIName[8] = "B0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortCauseUpdate[9] = true;
|
||||
logicPortUIName[9] = "B1";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortCauseUpdate[10] = true;
|
||||
logicPortUIName[10] = "B2";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortUIName[11] = "B3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortCauseUpdate[12] = true;
|
||||
logicPortUIName[12] = "B4";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortCauseUpdate[13] = true;
|
||||
logicPortUIName[13] = "B5";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortCauseUpdate[14] = true;
|
||||
logicPortUIName[14] = "B6";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortCauseUpdate[15] = true;
|
||||
logicPortUIName[15] = "B7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "15 -1 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortCauseUpdate[16] = true;
|
||||
logicPortUIName[16] = "Borrow In";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "15 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Diff0";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "13 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Diff1";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "11 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Diff2";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "9 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Diff3";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "7 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Diff4";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "5 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Diff5";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "3 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Diff6";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "1 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Diff7";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-15 -1 0";
|
||||
logicPortDir[25] = 0;
|
||||
logicPortUIName[25] = "Borrow Out";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_8bitSubtractor_Data");
|
||||
datablock fxDTSBrickData(LogicGate_8bitSubtractor_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/8bitAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "8bit Subtractor";
|
||||
iconName = $LuaLogic::Path @ "icons/8bit Subtractor";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "8bit Subtractor";
|
||||
logicUIDesc = "Subtracts B from A";
|
||||
|
||||
logicUpdate = "return function(gate) local c = bool_to_int[gate.ports[17].state] " @
|
||||
"local a = 0 " @
|
||||
"local b = 0 " @
|
||||
"for i = 1, 8 do " @
|
||||
"a = bool_to_int[gate.ports[i].state] " @
|
||||
"b = bool_to_int[gate.ports[i+8].state] " @
|
||||
"gate.ports[i+17]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
|
||||
"c = bit.bor(bit.bor(bit.band(bool_to_int[a == 0], b), bit.band(bool_to_int[a == 0], c)), bit.band(b, c)) " @
|
||||
"end " @
|
||||
"gate.ports[26]:setstate(c == 1) end";
|
||||
|
||||
numLogicPorts = 26;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-3 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-5 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-7 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortCauseUpdate[3] = true;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-9 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortCauseUpdate[4] = true;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-11 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortCauseUpdate[5] = true;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-13 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortCauseUpdate[6] = true;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-15 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortCauseUpdate[7] = true;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortCauseUpdate[8] = true;
|
||||
logicPortUIName[8] = "B0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortCauseUpdate[9] = true;
|
||||
logicPortUIName[9] = "B1";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortCauseUpdate[10] = true;
|
||||
logicPortUIName[10] = "B2";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortUIName[11] = "B3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortCauseUpdate[12] = true;
|
||||
logicPortUIName[12] = "B4";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortCauseUpdate[13] = true;
|
||||
logicPortUIName[13] = "B5";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortCauseUpdate[14] = true;
|
||||
logicPortUIName[14] = "B6";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortCauseUpdate[15] = true;
|
||||
logicPortUIName[15] = "B7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "15 -1 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortCauseUpdate[16] = true;
|
||||
logicPortUIName[16] = "Borrow In";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "15 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Diff0";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "13 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Diff1";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "11 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Diff2";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "9 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Diff3";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "7 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Diff4";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "5 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Diff5";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "3 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Diff6";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "1 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Diff7";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-15 -1 0";
|
||||
logicPortDir[25] = 0;
|
||||
logicPortUIName[25] = "Borrow Out";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_8bitSubtractor_Data");
|
||||
|
@ -1,53 +1,53 @@
|
||||
datablock fxDTSBrickData(LogicGate_FullAdder_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/FullAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Full Adder";
|
||||
iconName = $LuaLogic::Path @ "icons/Full Adder";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Full Adder";
|
||||
logicUIDesc = "Adds A and B with carry in";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b, c = bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state], bool_to_int[gate.ports[3].state] " @
|
||||
"gate.ports[4]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
|
||||
"gate.ports[5]:setstate(bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b)) == 1) end";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "Carry In";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Sum";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 0;
|
||||
logicPortUIName[4] = "Carry Out";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_FullAdder_Data");
|
||||
datablock fxDTSBrickData(LogicGate_FullAdder_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/FullAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Full Adder";
|
||||
iconName = $LuaLogic::Path @ "icons/Full Adder";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Full Adder";
|
||||
logicUIDesc = "Adds A and B with carry in";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b, c = bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state], bool_to_int[gate.ports[3].state] " @
|
||||
"gate.ports[4]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
|
||||
"gate.ports[5]:setstate(bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b)) == 1) end";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "Carry In";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Sum";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 0;
|
||||
logicPortUIName[4] = "Carry Out";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_FullAdder_Data");
|
||||
|
@ -1,53 +1,53 @@
|
||||
datablock fxDTSBrickData(LogicGate_FullSubtractor_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/FullAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Full Subtractor";
|
||||
iconName = $LuaLogic::Path @ "icons/Full Subtractor";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Full Subtractor";
|
||||
logicUIDesc = "Subtracts B from A with borrow in";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b, c = bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state], bool_to_int[gate.ports[3].state] " @
|
||||
"gate.ports[4]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
|
||||
"gate.ports[5]:setstate(not gate.ports[1].state and gate.ports[2].state or not (bit.bxor(a, b) == 1) and gate.ports[3].state) end";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "Borrow In";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Difference";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 0;
|
||||
logicPortUIName[4] = "Borrow Out";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_FullSubtractor_Data");
|
||||
datablock fxDTSBrickData(LogicGate_FullSubtractor_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/FullAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Full Subtractor";
|
||||
iconName = $LuaLogic::Path @ "icons/Full Subtractor";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Full Subtractor";
|
||||
logicUIDesc = "Subtracts B from A with borrow in";
|
||||
|
||||
logicUpdate = "return function(gate) local a, b, c = bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state], bool_to_int[gate.ports[3].state] " @
|
||||
"gate.ports[4]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
|
||||
"gate.ports[5]:setstate(not gate.ports[1].state and gate.ports[2].state or not (bit.bxor(a, b) == 1) and gate.ports[3].state) end";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortCauseUpdate[2] = true;
|
||||
logicPortUIName[2] = "Borrow In";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Difference";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 0;
|
||||
logicPortUIName[4] = "Borrow Out";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_FullSubtractor_Data");
|
||||
|
@ -1,46 +1,46 @@
|
||||
datablock fxDTSBrickData(LogicGate_HalfAdder_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/HalfAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Half Adder";
|
||||
iconName = $LuaLogic::Path @ "icons/Half Adder";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Half Adder";
|
||||
logicUIDesc = "Adds A and B";
|
||||
|
||||
logicUpdate = "return function(gate) gate.ports[3]:setstate(bit.bxor(bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state]) == 1) " @
|
||||
"gate.ports[4]:setstate(gate.ports[1].state and gate.ports[2].state) end";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Sum";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 0;
|
||||
logicPortUIName[3] = "Carry";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_HalfAdder_Data");
|
||||
datablock fxDTSBrickData(LogicGate_HalfAdder_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/HalfAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Half Adder";
|
||||
iconName = $LuaLogic::Path @ "icons/Half Adder";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Half Adder";
|
||||
logicUIDesc = "Adds A and B";
|
||||
|
||||
logicUpdate = "return function(gate) gate.ports[3]:setstate(bit.bxor(bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state]) == 1) " @
|
||||
"gate.ports[4]:setstate(gate.ports[1].state and gate.ports[2].state) end";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Sum";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 0;
|
||||
logicPortUIName[3] = "Carry";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_HalfAdder_Data");
|
||||
|
@ -1,46 +1,46 @@
|
||||
datablock fxDTSBrickData(LogicGate_HalfSubtractor_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/HalfAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Half Subtractor";
|
||||
iconName = $LuaLogic::Path @ "icons/Half Subtractor";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Half Subtractor";
|
||||
logicUIDesc = "Subtracts B from A";
|
||||
|
||||
logicUpdate = "return function(gate) gate.ports[3]:setstate(bit.bxor(bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state]) == 1) " @
|
||||
"gate.ports[4]:setstate(not gate.ports[1].state and gate.ports[2].state) end";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Difference";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 0;
|
||||
logicPortUIName[3] = "Borrow";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_HalfSubtractor_Data");
|
||||
datablock fxDTSBrickData(LogicGate_HalfSubtractor_Data)
|
||||
{
|
||||
brickFile = $LuaLogic::Path @ "bricks/blb/HalfAdder.blb";
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Half Subtractor";
|
||||
iconName = $LuaLogic::Path @ "icons/Half Subtractor";
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicUIName = "Half Subtractor";
|
||||
logicUIDesc = "Subtracts B from A";
|
||||
|
||||
logicUpdate = "return function(gate) gate.ports[3]:setstate(bit.bxor(bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state]) == 1) " @
|
||||
"gate.ports[4]:setstate(not gate.ports[1].state and gate.ports[2].state) end";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "-1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortCauseUpdate[0] = true;
|
||||
logicPortUIName[0] = "A";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortCauseUpdate[1] = true;
|
||||
logicPortUIName[1] = "B";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Difference";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 0;
|
||||
logicPortUIName[3] = "Borrow";
|
||||
};
|
||||
lualogic_registergatedefinition("LogicGate_HalfSubtractor_Data");
|
||||
|
Reference in New Issue
Block a user