added more bus bricks
This commit is contained in:
Redo
154
bricks/bus/8BitBuffer.cs
Normal file
154
bricks/bus/8BitBuffer.cs
Normal file
@ -0,0 +1,154 @@
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datablock fxDTSBrickData(LogicGate_8BitBuffer_Data)
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{
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brickFile = $LuaLogic::Path @ "bricks/blb/1x8f_8i_8o_p.blb";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "8 Bit Buffer";
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iconName = $LuaLogic::Path @ "icons/8 Bit Buffer";
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hasPrint = 1;
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printAspectRatio = "Logic";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicUIName = "8 Bit Buffer";
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logicUIDesc = "8 bit buffer with clock propagate";
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logicUpdate =
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"return function(gate) " @
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" if gate.ports[9].state then " @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(gate.ports[i].state) " @
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" end " @
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" gate.ports[10]:setstate(true) " @
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" else " @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(false) " @
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" end " @
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" gate.ports[10]:setstate(false) " @
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" end " @
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"end "
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;
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numLogicPorts = 18;
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logicPortType[0] = 1;
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logicPortPos[0] = "-7 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "D7";
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logicPortType[1] = 1;
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logicPortPos[1] = "-5 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "D6";
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logicPortType[2] = 1;
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logicPortPos[2] = "-3 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "D5";
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logicPortType[3] = 1;
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logicPortPos[3] = "-1 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "D4";
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logicPortType[4] = 1;
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logicPortPos[4] = "1 0 0";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "D3";
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logicPortType[5] = 1;
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logicPortPos[5] = "3 0 0";
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logicPortDir[5] = 3;
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logicPortUIName[5] = "D2";
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logicPortType[6] = 1;
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logicPortPos[6] = "5 0 0";
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logicPortDir[6] = 3;
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logicPortUIName[6] = "D1";
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logicPortType[7] = 1;
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logicPortPos[7] = "7 0 0";
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logicPortDir[7] = 3;
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logicPortUIName[7] = "D0";
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logicPortType[8] = 1;
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logicPortPos[8] = "7 0 0";
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logicPortDir[8] = 2;
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logicPortCauseUpdate[8] = true;
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logicPortUIName[8] = "ClockIn";
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logicPortType[9] = 0;
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logicPortPos[9] = "-7 0 0";
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logicPortDir[9] = 0;
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logicPortUIName[9] = "ClockOut";
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logicPortType[10] = 0;
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logicPortPos[10] = "-7 0 0";
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logicPortDir[10] = 1;
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logicPortUIName[10] = "Q7";
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logicPortType[11] = 0;
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logicPortPos[11] = "-5 0 0";
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logicPortDir[11] = 1;
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logicPortUIName[11] = "Q6";
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logicPortType[12] = 0;
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logicPortPos[12] = "-3 0 0";
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logicPortDir[12] = 1;
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logicPortUIName[12] = "Q5";
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logicPortType[13] = 0;
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logicPortPos[13] = "-1 0 0";
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logicPortDir[13] = 1;
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logicPortUIName[13] = "Q4";
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logicPortType[14] = 0;
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logicPortPos[14] = "1 0 0";
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logicPortDir[14] = 1;
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logicPortUIName[14] = "Q3";
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logicPortType[15] = 0;
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logicPortPos[15] = "3 0 0";
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logicPortDir[15] = 1;
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logicPortUIName[15] = "Q2";
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logicPortType[16] = 0;
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logicPortPos[16] = "5 0 0";
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logicPortDir[16] = 1;
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logicPortUIName[16] = "Q1";
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logicPortType[17] = 0;
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logicPortPos[17] = "7 0 0";
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logicPortDir[17] = 1;
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logicPortUIName[17] = "Q0";
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};
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lualogic_registergatedefinition("LogicGate_8BitBuffer_Data");
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datablock fxDTSBrickData(LogicGate_8BitBufferAL_Data : LogicGate_8BitBuffer_Data){
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uiName = "8 Bit Buffer Active Low";
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iconName = $LuaLogic::Path @ "icons/8 Bit Buffer Active Low";
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logicUIName = "8 Bit Buffer Active Low";
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logicUIDesc = "8 bit buffer with clock propagate; clock is active low";
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logicUpdate =
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"return function(gate) " @
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" if not gate.ports[9].state then " @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(gate.ports[i].state) " @
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" end " @
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" gate.ports[10]:setstate(false) " @
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" else " @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(false) " @
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" end " @
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" gate.ports[10]:setstate(true) " @
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" end " @
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"end "
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;
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};
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lualogic_registergatedefinition("LogicGate_8BitBufferAL_Data");
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@ -1,3 +1,4 @@
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datablock fxDTSBrickData(LogicGate_8BitDFlipFlop_Data)
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{
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brickFile = $LuaLogic::Path @ "bricks/blb/1x8f_8i_8o_p.blb";
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@ -118,3 +119,21 @@ datablock fxDTSBrickData(LogicGate_8BitDFlipFlop_Data)
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logicPortUIName[17] = "Q0";
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};
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lualogic_registergatedefinition("LogicGate_8BitDFlipFlop_Data");
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datablock fxDTSBrickData(LogicGate_8BitDFlipFlopAL_Data : LogicGate_8BitDFlipFlop_Data){
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uiName = "8 Bit D FlipFlop Active Low";
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iconName = $LuaLogic::Path @ "icons/8 Bit D FlipFlop Active Low";
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logicUIName = "8 Bit D FlipFlop Active Low";
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logicUIDesc = "8 bit d flipflop with clock propagate, clock is active low";
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logicUpdate =
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"return function(gate) if gate.ports[9]:isfalling() then " @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(gate.ports[i].state) " @
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" end " @
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"end " @
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"gate.ports[10]:setstate(gate.ports[9].state) end"
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;
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};
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lualogic_registergatedefinition("LogicGate_8BitDFlipFlopAL_Data");
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@ -1,3 +1,4 @@
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datablock fxDTSBrickData(LogicGate_8BitEnabler_Data)
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{
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brickFile = $LuaLogic::Path @ "bricks/blb/1x8f_8i_8o_p.blb";
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@ -130,3 +131,28 @@ datablock fxDTSBrickData(LogicGate_8BitEnabler_Data)
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logicPortUIName[17] = "Q0";
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};
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lualogic_registergatedefinition("LogicGate_8BitEnabler_Data");
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datablock fxDTSBrickData(LogicGate_8BitEnablerAL_Data : LogicGate_8BitEnabler_Data){
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uiName = "8 Bit Enabler Active Low";
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iconName = $LuaLogic::Path @ "icons/8 Bit Enabler Active Low";
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logicUIName = "8 Bit Enabler Active Low";
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logicUIDesc = "8 bit enabler with enable propagate; enable is active low";
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logicUpdate =
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"return function(gate) " @
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" if not gate.ports[9].state then " @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(gate.ports[i].state) " @
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" end " @
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" gate.ports[10]:setstate(false) " @
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" elseif gate.ports[9]:isrising() then" @
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" for i = 1, 8 do " @
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" gate.ports[i+10]:setstate(false) " @
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" end " @
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" gate.ports[10]:setstate(true) " @
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" end " @
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"end"
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;
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};
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lualogic_registergatedefinition("LogicGate_8BitEnablerAL_Data");
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269
bricks/bus/bus16.cs
Normal file
269
bricks/bus/bus16.cs
Normal file
@ -0,0 +1,269 @@
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datablock fxDTSBrickData(LogicGate_16BitBuffer_Data){
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brickFile = $LuaLogic::Path @ "/bricks/blb/16bitbus.blb";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "16 Bit Buffer";
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iconName = $LuaLogic::Path @ "icons/16 Bit Buffer";
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hasPrint = 1;
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printAspectRatio = "Logic";
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orientationFix = 0;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicUIName = "16 Bit Buffer";
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logicUIDesc = "16 bit buffer with clock propagate";
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logicUpdate =
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"return function(gate) " @
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" if gate.ports[33].state then " @
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" for i = 1, 16 do " @
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" gate.ports[i+16]:setstate(gate.ports[i].state) " @
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" end " @
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" gate.ports[34]:setstate(true) " @
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" else " @
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" for i = 1, 16 do " @
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" gate.ports[i+16]:setstate(false) " @
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" end " @
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" gate.ports[34]:setstate(false) " @
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" end " @
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"end "
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;
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numLogicPorts = 34;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 -15 0";
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logicPortDir[0] = 0;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 1;
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logicPortPos[1] = "0 -13 0";
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logicPortDir[1] = 0;
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logicPortUIName[1] = "In1";
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logicPortType[2] = 1;
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logicPortPos[2] = "0 -11 0";
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logicPortDir[2] = 0;
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logicPortUIName[2] = "In2";
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logicPortType[3] = 1;
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logicPortPos[3] = "0 -9 0";
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logicPortDir[3] = 0;
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logicPortUIName[3] = "In3";
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logicPortType[4] = 1;
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logicPortPos[4] = "0 -7 0";
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logicPortDir[4] = 0;
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logicPortUIName[4] = "In4";
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logicPortType[5] = 1;
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logicPortPos[5] = "0 -5 0";
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logicPortDir[5] = 0;
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logicPortUIName[5] = "In5";
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logicPortType[6] = 1;
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logicPortPos[6] = "0 -3 0";
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logicPortDir[6] = 0;
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logicPortUIName[6] = "In6";
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logicPortType[7] = 1;
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logicPortPos[7] = "0 -1 0";
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logicPortDir[7] = 0;
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logicPortUIName[7] = "In7";
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logicPortType[8] = 1;
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logicPortPos[8] = "0 1 0";
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logicPortDir[8] = 0;
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logicPortUIName[8] = "In8";
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logicPortType[9] = 1;
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logicPortPos[9] = "0 3 0";
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logicPortDir[9] = 0;
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logicPortUIName[9] = "In9";
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logicPortType[10] = 1;
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logicPortPos[10] = "0 5 0";
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logicPortDir[10] = 0;
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logicPortUIName[10] = "In10";
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logicPortType[11] = 1;
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logicPortPos[11] = "0 7 0";
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logicPortDir[11] = 0;
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logicPortUIName[11] = "In11";
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logicPortType[12] = 1;
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logicPortPos[12] = "0 9 0";
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logicPortDir[12] = 0;
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logicPortUIName[12] = "In12";
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logicPortType[13] = 1;
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logicPortPos[13] = "0 11 0";
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logicPortDir[13] = 0;
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logicPortUIName[13] = "In13";
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logicPortType[14] = 1;
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logicPortPos[14] = "0 13 0";
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logicPortDir[14] = 0;
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logicPortUIName[14] = "In14";
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logicPortType[15] = 1;
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logicPortPos[15] = "0 15 0";
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logicPortDir[15] = 0;
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logicPortUIName[15] = "In15";
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logicPortType[16] = 0;
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logicPortPos[16] = "0 -15 0";
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logicPortDir[16] = 2;
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logicPortUIName[16] = "Out0";
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logicPortType[17] = 0;
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logicPortPos[17] = "0 -13 0";
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logicPortDir[17] = 2;
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logicPortUIName[17] = "Out1";
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logicPortType[18] = 0;
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logicPortPos[18] = "0 -11 0";
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logicPortDir[18] = 2;
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logicPortUIName[18] = "Out2";
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logicPortType[19] = 0;
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logicPortPos[19] = "0 -9 0";
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logicPortDir[19] = 2;
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logicPortUIName[19] = "Out3";
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logicPortType[20] = 0;
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logicPortPos[20] = "0 -7 0";
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logicPortDir[20] = 2;
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logicPortUIName[20] = "Out4";
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logicPortType[21] = 0;
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logicPortPos[21] = "0 -5 0";
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logicPortDir[21] = 2;
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logicPortUIName[21] = "Out5";
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logicPortType[22] = 0;
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logicPortPos[22] = "0 -3 0";
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logicPortDir[22] = 2;
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logicPortUIName[22] = "Out6";
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logicPortType[23] = 0;
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logicPortPos[23] = "0 -1 0";
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logicPortDir[23] = 2;
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logicPortUIName[23] = "Out7";
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logicPortType[24] = 0;
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logicPortPos[24] = "0 1 0";
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logicPortDir[24] = 2;
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logicPortUIName[24] = "Out8";
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logicPortType[25] = 0;
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logicPortPos[25] = "0 3 0";
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logicPortDir[25] = 2;
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logicPortUIName[25] = "Out9";
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logicPortType[26] = 0;
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logicPortPos[26] = "0 5 0";
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logicPortDir[26] = 2;
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logicPortUIName[26] = "Out10";
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logicPortType[27] = 0;
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logicPortPos[27] = "0 7 0";
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logicPortDir[27] = 2;
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logicPortUIName[27] = "Out11";
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logicPortType[28] = 0;
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logicPortPos[28] = "0 9 0";
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logicPortDir[28] = 2;
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logicPortUIName[28] = "Out12";
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logicPortType[29] = 0;
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logicPortPos[29] = "0 11 0";
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||||
logicPortDir[29] = 2;
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logicPortUIName[29] = "Out13";
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logicPortType[30] = 0;
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logicPortPos[30] = "0 13 0";
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logicPortDir[30] = 2;
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logicPortUIName[30] = "Out14";
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logicPortType[31] = 0;
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logicPortPos[31] = "0 15 0";
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logicPortDir[31] = 2;
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logicPortUIName[31] = "Out15";
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logicPortType[32] = 1;
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logicPortPos[32] = "0 -15 0";
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logicPortDir[32] = 3;
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logicPortUIName[32] = "ClockIn";
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logicPortCauseUpdate[32] = true;
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logicPortType[33] = 0;
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logicPortPos[33] = "0 15 0";
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logicPortDir[33] = 1;
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logicPortUIName[33] = "ClockOut";
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};
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||||
datablock fxDtsBrickData(LogicGate_16BitBufferAL_Data : LogicGate_16BitBuffer_Data){
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||||
uiName = "16 Bit Buffer Active Low";
|
||||
iconName = $LuaLogic::Path @ "icons/16 Bit Buffer Active Low";
|
||||
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||||
logicUIName = "16 Bit Buffer Active Low";
|
||||
logicUIDesc = "16 big buffer with clock propagate; clock is active low";
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||||
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||||
logicUpdate =
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||||
"return function(gate) " @
|
||||
" if not gate.ports[33].state then " @
|
||||
" for i = 1, 16 do " @
|
||||
" gate.ports[i+16]:setstate(gate.ports[i].state) " @
|
||||
" end " @
|
||||
" gate.ports[34]:setstate(false) " @
|
||||
" else " @
|
||||
" for i = 1, 16 do " @
|
||||
" gate.ports[i+16]:setstate(false) " @
|
||||
" end " @
|
||||
" gate.ports[34]:setstate(true) " @
|
||||
" end " @
|
||||
"end "
|
||||
;
|
||||
};
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_16BitDFlipFlop_Data : LogicGate_16BitBuffer_Data){
|
||||
uiName = "16 Bit D FlipFlop";
|
||||
iconName = $LuaLogic::Path @ "icons/16 Bit D FlipFlop";
|
||||
|
||||
logicUIName = "16 Bit D FlipFlop";
|
||||
logicUIDesc = "16 big D FlipFlop with clock propagate";
|
||||
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[33]:isrising() then " @
|
||||
" for i = 1, 16 do " @
|
||||
" gate.ports[i+16]:setstate(gate.ports[i].state) " @
|
||||
" end " @
|
||||
" end " @
|
||||
" gate.ports[34]:setstate(gate.ports[33].state) " @
|
||||
"end "
|
||||
;
|
||||
};
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_16BitDFlipFlopAL_Data : LogicGate_16BitBuffer_Data){
|
||||
uiName = "16 Bit D FlipFlop Active Low";
|
||||
iconName = $LuaLogic::Path @ "icons/16 Bit D FlipFlop Active Low";
|
||||
|
||||
logicUIName = "16 Bit D FlipFlop Active Low";
|
||||
logicUIDesc = "16 big D FlipFlop with clock propagate; clock is active low";
|
||||
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[33]:isfalling() then " @
|
||||
" for i = 1, 16 do " @
|
||||
" gate.ports[i+16]:setstate(gate.ports[i].state) " @
|
||||
" end " @
|
||||
" end " @
|
||||
" gate.ports[34]:setstate(gate.ports[33].state) " @
|
||||
"end "
|
||||
;
|
||||
};
|
||||
Reference in New Issue
Block a user