redo/Brick_LuaLogic
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

update logic functions to remove metatable OOP

Browse Source
This commit is contained in:
Redo
2020-09-10 12:58:25 -05:00
parent 4095d193ff
commit ab19de7333
206 changed files with 22726 additions and 3544 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
bricks/math/8bitAdder.cs
View File

@ -16,16 +16,20 @@ datablock fxDTSBrickData(LogicGate_8bitAdder_Data)
logicUIName = "8bit Adder";
logicUIDesc = "";
logicUpdate = "return function(gate) local c = bool_to_int[gate.ports[17].state] " @
"local a = 0 " @
"local b = 0 " @
"for i = 1, 8 do " @
"a = bool_to_int[gate.ports[i].state] " @
"b = bool_to_int[gate.ports[i+8].state] " @
"gate.ports[i+17]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
"c = bit.bor(bit.band(a, b), bit.band(c, bit.bor(a, b))) " @
"end " @
"gate.ports[26]:setstate(c == 1) end";
logicUpdate =
"return function(gate) " @
" local c = bool_to_int[Gate.getportstate(gate, 17)] " @
" local a = 0 " @
" local b = 0 " @
" for i = 1, 8 do " @
" a = bool_to_int[Gate.getportstate(gate, i )] " @
" b = bool_to_int[Gate.getportstate(gate, i+8)] " @
" Gate.setportstate(gate, i+17, bit.bxor(bit.bxor(a, b), c) == 1) " @
" c = bit.bor(bit.band(a, b), bit.band(c, bit.bor(a, b))) " @
" end " @
" Gate.setportstate(gate, 26, c == 1) " @
"end"
;
numLogicPorts = 26;

48
bricks/math/8bitDivider.cs
View File

@ -15,28 +15,32 @@ datablock fxDTSBrickData(LogicGate_8bitDivider_Data)
logicUIName = "8bit Divider";
logicUIDesc = "Divides A by B";
logicUpdate = "return function(gate) local a, b, n = 0, 0 " @
"for i = 1, 8 do " @
"local n = 2^(i-1) " @
"a = a + bool_to_int[gate.ports[i].state] * n " @
"b = b + bool_to_int[gate.ports[i+8].state] * n " @
"end " @
"if b ~= 0 then " @
"local q = math.floor(a/b) " @
"local r = a-q*b " @
"for i = 1, 8 do " @
"local n = 2^(i-1) " @
"gate.ports[i+16]:setstate(bit.band(q, n) > 0) " @
"gate.ports[i+24]:setstate(bit.band(r, n) > 0) " @
"end " @
"else " @
"for i = 1, 8 do " @
"gate.ports[i+16]:setstate(false) " @
"gate.ports[i+24]:setstate(false) " @
"end " @
"end end";
logicUpdate =
"return function(gate) " @
" local a, b, n = 0, 0 " @
" for i = 1, 8 do " @
" local n = 2^(i-1) " @
" a = a + bool_to_int[Gate.getportstate(gate, i )] * n " @
" b = b + bool_to_int[Gate.getportstate(gate, i+8)] * n " @
" end " @
" if b ~= 0 then " @
" local q = math.floor(a/b) " @
" local r = a-q*b " @
" for i = 1, 8 do " @
" local n = 2^(i-1) " @
" Gate.setportstate(gate, i+16, bit.band(q, n) > 0) " @
" Gate.setportstate(gate, i+24, bit.band(r, n) > 0) " @
" end " @
" else " @
" for i = 1, 8 do " @
" Gate.setportstate(gate, i+16, false) " @
" Gate.setportstate(gate, i+24, false) " @
" end " @
" end " @
"end"
;
numLogicPorts = 32;
logicPortType[0] = 1;

25
bricks/math/8bitMultiplier.cs
View File

@ -16,17 +16,20 @@ datablock fxDTSBrickData(LogicGate_8bitMultiplier_Data)
logicUIName = "8bit Multiplier";
logicUIDesc = "Multiplies A by B";
logicUpdate = "return function(gate) local a, b = 0, 0 " @
"local sum = 0 " @
"for i = 1, 8 do " @
"a = a + bool_to_int[gate.ports[i].state] * 2^(i-1) " @
"b = b + bool_to_int[gate.ports[i+8].state] * 2^(i-1) " @
"end " @
"local sum = a * b " @
"for i = 1, 16 do " @
"gate.ports[i+16]:setstate(bit.band(sum, 2^(i-1)) > 0) " @
"end end";
logicUpdate =
"return function(gate) local a, b = 0, 0 " @
" local sum = 0 " @
" for i = 1, 8 do " @
" a = a + bool_to_int[Gate.getportstate(gate, i )] * 2^(i-1) " @
" b = b + bool_to_int[Gate.getportstate(gate, i+8)] * 2^(i-1) " @
" end " @
" local sum = a * b " @
" for i = 1, 16 do " @
" Gate.setportstate(gate, i+16, bit.band(sum, 2^(i-1)) > 0) " @
" end " @
"end"
;
numLogicPorts = 32;
logicPortType[0] = 1;

32
bricks/math/8bitSubtractor.cs
View File

@ -12,23 +12,27 @@ datablock fxDTSBrickData(LogicGate_8bitSubtractor_Data)
isLogic = true;
isLogicGate = true;
isLogicInput = false;
logicUIName = "8bit Subtractor";
logicUIDesc = "Subtracts B from A";
logicUpdate = "return function(gate) local c = bool_to_int[gate.ports[17].state] " @
"local a = 0 " @
"local b = 0 " @
"for i = 1, 8 do " @
"a = bool_to_int[gate.ports[i].state] " @
"b = bool_to_int[gate.ports[i+8].state] " @
"gate.ports[i+17]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
"c = bit.bor(bit.bor(bit.band(bool_to_int[a == 0], b), bit.band(bool_to_int[a == 0], c)), bit.band(b, c)) " @
"end " @
"gate.ports[26]:setstate(c == 1) end";
logicUpdate =
"return function(gate) " @
" local c = bool_to_int[Gate.getportstate(gate, 17)] " @
" local a = 0 " @
" local b = 0 " @
" for i = 1, 8 do " @
" a = bool_to_int[Gate.getportstate(gate, i )] " @
" b = bool_to_int[Gate.getportstate(gate, i+8)] " @
" Gate.setportstate(gate, i+17, bit.bxor(bit.bxor(a, b), c) == 1) " @
" c = bit.bor(bit.bor(bit.band(bool_to_int[a == 0], b), bit.band(bool_to_int[a == 0], c)), bit.band(b, c)) " @
" end " @
" Gate.setportstate(gate, 26, c == 1) " @
"end"
;
numLogicPorts = 26;
logicPortType[0] = 1;
logicPortPos[0] = "-1 -1 0";
logicPortDir[0] = 3;

14
bricks/math/FullAdder.cs
View File

@ -15,11 +15,15 @@ datablock fxDTSBrickData(LogicGate_FullAdder_Data)
logicUIName = "Full Adder";
logicUIDesc = "Adds A and B with carry in";
logicUpdate = "return function(gate) local a, b, c = bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state], bool_to_int[gate.ports[3].state] " @
"gate.ports[4]:setstate(bit.bxor(bit.bxor(a, b), c) == 1) " @
"gate.ports[5]:setstate(bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b)) == 1) end";
logicUpdate =
"return function(gate) " @
" local a, b, c = bool_to_int[Gate.getportstate(gate, 1)], bool_to_int[Gate.getportstate(gate, 2)], bool_to_int[Gate.getportstate(gate, 3)] " @
" Gate.setportstate(gate, 4, bit.bxor(bit.bxor(a, b), c) == 1) " @
" Gate.setportstate(gate, 5, bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b)) == 1) " @
"end"
;
numLogicPorts = 5;
logicPortType[0] = 1;

12
bricks/math/HalfAdder.cs
View File

@ -15,10 +15,14 @@ datablock fxDTSBrickData(LogicGate_HalfAdder_Data)
logicUIName = "Half Adder";
logicUIDesc = "Adds A and B";
logicUpdate = "return function(gate) gate.ports[3]:setstate(bit.bxor(bool_to_int[gate.ports[1].state], bool_to_int[gate.ports[2].state]) == 1) " @
"gate.ports[4]:setstate(gate.ports[1].state and gate.ports[2].state) end";
logicUpdate =
"return function(gate) " @
" Gate.setportstate(gate, 3, bit.bxor(bool_to_int[Gate.getportstate(gate, 1)], bool_to_int[Gate.getportstate(gate, 2)]) == 1) " @
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1) and Gate.getportstate(gate, 2)) " @
"end"
;
numLogicPorts = 4;
logicPortType[0] = 1;