remove active low buses; add vertical gates and more rom sizes
This commit is contained in:
Redo0
55
bricks/gen/newcode/AND 2 Bit Vertical.cs
Normal file
55
bricks/gen/newcode/AND 2 Bit Vertical.cs
Normal file
@ -0,0 +1,55 @@
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datablock fxDtsBrickData(LogicGate_GateAnd2Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 2 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 2 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 2 Bit Vertical";
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logicUIName = "AND 2 Bit Vertical";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 2";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" Gate.setportstate(gate, 3, ( " @
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" Gate.getportstate(gate, 1) and " @
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" Gate.getportstate(gate, 2) " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 3;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 1";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 -1";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 0;
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logicPortPos[2] = "0 0 -1";
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logicPortDir[2] = 1;
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logicPortUIName[2] = "Out";
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};
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62
bricks/gen/newcode/AND 3 Bit Vertical.cs
Normal file
62
bricks/gen/newcode/AND 3 Bit Vertical.cs
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@ -0,0 +1,62 @@
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datablock fxDtsBrickData(LogicGate_GateAnd3Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 3 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 3 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 3 Bit Vertical";
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logicUIName = "AND 3 Bit Vertical";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 3";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" Gate.setportstate(gate, 4, ( " @
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" Gate.getportstate(gate, 1) and " @
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" Gate.getportstate(gate, 2) and " @
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" Gate.getportstate(gate, 3) " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 4;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 2";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 -2";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 0;
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logicPortPos[3] = "0 0 -2";
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logicPortDir[3] = 1;
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logicPortUIName[3] = "Out";
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};
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69
bricks/gen/newcode/AND 4 Bit Vertical.cs
Normal file
69
bricks/gen/newcode/AND 4 Bit Vertical.cs
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@ -0,0 +1,69 @@
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datablock fxDtsBrickData(LogicGate_GateAnd4Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 4 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 4 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 4 Bit Vertical";
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logicUIName = "AND 4 Bit Vertical";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 4";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" Gate.setportstate(gate, 5, ( " @
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" Gate.getportstate(gate, 1) and " @
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" Gate.getportstate(gate, 2) and " @
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" Gate.getportstate(gate, 3) and " @
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" Gate.getportstate(gate, 4) " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 5;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 3";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 1";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 -1";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "0 0 -3";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 0;
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logicPortPos[4] = "0 0 -3";
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logicPortDir[4] = 1;
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logicPortUIName[4] = "Out";
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};
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76
bricks/gen/newcode/AND 5 Bit Vertical.cs
Normal file
76
bricks/gen/newcode/AND 5 Bit Vertical.cs
Normal file
@ -0,0 +1,76 @@
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datablock fxDtsBrickData(LogicGate_GateAnd5Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 5 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 5 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 5 Bit Vertical";
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logicUIName = "AND 5 Bit Vertical";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 5";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" Gate.setportstate(gate, 6, ( " @
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" Gate.getportstate(gate, 1) and " @
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" Gate.getportstate(gate, 2) and " @
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" Gate.getportstate(gate, 3) and " @
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" Gate.getportstate(gate, 4) and " @
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" Gate.getportstate(gate, 5) " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 6;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 4";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 2";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "0 0 -2";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "0 0 -4";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 0;
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logicPortPos[5] = "0 0 -4";
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logicPortDir[5] = 1;
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logicPortUIName[5] = "Out";
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};
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83
bricks/gen/newcode/AND 6 Bit Vertical.cs
Normal file
83
bricks/gen/newcode/AND 6 Bit Vertical.cs
Normal file
@ -0,0 +1,83 @@
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datablock fxDtsBrickData(LogicGate_GateAnd6Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 6 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 6 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 6 Bit Vertical";
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logicUIName = "AND 6 Bit Vertical";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 6";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" Gate.setportstate(gate, 7, ( " @
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" Gate.getportstate(gate, 1) and " @
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" Gate.getportstate(gate, 2) and " @
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" Gate.getportstate(gate, 3) and " @
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" Gate.getportstate(gate, 4) and " @
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" Gate.getportstate(gate, 5) and " @
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" Gate.getportstate(gate, 6) " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 7;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 5";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 3";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 1";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "0 0 -1";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "0 0 -3";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 1;
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logicPortPos[5] = "0 0 -5";
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logicPortDir[5] = 3;
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logicPortUIName[5] = "In5";
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logicPortCauseUpdate[5] = true;
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logicPortType[6] = 0;
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logicPortPos[6] = "0 0 -5";
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logicPortDir[6] = 1;
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logicPortUIName[6] = "Out";
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};
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90
bricks/gen/newcode/AND 7 Bit Vertical.cs
Normal file
90
bricks/gen/newcode/AND 7 Bit Vertical.cs
Normal file
@ -0,0 +1,90 @@
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datablock fxDtsBrickData(LogicGate_GateAnd7Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 7 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 7 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 7 Bit Vertical";
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logicUIName = "AND 7 Bit Vertical";
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logicUIDesc = "";
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|
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hasPrint = 1;
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printAspectRatio = "Logic";
|
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|
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logicBrickSize = "1 1 7";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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|
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logicInit = "";
|
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logicInput = "";
|
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logicUpdate =
|
||||
"return function(gate) " @
|
||||
" Gate.setportstate(gate, 8, ( " @
|
||||
" Gate.getportstate(gate, 1) and " @
|
||||
" Gate.getportstate(gate, 2) and " @
|
||||
" Gate.getportstate(gate, 3) and " @
|
||||
" Gate.getportstate(gate, 4) and " @
|
||||
" Gate.getportstate(gate, 5) and " @
|
||||
" Gate.getportstate(gate, 6) and " @
|
||||
" Gate.getportstate(gate, 7) " @
|
||||
" )) " @
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"end"
|
||||
;
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logicGlobal = "";
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|
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numLogicPorts = 8;
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|
||||
|
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 6";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 4";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 2";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
|
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logicPortType[3] = 1;
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logicPortPos[3] = "0 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
|
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|
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logicPortType[4] = 1;
|
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logicPortPos[4] = "0 0 -2";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 1;
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logicPortPos[5] = "0 0 -4";
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logicPortDir[5] = 3;
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logicPortUIName[5] = "In5";
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logicPortCauseUpdate[5] = true;
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logicPortType[6] = 1;
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logicPortPos[6] = "0 0 -6";
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logicPortDir[6] = 3;
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logicPortUIName[6] = "In6";
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logicPortCauseUpdate[6] = true;
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logicPortType[7] = 0;
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logicPortPos[7] = "0 0 -6";
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logicPortDir[7] = 1;
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logicPortUIName[7] = "Out";
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|
||||
};
|
||||
97
bricks/gen/newcode/AND 8 Bit Vertical.cs
Normal file
97
bricks/gen/newcode/AND 8 Bit Vertical.cs
Normal file
@ -0,0 +1,97 @@
|
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|
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datablock fxDtsBrickData(LogicGate_GateAnd8Vertical_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 8 Bit Vertical.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 8 Bit Vertical";
|
||||
|
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category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "AND 8 Bit Vertical";
|
||||
logicUIName = "AND 8 Bit Vertical";
|
||||
logicUIDesc = "";
|
||||
|
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hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 8";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" Gate.setportstate(gate, 9, ( " @
|
||||
" Gate.getportstate(gate, 1) and " @
|
||||
" Gate.getportstate(gate, 2) and " @
|
||||
" Gate.getportstate(gate, 3) and " @
|
||||
" Gate.getportstate(gate, 4) and " @
|
||||
" Gate.getportstate(gate, 5) and " @
|
||||
" Gate.getportstate(gate, 6) and " @
|
||||
" Gate.getportstate(gate, 7) and " @
|
||||
" Gate.getportstate(gate, 8) " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 7";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 5";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 3";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 1";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -1";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -3";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -5";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 -7";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "0 0 -7";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out";
|
||||
|
||||
};
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer1BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer1BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer1BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer1BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer1Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer1Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer10BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer10BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer10BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer10BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer10Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer10Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer11BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer11BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer11BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer11BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer11Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer11Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer12BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer12BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer12BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer12BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer12Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer12Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer13BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer13BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer13BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer13BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer13Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer13Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer14BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer14BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer14BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer14BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer14Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer14Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer15BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer15BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer15BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer15BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer15Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer15Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer16BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer16BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer16BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer16BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer16Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer16Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer2BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer2BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer2BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer2BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer2Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer2Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer24BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer24BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer24BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer24BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer24Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer24Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer3BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer3BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer3BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer3BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer3Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer3Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer32BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer32BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer32BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer32BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer32Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer32Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer4BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer4BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer4BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer4BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer4Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer4Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer48BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer48BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer48BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer48BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer48Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer48Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer5BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer5BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer5BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer5BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer5Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer5Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer6BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer6BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer6BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer6BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer6Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer6Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer64BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer64BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer64BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer64BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer64Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer64Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer7BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer7BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer7BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer7BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer7Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer7Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer8BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer8BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer8BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer8BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer8Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer8Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer9BitDown){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer9BitDown_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit Down";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer9BitUp){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer9BitUp_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit Up";
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer9Bit){
|
||||
datablock fxDtsBrickData(LogicGate_Buffer9Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit";
|
||||
|
||||
|
||||
@ -1,55 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl1BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 1 Bit Down";
|
||||
logicUIName = "Buffer Active Low 1 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 3) then " @
|
||||
" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 2, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
@ -1,55 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl1BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 1 Bit Up";
|
||||
logicUIName = "Buffer Active Low 1 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 3) then " @
|
||||
" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 2, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
@ -1,55 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl1Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 1 Bit";
|
||||
logicUIName = "Buffer Active Low 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 3) then " @
|
||||
" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 2, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
@ -1,163 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl10BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 10 Bit Down";
|
||||
logicUIName = "Buffer Active Low 10 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 21) then " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
@ -1,163 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl10BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 10 Bit Up";
|
||||
logicUIName = "Buffer Active Low 10 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 21) then " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
@ -1,163 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl10Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 10 Bit";
|
||||
logicUIName = "Buffer Active Low 10 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 21) then " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
@ -1,175 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl11BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 11 Bit Down";
|
||||
logicUIName = "Buffer Active Low 11 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
@ -1,175 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl11BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 11 Bit Up";
|
||||
logicUIName = "Buffer Active Low 11 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
@ -1,175 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl11Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 11 Bit";
|
||||
logicUIName = "Buffer Active Low 11 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
@ -1,187 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl12BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 12 Bit Down";
|
||||
logicUIName = "Buffer Active Low 12 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
@ -1,187 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl12BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 12 Bit Up";
|
||||
logicUIName = "Buffer Active Low 12 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
@ -1,187 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl12Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 12 Bit";
|
||||
logicUIName = "Buffer Active Low 12 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
@ -1,199 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl13BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 13 Bit Down";
|
||||
logicUIName = "Buffer Active Low 13 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
@ -1,199 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl13BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 13 Bit Up";
|
||||
logicUIName = "Buffer Active Low 13 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
@ -1,199 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl13Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 13 Bit";
|
||||
logicUIName = "Buffer Active Low 13 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
@ -1,211 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl14BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 14 Bit Down";
|
||||
logicUIName = "Buffer Active Low 14 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
@ -1,211 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl14BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 14 Bit Up";
|
||||
logicUIName = "Buffer Active Low 14 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
@ -1,211 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl14Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 14 Bit";
|
||||
logicUIName = "Buffer Active Low 14 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
@ -1,223 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl15BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 15 Bit Down";
|
||||
logicUIName = "Buffer Active Low 15 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
@ -1,223 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl15BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 15 Bit Up";
|
||||
logicUIName = "Buffer Active Low 15 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
@ -1,223 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl15Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 15 Bit";
|
||||
logicUIName = "Buffer Active Low 15 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
@ -1,235 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl16BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 16 Bit Down";
|
||||
logicUIName = "Buffer Active Low 16 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
@ -1,235 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl16BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 16 Bit Up";
|
||||
logicUIName = "Buffer Active Low 16 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
@ -1,235 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl16Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 16 Bit";
|
||||
logicUIName = "Buffer Active Low 16 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
@ -1,67 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl2BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 2 Bit Down";
|
||||
logicUIName = "Buffer Active Low 2 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
@ -1,67 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl2BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 2 Bit Up";
|
||||
logicUIName = "Buffer Active Low 2 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
@ -1,67 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl2Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 2 Bit";
|
||||
logicUIName = "Buffer Active Low 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
@ -1,331 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl24BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 24 Bit Down";
|
||||
logicUIName = "Buffer Active Low 24 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 5;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 5;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 5;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 5;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 5;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 5;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 5;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 5;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 5;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 5;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 5;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 5;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 5;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 5;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 5;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 5;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
@ -1,331 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl24BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 24 Bit Up";
|
||||
logicUIName = "Buffer Active Low 24 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 4;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 4;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 4;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 4;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 4;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 4;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 4;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 4;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 4;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 4;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 4;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 4;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 4;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 4;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 4;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 4;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
@ -1,331 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl24Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 24 Bit";
|
||||
logicUIName = "Buffer Active Low 24 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
@ -1,79 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl3BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 3 Bit Down";
|
||||
logicUIName = "Buffer Active Low 3 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
@ -1,79 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl3BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 3 Bit Up";
|
||||
logicUIName = "Buffer Active Low 3 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
@ -1,79 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl3Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 3 Bit";
|
||||
logicUIName = "Buffer Active Low 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user