add math gates
4162
bricks/gen/newbricks/Incrementer 16 Bit.blb
Normal file
1082
bricks/gen/newbricks/Incrementer 2 Bit.blb
Normal file
7682
bricks/gen/newbricks/Incrementer 32 Bit.blb
Normal file
1522
bricks/gen/newbricks/Incrementer 4 Bit.blb
Normal file
2402
bricks/gen/newbricks/Incrementer 8 Bit.blb
Normal file
7242
bricks/gen/newbricks/Multiplier 16 Bit.blb
Normal file
1082
bricks/gen/newbricks/Multiplier 2 Bit.blb
Normal file
14282
bricks/gen/newbricks/Multiplier 32 Bit.blb
Normal file
1962
bricks/gen/newbricks/Multiplier 4 Bit.blb
Normal file
3722
bricks/gen/newbricks/Multiplier 8 Bit.blb
Normal file
6032
bricks/gen/newbricks/Shifter Left 16 Bit.blb
Normal file
1082
bricks/gen/newbricks/Shifter Left 2 Bit.blb
Normal file
11422
bricks/gen/newbricks/Shifter Left 32 Bit.blb
Normal file
1852
bricks/gen/newbricks/Shifter Left 4 Bit.blb
Normal file
3282
bricks/gen/newbricks/Shifter Left 8 Bit.blb
Normal file
383
bricks/gen/newcode/Divider 16 Bit.cs
Normal file
@ -0,0 +1,383 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Divider16Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Divider 16 Bit";
|
||||||
|
logicUIName = "Divider 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 64;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "A4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "A5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "A6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "A7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "A8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "A9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "A10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "A11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "A12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "A13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "A14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "A15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-1 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "B0";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-3 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "B1";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-5 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "B2";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-7 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "B3";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-9 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "B4";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-11 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "B5";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-13 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "B6";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-15 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "B7";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-17 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "B8";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-19 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "B9";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-21 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "B10";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-23 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "B11";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-25 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "B12";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-27 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "B13";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-29 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "B14";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-31 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "B15";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "31 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "Q0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "29 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "Q1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "27 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "Q2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "25 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "Q3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "23 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "Q4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "21 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "Q5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "19 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "Q6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "17 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "Q7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "15 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "Q8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "13 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "Q9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "11 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "Q10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "9 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "Q11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "7 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "Q12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "5 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "Q13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "3 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "Q14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "1 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "Q15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "-1 1 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "R0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "-3 1 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "R1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "-5 1 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "R2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "-7 1 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "R3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "-9 1 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "R4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "-11 1 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "R5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "-13 1 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "R6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "-15 1 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "R7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "-17 1 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "R8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "-19 1 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "R9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "-21 1 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "R10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "-23 1 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "R11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "-25 1 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "R12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "-27 1 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "R13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "-29 1 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "R14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "-31 1 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "R15";
|
||||||
|
|
||||||
|
};
|
75
bricks/gen/newcode/Divider 2 Bit.cs
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Divider2Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Divider 2 Bit";
|
||||||
|
logicUIName = "Divider 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 8;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-1 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "B0";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-3 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "B1";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "3 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "Q0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "1 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Q1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "-1 1 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "R0";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "-3 1 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "R1";
|
||||||
|
|
||||||
|
};
|
735
bricks/gen/newcode/Divider 32 Bit.cs
Normal file
@ -0,0 +1,735 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Divider32Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Divider 32 Bit";
|
||||||
|
logicUIName = "Divider 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 128;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "A4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "A5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "A6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "A7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "A8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "A9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "A10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "A11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "A12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "A13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "A14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "A15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "A16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "A17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "A18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "A19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "A20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "A21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "A22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "A23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "A24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "A25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "A26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "A27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "A28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "A29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "A30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "A31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 -1 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "B0";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 -1 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "B1";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 -1 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "B2";
|
||||||
|
logicPortCauseUpdate[34] = true;
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 -1 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "B3";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 -1 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "B4";
|
||||||
|
logicPortCauseUpdate[36] = true;
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 -1 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "B5";
|
||||||
|
logicPortCauseUpdate[37] = true;
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 -1 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "B6";
|
||||||
|
logicPortCauseUpdate[38] = true;
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 -1 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "B7";
|
||||||
|
logicPortCauseUpdate[39] = true;
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 -1 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "B8";
|
||||||
|
logicPortCauseUpdate[40] = true;
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 -1 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "B9";
|
||||||
|
logicPortCauseUpdate[41] = true;
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 -1 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "B10";
|
||||||
|
logicPortCauseUpdate[42] = true;
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 -1 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "B11";
|
||||||
|
logicPortCauseUpdate[43] = true;
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 -1 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "B12";
|
||||||
|
logicPortCauseUpdate[44] = true;
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 -1 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "B13";
|
||||||
|
logicPortCauseUpdate[45] = true;
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 -1 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "B14";
|
||||||
|
logicPortCauseUpdate[46] = true;
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 -1 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "B15";
|
||||||
|
logicPortCauseUpdate[47] = true;
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 -1 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "B16";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 -1 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "B17";
|
||||||
|
logicPortCauseUpdate[49] = true;
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 -1 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "B18";
|
||||||
|
logicPortCauseUpdate[50] = true;
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 -1 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "B19";
|
||||||
|
logicPortCauseUpdate[51] = true;
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 -1 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "B20";
|
||||||
|
logicPortCauseUpdate[52] = true;
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 -1 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "B21";
|
||||||
|
logicPortCauseUpdate[53] = true;
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 -1 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "B22";
|
||||||
|
logicPortCauseUpdate[54] = true;
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 -1 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "B23";
|
||||||
|
logicPortCauseUpdate[55] = true;
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 -1 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "B24";
|
||||||
|
logicPortCauseUpdate[56] = true;
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 -1 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "B25";
|
||||||
|
logicPortCauseUpdate[57] = true;
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 -1 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "B26";
|
||||||
|
logicPortCauseUpdate[58] = true;
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 -1 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "B27";
|
||||||
|
logicPortCauseUpdate[59] = true;
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 -1 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "B28";
|
||||||
|
logicPortCauseUpdate[60] = true;
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 -1 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "B29";
|
||||||
|
logicPortCauseUpdate[61] = true;
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 -1 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "B30";
|
||||||
|
logicPortCauseUpdate[62] = true;
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 -1 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "B31";
|
||||||
|
logicPortCauseUpdate[63] = true;
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 1 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Q0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 1 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Q1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 1 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Q2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 1 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Q3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 1 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Q4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 1 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Q5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 1 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Q6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 1 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Q7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 1 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Q8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 1 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Q9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 1 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Q10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 1 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Q11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 1 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Q12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 1 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Q13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 1 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Q14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 1 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Q15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 1 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Q16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 1 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Q17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 1 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Q18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 1 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Q19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 1 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Q20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 1 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Q21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 1 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Q22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 1 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Q23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 1 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Q24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 1 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Q25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 1 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Q26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 1 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Q27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 1 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Q28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 1 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Q29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 1 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Q30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 1 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Q31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 1 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "R0";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 1 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "R1";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 1 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "R2";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 1 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "R3";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 1 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "R4";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 1 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "R5";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 1 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "R6";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 1 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "R7";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 1 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "R8";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 1 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "R9";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 1 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "R10";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 1 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "R11";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 1 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "R12";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 1 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "R13";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 1 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "R14";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 1 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "R15";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 1 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "R16";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 1 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "R17";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 1 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "R18";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 1 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "R19";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 1 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "R20";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 1 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "R21";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 1 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "R22";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 1 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "R23";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 1 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "R24";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 1 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "R25";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 1 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "R26";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 1 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "R27";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 1 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "R28";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 1 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "R29";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 1 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "R30";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 1 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "R31";
|
||||||
|
|
||||||
|
};
|
119
bricks/gen/newcode/Divider 4 Bit.cs
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Divider4Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Divider 4 Bit";
|
||||||
|
logicUIName = "Divider 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 16;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-1 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "B0";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-3 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "B1";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-5 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "B2";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-7 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "B3";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "7 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Q0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "5 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Q1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "3 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Q2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "1 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Q3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-1 1 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "R0";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-3 1 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "R1";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-5 1 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "R2";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-7 1 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "R3";
|
||||||
|
|
||||||
|
};
|
207
bricks/gen/newcode/Divider 8 Bit.cs
Normal file
@ -0,0 +1,207 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Divider8Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Divider 8 Bit";
|
||||||
|
logicUIName = "Divider 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 32;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "A4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "A5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "A6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "A7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-1 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "B0";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-3 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "B1";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-5 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "B2";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-7 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "B3";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-9 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "B4";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-11 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "B5";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-13 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "B6";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-15 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "B7";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "15 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Q0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "13 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Q1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "11 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Q2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "9 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Q3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "7 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Q4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "5 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Q5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "3 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Q6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "1 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Q7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-1 1 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "R0";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-3 1 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "R1";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-5 1 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "R2";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-7 1 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "R3";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-9 1 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "R4";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-11 1 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "R5";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "-13 1 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "R6";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "-15 1 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "R7";
|
||||||
|
|
||||||
|
};
|
230
bricks/gen/newcode/Incrementer 16 Bit.cs
Normal file
@ -0,0 +1,230 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Incrementer16Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Incrementer 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Incrementer 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Incrementer 16 Bit";
|
||||||
|
logicUIName = "Incrementer 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 36;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-1 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "I8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-3 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "I9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-5 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "I10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-7 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "I11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-9 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "I12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-11 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "I13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-13 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "I14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-15 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "I15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "15 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "O0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "13 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "O1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "11 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "O2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "9 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "O3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "7 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "O4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "5 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "O5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "3 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "O6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "1 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "O7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-1 1 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "O8";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-3 1 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "O9";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-5 1 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "O10";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-7 1 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "O11";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-9 1 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "O12";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-11 1 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "O13";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "-13 1 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "O14";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "-15 1 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "O15";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "15 -1 0";
|
||||||
|
logicPortDir[32] = 2;
|
||||||
|
logicPortUIName[32] = "Inc";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "15 1 0";
|
||||||
|
logicPortDir[33] = 2;
|
||||||
|
logicPortUIName[33] = "Dec";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "-15 -1 0";
|
||||||
|
logicPortDir[34] = 0;
|
||||||
|
logicPortUIName[34] = "COut";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-15 1 0";
|
||||||
|
logicPortDir[35] = 0;
|
||||||
|
logicPortUIName[35] = "Inv";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
};
|
76
bricks/gen/newcode/Incrementer 2 Bit.cs
Normal file
@ -0,0 +1,76 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Incrementer2Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Incrementer 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Incrementer 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Incrementer 2 Bit";
|
||||||
|
logicUIName = "Incrementer 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "2 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 8;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "1 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "-1 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 0;
|
||||||
|
logicPortPos[2] = "1 1 0";
|
||||||
|
logicPortDir[2] = 1;
|
||||||
|
logicPortUIName[2] = "O0";
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "-1 1 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "O1";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "1 -1 0";
|
||||||
|
logicPortDir[4] = 2;
|
||||||
|
logicPortUIName[4] = "Inc";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "1 1 0";
|
||||||
|
logicPortDir[5] = 2;
|
||||||
|
logicPortUIName[5] = "Dec";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "-1 -1 0";
|
||||||
|
logicPortDir[6] = 0;
|
||||||
|
logicPortUIName[6] = "COut";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-1 1 0";
|
||||||
|
logicPortDir[7] = 0;
|
||||||
|
logicPortUIName[7] = "Inv";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
};
|
406
bricks/gen/newcode/Incrementer 32 Bit.cs
Normal file
@ -0,0 +1,406 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Incrementer32Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Incrementer 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Incrementer 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Incrementer 32 Bit";
|
||||||
|
logicUIName = "Incrementer 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 68;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "I8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "I9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "I10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "I11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "I12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "I13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "I14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "I15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-1 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "I16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-3 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "I17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-5 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "I18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-7 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "I19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-9 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "I20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-11 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "I21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-13 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "I22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-15 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "I23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-17 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "I24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-19 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "I25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-21 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "I26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-23 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "I27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-25 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "I28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-27 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "I29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-29 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "I30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-31 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "I31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "31 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "O0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "29 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "O1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "27 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "O2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "25 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "O3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "23 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "O4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "21 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "O5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "19 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "O6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "17 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "O7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "15 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "O8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "13 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "O9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "11 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "O10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "9 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "O11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "7 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "O12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "5 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "O13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "3 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "O14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "1 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "O15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "-1 1 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "O16";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "-3 1 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "O17";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "-5 1 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "O18";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "-7 1 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "O19";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "-9 1 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "O20";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "-11 1 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "O21";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "-13 1 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "O22";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "-15 1 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "O23";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "-17 1 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "O24";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "-19 1 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "O25";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "-21 1 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "O26";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "-23 1 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "O27";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "-25 1 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "O28";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "-27 1 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "O29";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "-29 1 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "O30";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "-31 1 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "O31";
|
||||||
|
|
||||||
|
logicPortType[64] = 1;
|
||||||
|
logicPortPos[64] = "31 -1 0";
|
||||||
|
logicPortDir[64] = 2;
|
||||||
|
logicPortUIName[64] = "Inc";
|
||||||
|
logicPortCauseUpdate[64] = true;
|
||||||
|
|
||||||
|
logicPortType[65] = 1;
|
||||||
|
logicPortPos[65] = "31 1 0";
|
||||||
|
logicPortDir[65] = 2;
|
||||||
|
logicPortUIName[65] = "Dec";
|
||||||
|
logicPortCauseUpdate[65] = true;
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "-31 -1 0";
|
||||||
|
logicPortDir[66] = 0;
|
||||||
|
logicPortUIName[66] = "COut";
|
||||||
|
|
||||||
|
logicPortType[67] = 1;
|
||||||
|
logicPortPos[67] = "-31 1 0";
|
||||||
|
logicPortDir[67] = 0;
|
||||||
|
logicPortUIName[67] = "Inv";
|
||||||
|
logicPortCauseUpdate[67] = true;
|
||||||
|
|
||||||
|
};
|
98
bricks/gen/newcode/Incrementer 4 Bit.cs
Normal file
@ -0,0 +1,98 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Incrementer4Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Incrementer 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Incrementer 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Incrementer 4 Bit";
|
||||||
|
logicUIName = "Incrementer 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 12;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-1 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-3 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "3 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "O0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "1 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "O1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "-1 1 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "O2";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "-3 1 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "O3";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "3 -1 0";
|
||||||
|
logicPortDir[8] = 2;
|
||||||
|
logicPortUIName[8] = "Inc";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "3 1 0";
|
||||||
|
logicPortDir[9] = 2;
|
||||||
|
logicPortUIName[9] = "Dec";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "-3 -1 0";
|
||||||
|
logicPortDir[10] = 0;
|
||||||
|
logicPortUIName[10] = "COut";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-3 1 0";
|
||||||
|
logicPortDir[11] = 0;
|
||||||
|
logicPortUIName[11] = "Inv";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
};
|
142
bricks/gen/newcode/Incrementer 8 Bit.cs
Normal file
@ -0,0 +1,142 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Incrementer8Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Incrementer 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Incrementer 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Incrementer 8 Bit";
|
||||||
|
logicUIName = "Incrementer 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 20;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-1 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-3 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-5 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-7 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "7 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "O0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "5 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "O1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "3 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "O2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "1 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "O3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-1 1 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "O4";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-3 1 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "O5";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-5 1 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "O6";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-7 1 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "O7";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "7 -1 0";
|
||||||
|
logicPortDir[16] = 2;
|
||||||
|
logicPortUIName[16] = "Inc";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "7 1 0";
|
||||||
|
logicPortDir[17] = 2;
|
||||||
|
logicPortUIName[17] = "Dec";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-7 -1 0";
|
||||||
|
logicPortDir[18] = 0;
|
||||||
|
logicPortUIName[18] = "COut";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-7 1 0";
|
||||||
|
logicPortDir[19] = 0;
|
||||||
|
logicPortUIName[19] = "Inv";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
};
|
383
bricks/gen/newcode/Multiplier 16 Bit.cs
Normal file
@ -0,0 +1,383 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Multiplier16Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Multiplier 16 Bit";
|
||||||
|
logicUIName = "Multiplier 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 64;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "A4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "A5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "A6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "A7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "A8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "A9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "A10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "A11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "A12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "A13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "A14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "A15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-1 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "B0";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-3 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "B1";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-5 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "B2";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-7 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "B3";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-9 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "B4";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-11 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "B5";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-13 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "B6";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-15 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "B7";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-17 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "B8";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-19 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "B9";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-21 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "B10";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-23 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "B11";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-25 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "B12";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-27 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "B13";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-29 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "B14";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-31 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "B15";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "31 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "O0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "29 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "O1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "27 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "O2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "25 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "O3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "23 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "O4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "21 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "O5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "19 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "O6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "17 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "O7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "15 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "O8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "13 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "O9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "11 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "O10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "9 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "O11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "7 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "O12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "5 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "O13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "3 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "O14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "1 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "O15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "-1 1 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "O16";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "-3 1 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "O17";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "-5 1 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "O18";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "-7 1 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "O19";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "-9 1 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "O20";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "-11 1 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "O21";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "-13 1 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "O22";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "-15 1 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "O23";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "-17 1 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "O24";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "-19 1 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "O25";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "-21 1 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "O26";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "-23 1 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "O27";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "-25 1 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "O28";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "-27 1 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "O29";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "-29 1 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "O30";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "-31 1 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "O31";
|
||||||
|
|
||||||
|
};
|
75
bricks/gen/newcode/Multiplier 2 Bit.cs
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Multiplier2Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Multiplier 2 Bit";
|
||||||
|
logicUIName = "Multiplier 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 8;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-1 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "B0";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-3 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "B1";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "3 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "O0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "1 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "O1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "-1 1 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "O2";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "-3 1 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "O3";
|
||||||
|
|
||||||
|
};
|
735
bricks/gen/newcode/Multiplier 32 Bit.cs
Normal file
@ -0,0 +1,735 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Multiplier32Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Multiplier 32 Bit";
|
||||||
|
logicUIName = "Multiplier 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 128;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "A4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "A5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "A6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "A7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "A8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "A9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "A10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "A11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "A12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "A13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "A14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "A15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "A16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "A17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "A18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "A19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "A20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "A21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "A22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "A23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "A24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "A25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "A26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "A27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "A28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "A29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "A30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "A31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 -1 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "B0";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 -1 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "B1";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 -1 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "B2";
|
||||||
|
logicPortCauseUpdate[34] = true;
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 -1 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "B3";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 -1 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "B4";
|
||||||
|
logicPortCauseUpdate[36] = true;
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 -1 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "B5";
|
||||||
|
logicPortCauseUpdate[37] = true;
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 -1 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "B6";
|
||||||
|
logicPortCauseUpdate[38] = true;
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 -1 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "B7";
|
||||||
|
logicPortCauseUpdate[39] = true;
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 -1 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "B8";
|
||||||
|
logicPortCauseUpdate[40] = true;
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 -1 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "B9";
|
||||||
|
logicPortCauseUpdate[41] = true;
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 -1 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "B10";
|
||||||
|
logicPortCauseUpdate[42] = true;
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 -1 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "B11";
|
||||||
|
logicPortCauseUpdate[43] = true;
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 -1 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "B12";
|
||||||
|
logicPortCauseUpdate[44] = true;
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 -1 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "B13";
|
||||||
|
logicPortCauseUpdate[45] = true;
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 -1 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "B14";
|
||||||
|
logicPortCauseUpdate[46] = true;
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 -1 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "B15";
|
||||||
|
logicPortCauseUpdate[47] = true;
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 -1 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "B16";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 -1 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "B17";
|
||||||
|
logicPortCauseUpdate[49] = true;
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 -1 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "B18";
|
||||||
|
logicPortCauseUpdate[50] = true;
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 -1 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "B19";
|
||||||
|
logicPortCauseUpdate[51] = true;
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 -1 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "B20";
|
||||||
|
logicPortCauseUpdate[52] = true;
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 -1 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "B21";
|
||||||
|
logicPortCauseUpdate[53] = true;
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 -1 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "B22";
|
||||||
|
logicPortCauseUpdate[54] = true;
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 -1 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "B23";
|
||||||
|
logicPortCauseUpdate[55] = true;
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 -1 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "B24";
|
||||||
|
logicPortCauseUpdate[56] = true;
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 -1 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "B25";
|
||||||
|
logicPortCauseUpdate[57] = true;
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 -1 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "B26";
|
||||||
|
logicPortCauseUpdate[58] = true;
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 -1 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "B27";
|
||||||
|
logicPortCauseUpdate[59] = true;
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 -1 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "B28";
|
||||||
|
logicPortCauseUpdate[60] = true;
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 -1 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "B29";
|
||||||
|
logicPortCauseUpdate[61] = true;
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 -1 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "B30";
|
||||||
|
logicPortCauseUpdate[62] = true;
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 -1 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "B31";
|
||||||
|
logicPortCauseUpdate[63] = true;
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 1 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "O0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 1 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "O1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 1 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "O2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 1 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "O3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 1 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "O4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 1 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "O5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 1 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "O6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 1 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "O7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 1 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "O8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 1 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "O9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 1 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "O10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 1 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "O11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 1 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "O12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 1 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "O13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 1 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "O14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 1 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "O15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 1 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "O16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 1 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "O17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 1 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "O18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 1 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "O19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 1 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "O20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 1 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "O21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 1 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "O22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 1 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "O23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 1 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "O24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 1 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "O25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 1 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "O26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 1 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "O27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 1 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "O28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 1 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "O29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 1 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "O30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 1 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "O31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 1 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "O32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 1 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "O33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 1 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "O34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 1 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "O35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 1 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "O36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 1 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "O37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 1 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "O38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 1 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "O39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 1 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "O40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 1 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "O41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 1 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "O42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 1 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "O43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 1 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "O44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 1 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "O45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 1 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "O46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 1 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "O47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 1 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "O48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 1 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "O49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 1 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "O50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 1 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "O51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 1 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "O52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 1 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "O53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 1 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "O54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 1 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "O55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 1 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "O56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 1 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "O57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 1 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "O58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 1 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "O59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 1 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "O60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 1 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "O61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 1 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "O62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 1 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "O63";
|
||||||
|
|
||||||
|
};
|
119
bricks/gen/newcode/Multiplier 4 Bit.cs
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Multiplier4Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Multiplier 4 Bit";
|
||||||
|
logicUIName = "Multiplier 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 16;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-1 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "B0";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-3 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "B1";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-5 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "B2";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-7 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "B3";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "7 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "O0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "5 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "O1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "3 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "O2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "1 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "O3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-1 1 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "O4";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-3 1 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "O5";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-5 1 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "O6";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-7 1 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "O7";
|
||||||
|
|
||||||
|
};
|
207
bricks/gen/newcode/Multiplier 8 Bit.cs
Normal file
@ -0,0 +1,207 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Multiplier8Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Multiplier 8 Bit";
|
||||||
|
logicUIName = "Multiplier 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 32;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "A0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "A1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "A2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "A3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "A4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "A5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "A6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "A7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-1 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "B0";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-3 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "B1";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-5 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "B2";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-7 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "B3";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-9 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "B4";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-11 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "B5";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-13 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "B6";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-15 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "B7";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "15 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "O0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "13 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "O1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "11 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "O2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "9 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "O3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "7 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "O4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "5 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "O5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "3 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "O6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "1 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "O7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-1 1 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "O8";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-3 1 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "O9";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-5 1 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "O10";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-7 1 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "O11";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-9 1 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "O12";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-11 1 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "O13";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "-13 1 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "O14";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "-15 1 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "O15";
|
||||||
|
|
||||||
|
};
|
317
bricks/gen/newcode/Shifter Left 16 Bit.cs
Normal file
@ -0,0 +1,317 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterLeft16Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Left 16 Bit";
|
||||||
|
logicUIName = "Shifter Left 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 53;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "I8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "I9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "I10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "I11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "I12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "I13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "I14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "I15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "31 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "O0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "29 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "O1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "27 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "O2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "25 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "O3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "23 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "O4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "21 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "O5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "19 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "O6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "17 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "O7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "15 1 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "O8";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "13 1 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "O9";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "11 1 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "O10";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "9 1 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "O11";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "7 1 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "O12";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "5 1 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "O13";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "3 1 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "O14";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "1 1 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "O15";
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "-1 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "O16";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "-3 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "O17";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "-5 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "O18";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "-7 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "O19";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "-9 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "O20";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "-11 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "O21";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "-13 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "O22";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "-15 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "O23";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "-17 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "O24";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "-19 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "O25";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "-21 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "O26";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "-23 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "O27";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "-25 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "O28";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "-27 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "O29";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "-29 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "O30";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "-31 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "O31";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-25 -1 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "S0";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-27 -1 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "S1";
|
||||||
|
logicPortCauseUpdate[49] = true;
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-29 -1 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "S2";
|
||||||
|
logicPortCauseUpdate[50] = true;
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-31 -1 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "S3";
|
||||||
|
logicPortCauseUpdate[51] = true;
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "31 -1 0";
|
||||||
|
logicPortDir[52] = 2;
|
||||||
|
logicPortUIName[52] = "Fill";
|
||||||
|
logicPortCauseUpdate[52] = true;
|
||||||
|
|
||||||
|
};
|
75
bricks/gen/newcode/Shifter Left 2 Bit.cs
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterLeft2Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Left 2 Bit";
|
||||||
|
logicUIName = "Shifter Left 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 8;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 0;
|
||||||
|
logicPortPos[2] = "3 1 0";
|
||||||
|
logicPortDir[2] = 1;
|
||||||
|
logicPortUIName[2] = "O0";
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "1 1 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "O1";
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "-1 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "O2";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "-3 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "O3";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "S0";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "3 -1 0";
|
||||||
|
logicPortDir[7] = 2;
|
||||||
|
logicPortUIName[7] = "Fill";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
};
|
579
bricks/gen/newcode/Shifter Left 32 Bit.cs
Normal file
@ -0,0 +1,579 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterLeft32Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Left 32 Bit";
|
||||||
|
logicUIName = "Shifter Left 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 102;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "I8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "I9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "I10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "I11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "I12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "I13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "I14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "I15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "I16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "I17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "I18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "I19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "I20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "I21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "I22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "I23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "I24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "I25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "I26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "I27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "I28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "I29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "I30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "I31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "63 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "O0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "61 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "O1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "59 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "O2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "57 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "O3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "55 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "O4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "53 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "O5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "51 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "O6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "49 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "O7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "47 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "O8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "45 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "O9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "43 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "O10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "41 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "O11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "39 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "O12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "37 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "O13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "35 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "O14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "33 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "O15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "31 1 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "O16";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "29 1 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "O17";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "27 1 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "O18";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "25 1 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "O19";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "23 1 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "O20";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "21 1 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "O21";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "19 1 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "O22";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "17 1 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "O23";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "15 1 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "O24";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "13 1 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "O25";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "11 1 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "O26";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "9 1 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "O27";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "7 1 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "O28";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "5 1 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "O29";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "3 1 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "O30";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "1 1 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "O31";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "-1 1 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "O32";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "-3 1 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "O33";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "-5 1 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "O34";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "-7 1 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "O35";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "-9 1 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "O36";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "-11 1 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "O37";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "-13 1 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "O38";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "-15 1 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "O39";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-17 1 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "O40";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-19 1 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "O41";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-21 1 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "O42";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-23 1 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "O43";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-25 1 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "O44";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-27 1 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "O45";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-29 1 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "O46";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-31 1 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "O47";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-33 1 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "O48";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-35 1 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "O49";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-37 1 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "O50";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-39 1 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "O51";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-41 1 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "O52";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-43 1 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "O53";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-45 1 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "O54";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-47 1 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "O55";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-49 1 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "O56";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-51 1 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "O57";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-53 1 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "O58";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-55 1 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "O59";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-57 1 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "O60";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-59 1 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "O61";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-61 1 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "O62";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-63 1 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "O63";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "-55 -1 0";
|
||||||
|
logicPortDir[96] = 3;
|
||||||
|
logicPortUIName[96] = "S0";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
logicPortType[97] = 1;
|
||||||
|
logicPortPos[97] = "-57 -1 0";
|
||||||
|
logicPortDir[97] = 3;
|
||||||
|
logicPortUIName[97] = "S1";
|
||||||
|
logicPortCauseUpdate[97] = true;
|
||||||
|
|
||||||
|
logicPortType[98] = 1;
|
||||||
|
logicPortPos[98] = "-59 -1 0";
|
||||||
|
logicPortDir[98] = 3;
|
||||||
|
logicPortUIName[98] = "S2";
|
||||||
|
logicPortCauseUpdate[98] = true;
|
||||||
|
|
||||||
|
logicPortType[99] = 1;
|
||||||
|
logicPortPos[99] = "-61 -1 0";
|
||||||
|
logicPortDir[99] = 3;
|
||||||
|
logicPortUIName[99] = "S3";
|
||||||
|
logicPortCauseUpdate[99] = true;
|
||||||
|
|
||||||
|
logicPortType[100] = 1;
|
||||||
|
logicPortPos[100] = "-63 -1 0";
|
||||||
|
logicPortDir[100] = 3;
|
||||||
|
logicPortUIName[100] = "S4";
|
||||||
|
logicPortCauseUpdate[100] = true;
|
||||||
|
|
||||||
|
logicPortType[101] = 1;
|
||||||
|
logicPortPos[101] = "63 -1 0";
|
||||||
|
logicPortDir[101] = 2;
|
||||||
|
logicPortUIName[101] = "Fill";
|
||||||
|
logicPortCauseUpdate[101] = true;
|
||||||
|
|
||||||
|
};
|
113
bricks/gen/newcode/Shifter Left 4 Bit.cs
Normal file
@ -0,0 +1,113 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterLeft4Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Left 4 Bit";
|
||||||
|
logicUIName = "Shifter Left 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 15;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "7 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "O0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "5 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "O1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "3 1 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "O2";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "1 1 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "O3";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "-1 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "O4";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "-3 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "O5";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "-5 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "O6";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "-7 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "O7";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-5 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "S0";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-7 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "S1";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "7 -1 0";
|
||||||
|
logicPortDir[14] = 2;
|
||||||
|
logicPortUIName[14] = "Fill";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
};
|
183
bricks/gen/newcode/Shifter Left 8 Bit.cs
Normal file
@ -0,0 +1,183 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterLeft8Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Left 8 Bit";
|
||||||
|
logicUIName = "Shifter Left 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 28;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "15 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "O0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "13 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "O1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "11 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "O2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "9 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "O3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "7 1 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "O4";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "5 1 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "O5";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "3 1 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "O6";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "1 1 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "O7";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "-1 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "O8";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-3 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "O9";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-5 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "O10";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-7 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "O11";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-9 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "O12";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-11 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "O13";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-13 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "O14";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-15 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "O15";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-11 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "S0";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-13 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "S1";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-15 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "S2";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "15 -1 0";
|
||||||
|
logicPortDir[27] = 2;
|
||||||
|
logicPortUIName[27] = "Fill";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
};
|
317
bricks/gen/newcode/Shifter Right 16 Bit.cs
Normal file
@ -0,0 +1,317 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterRight16Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Right 16 Bit";
|
||||||
|
logicUIName = "Shifter Right 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 53;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "I8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "I9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "I10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "I11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "I12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "I13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "I14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "I15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "31 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "O0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "29 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "O1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "27 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "O2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "25 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "O3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "23 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "O4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "21 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "O5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "19 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "O6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "17 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "O7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "15 1 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "O8";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "13 1 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "O9";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "11 1 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "O10";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "9 1 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "O11";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "7 1 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "O12";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "5 1 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "O13";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "3 1 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "O14";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "1 1 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "O15";
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "-1 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "O16";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "-3 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "O17";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "-5 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "O18";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "-7 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "O19";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "-9 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "O20";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "-11 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "O21";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "-13 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "O22";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "-15 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "O23";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "-17 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "O24";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "-19 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "O25";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "-21 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "O26";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "-23 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "O27";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "-25 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "O28";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "-27 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "O29";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "-29 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "O30";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "-31 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "O31";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-25 -1 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "S0";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-27 -1 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "S1";
|
||||||
|
logicPortCauseUpdate[49] = true;
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-29 -1 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "S2";
|
||||||
|
logicPortCauseUpdate[50] = true;
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-31 -1 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "S3";
|
||||||
|
logicPortCauseUpdate[51] = true;
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "31 -1 0";
|
||||||
|
logicPortDir[52] = 2;
|
||||||
|
logicPortUIName[52] = "Fill";
|
||||||
|
logicPortCauseUpdate[52] = true;
|
||||||
|
|
||||||
|
};
|
75
bricks/gen/newcode/Shifter Right 2 Bit.cs
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterRight2Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Right 2 Bit";
|
||||||
|
logicUIName = "Shifter Right 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 8;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 0;
|
||||||
|
logicPortPos[2] = "3 1 0";
|
||||||
|
logicPortDir[2] = 1;
|
||||||
|
logicPortUIName[2] = "O0";
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "1 1 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "O1";
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "-1 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "O2";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "-3 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "O3";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "S0";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "3 -1 0";
|
||||||
|
logicPortDir[7] = 2;
|
||||||
|
logicPortUIName[7] = "Fill";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
};
|
579
bricks/gen/newcode/Shifter Right 32 Bit.cs
Normal file
@ -0,0 +1,579 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterRight32Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Right 32 Bit";
|
||||||
|
logicUIName = "Shifter Right 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 102;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 -1 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "I8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 -1 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "I9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 -1 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "I10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 -1 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "I11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "I12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "I13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 -1 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "I14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 -1 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "I15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 -1 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "I16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 -1 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "I17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 -1 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "I18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 -1 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "I19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 -1 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "I20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 -1 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "I21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 -1 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "I22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 -1 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "I23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "I24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "I25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "I26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 -1 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "I27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 -1 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "I28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 -1 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "I29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 -1 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "I30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 -1 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "I31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "63 1 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "O0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "61 1 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "O1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "59 1 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "O2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "57 1 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "O3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "55 1 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "O4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "53 1 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "O5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "51 1 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "O6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "49 1 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "O7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "47 1 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "O8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "45 1 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "O9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "43 1 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "O10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "41 1 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "O11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "39 1 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "O12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "37 1 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "O13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "35 1 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "O14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "33 1 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "O15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "31 1 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "O16";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "29 1 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "O17";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "27 1 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "O18";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "25 1 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "O19";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "23 1 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "O20";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "21 1 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "O21";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "19 1 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "O22";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "17 1 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "O23";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "15 1 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "O24";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "13 1 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "O25";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "11 1 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "O26";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "9 1 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "O27";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "7 1 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "O28";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "5 1 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "O29";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "3 1 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "O30";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "1 1 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "O31";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "-1 1 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "O32";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "-3 1 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "O33";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "-5 1 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "O34";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "-7 1 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "O35";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "-9 1 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "O36";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "-11 1 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "O37";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "-13 1 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "O38";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "-15 1 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "O39";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-17 1 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "O40";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-19 1 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "O41";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-21 1 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "O42";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-23 1 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "O43";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-25 1 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "O44";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-27 1 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "O45";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-29 1 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "O46";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-31 1 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "O47";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-33 1 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "O48";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-35 1 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "O49";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-37 1 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "O50";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-39 1 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "O51";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-41 1 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "O52";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-43 1 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "O53";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-45 1 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "O54";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-47 1 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "O55";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-49 1 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "O56";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-51 1 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "O57";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-53 1 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "O58";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-55 1 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "O59";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-57 1 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "O60";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-59 1 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "O61";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-61 1 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "O62";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-63 1 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "O63";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "-55 -1 0";
|
||||||
|
logicPortDir[96] = 3;
|
||||||
|
logicPortUIName[96] = "S0";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
logicPortType[97] = 1;
|
||||||
|
logicPortPos[97] = "-57 -1 0";
|
||||||
|
logicPortDir[97] = 3;
|
||||||
|
logicPortUIName[97] = "S1";
|
||||||
|
logicPortCauseUpdate[97] = true;
|
||||||
|
|
||||||
|
logicPortType[98] = 1;
|
||||||
|
logicPortPos[98] = "-59 -1 0";
|
||||||
|
logicPortDir[98] = 3;
|
||||||
|
logicPortUIName[98] = "S2";
|
||||||
|
logicPortCauseUpdate[98] = true;
|
||||||
|
|
||||||
|
logicPortType[99] = 1;
|
||||||
|
logicPortPos[99] = "-61 -1 0";
|
||||||
|
logicPortDir[99] = 3;
|
||||||
|
logicPortUIName[99] = "S3";
|
||||||
|
logicPortCauseUpdate[99] = true;
|
||||||
|
|
||||||
|
logicPortType[100] = 1;
|
||||||
|
logicPortPos[100] = "-63 -1 0";
|
||||||
|
logicPortDir[100] = 3;
|
||||||
|
logicPortUIName[100] = "S4";
|
||||||
|
logicPortCauseUpdate[100] = true;
|
||||||
|
|
||||||
|
logicPortType[101] = 1;
|
||||||
|
logicPortPos[101] = "63 -1 0";
|
||||||
|
logicPortDir[101] = 2;
|
||||||
|
logicPortUIName[101] = "Fill";
|
||||||
|
logicPortCauseUpdate[101] = true;
|
||||||
|
|
||||||
|
};
|
113
bricks/gen/newcode/Shifter Right 4 Bit.cs
Normal file
@ -0,0 +1,113 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterRight4Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Right 4 Bit";
|
||||||
|
logicUIName = "Shifter Right 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 15;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "7 1 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "O0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "5 1 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "O1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "3 1 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "O2";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "1 1 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "O3";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "-1 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "O4";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "-3 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "O5";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "-5 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "O6";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "-7 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "O7";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-5 -1 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "S0";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-7 -1 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "S1";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "7 -1 0";
|
||||||
|
logicPortDir[14] = 2;
|
||||||
|
logicPortUIName[14] = "Fill";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
};
|
183
bricks/gen/newcode/Shifter Right 8 Bit.cs
Normal file
@ -0,0 +1,183 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_ShifterRight8Bit_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Shifter Left 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Shifter Left 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Math";
|
||||||
|
uiName = "Shifter Right 8 Bit";
|
||||||
|
logicUIName = "Shifter Right 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 2 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate = "";
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 28;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 -1 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "I0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 -1 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "I1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 -1 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "I2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 -1 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "I3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 -1 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "I4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 -1 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "I5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 -1 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "I6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 -1 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "I7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "15 1 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "O0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "13 1 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "O1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "11 1 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "O2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "9 1 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "O3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "7 1 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "O4";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "5 1 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "O5";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "3 1 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "O6";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "1 1 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "O7";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "-1 1 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "O8";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-3 1 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "O9";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-5 1 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "O10";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-7 1 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "O11";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-9 1 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "O12";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-11 1 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "O13";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-13 1 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "O14";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-15 1 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "O15";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-11 -1 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "S0";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-13 -1 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "S1";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-15 -1 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "S2";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "15 -1 0";
|
||||||
|
logicPortDir[27] = 2;
|
||||||
|
logicPortUIName[27] = "Fill";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
};
|
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bricks/gen/newicons/Incrementer 16 Bit.png
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After Width: | Height: | Size: 711 B |
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bricks/gen/newicons/Incrementer 2 Bit.png
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After Width: | Height: | Size: 639 B |
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bricks/gen/newicons/Incrementer 32 Bit.png
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After Width: | Height: | Size: 565 B |
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bricks/gen/newicons/Incrementer 4 Bit.png
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After Width: | Height: | Size: 786 B |
BIN
bricks/gen/newicons/Incrementer 8 Bit.png
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After Width: | Height: | Size: 817 B |
BIN
bricks/gen/newicons/Multiplier 16 Bit.png
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After Width: | Height: | Size: 597 B |
BIN
bricks/gen/newicons/Multiplier 2 Bit.png
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After Width: | Height: | Size: 770 B |
BIN
bricks/gen/newicons/Multiplier 32 Bit.png
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After Width: | Height: | Size: 608 B |
BIN
bricks/gen/newicons/Multiplier 4 Bit.png
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After Width: | Height: | Size: 949 B |
BIN
bricks/gen/newicons/Multiplier 8 Bit.png
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After Width: | Height: | Size: 642 B |
BIN
bricks/gen/newicons/Shifter Left 16 Bit.png
Normal file
After Width: | Height: | Size: 592 B |
BIN
bricks/gen/newicons/Shifter Left 2 Bit.png
Normal file
After Width: | Height: | Size: 783 B |
BIN
bricks/gen/newicons/Shifter Left 32 Bit.png
Normal file
After Width: | Height: | Size: 598 B |
BIN
bricks/gen/newicons/Shifter Left 4 Bit.png
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After Width: | Height: | Size: 954 B |
BIN
bricks/gen/newicons/Shifter Left 8 Bit.png
Normal file
After Width: | Height: | Size: 729 B |
BIN
bricks/icons/1x1f Diode.png
Normal file
After Width: | Height: | Size: 690 B |
BIN
bricks/icons/1x1f NOT.png
Normal file
After Width: | Height: | Size: 731 B |
BIN
bricks/icons/8bit Multiplier.png
Normal file
After Width: | Height: | Size: 1.2 KiB |
BIN
bricks/icons/Diode Down.png
Normal file
After Width: | Height: | Size: 732 B |
BIN
bricks/icons/Diode Up.png
Normal file
After Width: | Height: | Size: 725 B |
BIN
bricks/icons/Full Adder.png
Normal file
After Width: | Height: | Size: 472 B |
BIN
bricks/icons/Half Adder.png
Normal file
After Width: | Height: | Size: 472 B |
BIN
bricks/icons/Input Keyboard.png
Normal file
After Width: | Height: | Size: 664 B |
BIN
bricks/icons/Not Down.png
Normal file
After Width: | Height: | Size: 736 B |
BIN
bricks/icons/Not Up.png
Normal file
After Width: | Height: | Size: 734 B |
BIN
bricks/icons/Pixel 2x2.png
Normal file
After Width: | Height: | Size: 2.4 KiB |
BIN
bricks/icons/Text Brick.png
Normal file
After Width: | Height: | Size: 632 B |
BIN
bricks/icons/serialport.png
Normal file
After Width: | Height: | Size: 14 KiB |
BIN
bricks/icons/switch.png
Normal file
After Width: | Height: | Size: 451 B |