add vertical bus bricks; delete redundant diode bricks
This commit is contained in:
Redo0
@@ -33,6 +33,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd2_Data){
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numLogicPorts = 3;
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logicPortType[0] = 1;
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logicPortPos[0] = "1 0 0";
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logicPortDir[0] = 3;
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@@ -34,6 +34,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd3_Data){
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numLogicPorts = 4;
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logicPortType[0] = 1;
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logicPortPos[0] = "2 0 0";
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logicPortDir[0] = 3;
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@@ -35,6 +35,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd4_Data){
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numLogicPorts = 5;
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logicPortType[0] = 1;
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logicPortPos[0] = "3 0 0";
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logicPortDir[0] = 3;
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@@ -36,6 +36,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd5_Data){
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numLogicPorts = 6;
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logicPortType[0] = 1;
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logicPortPos[0] = "4 0 0";
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logicPortDir[0] = 3;
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@@ -37,6 +37,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd6_Data){
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numLogicPorts = 7;
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logicPortType[0] = 1;
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logicPortPos[0] = "5 0 0";
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logicPortDir[0] = 3;
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@@ -38,6 +38,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd7_Data){
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numLogicPorts = 8;
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logicPortType[0] = 1;
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logicPortPos[0] = "6 0 0";
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logicPortDir[0] = 3;
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@@ -39,6 +39,8 @@ datablock fxDtsBrickData(LogicGate_GateAnd8_Data){
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numLogicPorts = 9;
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logicPortType[0] = 1;
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logicPortPos[0] = "7 0 0";
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logicPortDir[0] = 3;
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55
bricks/gen/newcode/Buffer 1 Bit Down.cs
Normal file
55
bricks/gen/newcode/Buffer 1 Bit Down.cs
Normal file
@@ -0,0 +1,55 @@
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datablock fxDtsBrickData(Buffer1BitDown){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit Down.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit Down";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "Buffer 1 Bit Down";
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logicUIName = "Buffer 1 Bit Down";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if Gate.getportstate(gate, 3) then " @
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" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
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" else " @
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" Gate.setportstate(gate, 2, false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 3;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 0";
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logicPortDir[0] = 4;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 0;
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logicPortPos[1] = "0 0 0";
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logicPortDir[1] = 5;
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logicPortUIName[1] = "Out0";
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 0";
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logicPortDir[2] = 2;
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logicPortUIName[2] = "Clock";
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logicPortCauseUpdate[2] = true;
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};
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55
bricks/gen/newcode/Buffer 1 Bit Up.cs
Normal file
55
bricks/gen/newcode/Buffer 1 Bit Up.cs
Normal file
@@ -0,0 +1,55 @@
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datablock fxDtsBrickData(Buffer1BitUp){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit Up.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit Up";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "Buffer 1 Bit Up";
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logicUIName = "Buffer 1 Bit Up";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if Gate.getportstate(gate, 3) then " @
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" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
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" else " @
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" Gate.setportstate(gate, 2, false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 3;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 0";
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logicPortDir[0] = 5;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 0;
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logicPortPos[1] = "0 0 0";
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logicPortDir[1] = 4;
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logicPortUIName[1] = "Out0";
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 0";
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logicPortDir[2] = 2;
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logicPortUIName[2] = "Clock";
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logicPortCauseUpdate[2] = true;
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};
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@@ -1,5 +1,5 @@
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datablock fxDtsBrickData(LogicGate_Buffer1_Data){
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datablock fxDtsBrickData(Buffer1Bit){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit";
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@@ -34,6 +34,8 @@ datablock fxDtsBrickData(LogicGate_Buffer1_Data){
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numLogicPorts = 3;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 0";
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logicPortDir[0] = 3;
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163
bricks/gen/newcode/Buffer 10 Bit Down.cs
Normal file
163
bricks/gen/newcode/Buffer 10 Bit Down.cs
Normal file
@@ -0,0 +1,163 @@
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datablock fxDtsBrickData(Buffer10BitDown){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit Down.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit Down";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "Buffer 10 Bit Down";
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logicUIName = "Buffer 10 Bit Down";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "10 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if Gate.getportstate(gate, 21) then " @
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" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
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" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
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" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
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" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
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" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
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" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
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" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
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" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
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" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
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" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
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" else " @
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" Gate.setportstate(gate, 11, false) " @
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" Gate.setportstate(gate, 12, false) " @
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" Gate.setportstate(gate, 13, false) " @
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" Gate.setportstate(gate, 14, false) " @
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" Gate.setportstate(gate, 15, false) " @
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" Gate.setportstate(gate, 16, false) " @
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" Gate.setportstate(gate, 17, false) " @
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" Gate.setportstate(gate, 18, false) " @
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" Gate.setportstate(gate, 19, false) " @
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" Gate.setportstate(gate, 20, false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 21;
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logicPortType[0] = 1;
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logicPortPos[0] = "9 0 0";
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logicPortDir[0] = 4;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 1;
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logicPortPos[1] = "7 0 0";
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logicPortDir[1] = 4;
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logicPortUIName[1] = "In1";
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logicPortType[2] = 1;
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logicPortPos[2] = "5 0 0";
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logicPortDir[2] = 4;
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logicPortUIName[2] = "In2";
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logicPortType[3] = 1;
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logicPortPos[3] = "3 0 0";
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logicPortDir[3] = 4;
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logicPortUIName[3] = "In3";
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logicPortType[4] = 1;
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logicPortPos[4] = "1 0 0";
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logicPortDir[4] = 4;
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logicPortUIName[4] = "In4";
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logicPortType[5] = 1;
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logicPortPos[5] = "-1 0 0";
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logicPortDir[5] = 4;
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logicPortUIName[5] = "In5";
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logicPortType[6] = 1;
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logicPortPos[6] = "-3 0 0";
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logicPortDir[6] = 4;
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logicPortUIName[6] = "In6";
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logicPortType[7] = 1;
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logicPortPos[7] = "-5 0 0";
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logicPortDir[7] = 4;
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logicPortUIName[7] = "In7";
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logicPortType[8] = 1;
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logicPortPos[8] = "-7 0 0";
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logicPortDir[8] = 4;
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logicPortUIName[8] = "In8";
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logicPortType[9] = 1;
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logicPortPos[9] = "-9 0 0";
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logicPortDir[9] = 4;
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logicPortUIName[9] = "In9";
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logicPortType[10] = 0;
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logicPortPos[10] = "9 0 0";
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logicPortDir[10] = 5;
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logicPortUIName[10] = "Out0";
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logicPortType[11] = 0;
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logicPortPos[11] = "7 0 0";
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logicPortDir[11] = 5;
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logicPortUIName[11] = "Out1";
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logicPortType[12] = 0;
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logicPortPos[12] = "5 0 0";
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logicPortDir[12] = 5;
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logicPortUIName[12] = "Out2";
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logicPortType[13] = 0;
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logicPortPos[13] = "3 0 0";
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logicPortDir[13] = 5;
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logicPortUIName[13] = "Out3";
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logicPortType[14] = 0;
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logicPortPos[14] = "1 0 0";
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logicPortDir[14] = 5;
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logicPortUIName[14] = "Out4";
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logicPortType[15] = 0;
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logicPortPos[15] = "-1 0 0";
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logicPortDir[15] = 5;
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logicPortUIName[15] = "Out5";
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logicPortType[16] = 0;
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logicPortPos[16] = "-3 0 0";
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logicPortDir[16] = 5;
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logicPortUIName[16] = "Out6";
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logicPortType[17] = 0;
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logicPortPos[17] = "-5 0 0";
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logicPortDir[17] = 5;
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logicPortUIName[17] = "Out7";
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logicPortType[18] = 0;
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logicPortPos[18] = "-7 0 0";
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logicPortDir[18] = 5;
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logicPortUIName[18] = "Out8";
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logicPortType[19] = 0;
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logicPortPos[19] = "-9 0 0";
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logicPortDir[19] = 5;
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logicPortUIName[19] = "Out9";
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logicPortType[20] = 1;
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logicPortPos[20] = "9 0 0";
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logicPortDir[20] = 2;
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logicPortUIName[20] = "Clock";
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logicPortCauseUpdate[20] = true;
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};
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163
bricks/gen/newcode/Buffer 10 Bit Up.cs
Normal file
163
bricks/gen/newcode/Buffer 10 Bit Up.cs
Normal file
@@ -0,0 +1,163 @@
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datablock fxDtsBrickData(Buffer10BitUp){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit Up.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit Up";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "Buffer 10 Bit Up";
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logicUIName = "Buffer 10 Bit Up";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "10 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if Gate.getportstate(gate, 21) then " @
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" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
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" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
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" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
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" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
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" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
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" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
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" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
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" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
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" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
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" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
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" else " @
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" Gate.setportstate(gate, 11, false) " @
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" Gate.setportstate(gate, 12, false) " @
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" Gate.setportstate(gate, 13, false) " @
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" Gate.setportstate(gate, 14, false) " @
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" Gate.setportstate(gate, 15, false) " @
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" Gate.setportstate(gate, 16, false) " @
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" Gate.setportstate(gate, 17, false) " @
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" Gate.setportstate(gate, 18, false) " @
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" Gate.setportstate(gate, 19, false) " @
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" Gate.setportstate(gate, 20, false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 21;
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logicPortType[0] = 1;
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logicPortPos[0] = "9 0 0";
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logicPortDir[0] = 5;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 1;
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logicPortPos[1] = "7 0 0";
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logicPortDir[1] = 5;
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logicPortUIName[1] = "In1";
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logicPortType[2] = 1;
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logicPortPos[2] = "5 0 0";
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logicPortDir[2] = 5;
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logicPortUIName[2] = "In2";
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logicPortType[3] = 1;
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logicPortPos[3] = "3 0 0";
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logicPortDir[3] = 5;
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logicPortUIName[3] = "In3";
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logicPortType[4] = 1;
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logicPortPos[4] = "1 0 0";
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logicPortDir[4] = 5;
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logicPortUIName[4] = "In4";
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logicPortType[5] = 1;
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logicPortPos[5] = "-1 0 0";
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logicPortDir[5] = 5;
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logicPortUIName[5] = "In5";
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logicPortType[6] = 1;
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logicPortPos[6] = "-3 0 0";
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logicPortDir[6] = 5;
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logicPortUIName[6] = "In6";
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logicPortType[7] = 1;
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logicPortPos[7] = "-5 0 0";
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logicPortDir[7] = 5;
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logicPortUIName[7] = "In7";
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logicPortType[8] = 1;
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logicPortPos[8] = "-7 0 0";
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logicPortDir[8] = 5;
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logicPortUIName[8] = "In8";
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logicPortType[9] = 1;
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logicPortPos[9] = "-9 0 0";
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logicPortDir[9] = 5;
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logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer10_Data){
|
||||
datablock fxDtsBrickData(Buffer10Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit";
|
||||
|
||||
@@ -52,6 +52,8 @@ datablock fxDtsBrickData(LogicGate_Buffer10_Data){
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
175
bricks/gen/newcode/Buffer 11 Bit Down.cs
Normal file
175
bricks/gen/newcode/Buffer 11 Bit Down.cs
Normal file
@@ -0,0 +1,175 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer11BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 11 Bit Down";
|
||||
logicUIName = "Buffer 11 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
175
bricks/gen/newcode/Buffer 11 Bit Up.cs
Normal file
175
bricks/gen/newcode/Buffer 11 Bit Up.cs
Normal file
@@ -0,0 +1,175 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer11BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 11 Bit Up";
|
||||
logicUIName = "Buffer 11 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer11_Data){
|
||||
datablock fxDtsBrickData(Buffer11Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit";
|
||||
|
||||
@@ -54,6 +54,8 @@ datablock fxDtsBrickData(LogicGate_Buffer11_Data){
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
187
bricks/gen/newcode/Buffer 12 Bit Down.cs
Normal file
187
bricks/gen/newcode/Buffer 12 Bit Down.cs
Normal file
@@ -0,0 +1,187 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer12BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 12 Bit Down";
|
||||
logicUIName = "Buffer 12 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
187
bricks/gen/newcode/Buffer 12 Bit Up.cs
Normal file
187
bricks/gen/newcode/Buffer 12 Bit Up.cs
Normal file
@@ -0,0 +1,187 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer12BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 12 Bit Up";
|
||||
logicUIName = "Buffer 12 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer12_Data){
|
||||
datablock fxDtsBrickData(Buffer12Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit";
|
||||
|
||||
@@ -56,6 +56,8 @@ datablock fxDtsBrickData(LogicGate_Buffer12_Data){
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
199
bricks/gen/newcode/Buffer 13 Bit Down.cs
Normal file
199
bricks/gen/newcode/Buffer 13 Bit Down.cs
Normal file
@@ -0,0 +1,199 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer13BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 13 Bit Down";
|
||||
logicUIName = "Buffer 13 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
199
bricks/gen/newcode/Buffer 13 Bit Up.cs
Normal file
199
bricks/gen/newcode/Buffer 13 Bit Up.cs
Normal file
@@ -0,0 +1,199 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer13BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 13 Bit Up";
|
||||
logicUIName = "Buffer 13 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer13_Data){
|
||||
datablock fxDtsBrickData(Buffer13Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit";
|
||||
|
||||
@@ -58,6 +58,8 @@ datablock fxDtsBrickData(LogicGate_Buffer13_Data){
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
211
bricks/gen/newcode/Buffer 14 Bit Down.cs
Normal file
211
bricks/gen/newcode/Buffer 14 Bit Down.cs
Normal file
@@ -0,0 +1,211 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer14BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 14 Bit Down";
|
||||
logicUIName = "Buffer 14 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
211
bricks/gen/newcode/Buffer 14 Bit Up.cs
Normal file
211
bricks/gen/newcode/Buffer 14 Bit Up.cs
Normal file
@@ -0,0 +1,211 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer14BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 14 Bit Up";
|
||||
logicUIName = "Buffer 14 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer14_Data){
|
||||
datablock fxDtsBrickData(Buffer14Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit";
|
||||
|
||||
@@ -60,6 +60,8 @@ datablock fxDtsBrickData(LogicGate_Buffer14_Data){
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
223
bricks/gen/newcode/Buffer 15 Bit Down.cs
Normal file
223
bricks/gen/newcode/Buffer 15 Bit Down.cs
Normal file
@@ -0,0 +1,223 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer15BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 15 Bit Down";
|
||||
logicUIName = "Buffer 15 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
223
bricks/gen/newcode/Buffer 15 Bit Up.cs
Normal file
223
bricks/gen/newcode/Buffer 15 Bit Up.cs
Normal file
@@ -0,0 +1,223 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer15BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 15 Bit Up";
|
||||
logicUIName = "Buffer 15 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer15_Data){
|
||||
datablock fxDtsBrickData(Buffer15Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit";
|
||||
|
||||
@@ -62,6 +62,8 @@ datablock fxDtsBrickData(LogicGate_Buffer15_Data){
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
235
bricks/gen/newcode/Buffer 16 Bit Down.cs
Normal file
235
bricks/gen/newcode/Buffer 16 Bit Down.cs
Normal file
@@ -0,0 +1,235 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer16BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 16 Bit Down";
|
||||
logicUIName = "Buffer 16 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
235
bricks/gen/newcode/Buffer 16 Bit Up.cs
Normal file
235
bricks/gen/newcode/Buffer 16 Bit Up.cs
Normal file
@@ -0,0 +1,235 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer16BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 16 Bit Up";
|
||||
logicUIName = "Buffer 16 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer16_Data){
|
||||
datablock fxDtsBrickData(Buffer16Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit";
|
||||
|
||||
@@ -64,6 +64,8 @@ datablock fxDtsBrickData(LogicGate_Buffer16_Data){
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
67
bricks/gen/newcode/Buffer 2 Bit Down.cs
Normal file
67
bricks/gen/newcode/Buffer 2 Bit Down.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer2BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 2 Bit Down";
|
||||
logicUIName = "Buffer 2 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
67
bricks/gen/newcode/Buffer 2 Bit Up.cs
Normal file
67
bricks/gen/newcode/Buffer 2 Bit Up.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer2BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 2 Bit Up";
|
||||
logicUIName = "Buffer 2 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer2_Data){
|
||||
datablock fxDtsBrickData(Buffer2Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit";
|
||||
|
||||
@@ -36,6 +36,8 @@ datablock fxDtsBrickData(LogicGate_Buffer2_Data){
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
331
bricks/gen/newcode/Buffer 24 Bit Down.cs
Normal file
331
bricks/gen/newcode/Buffer 24 Bit Down.cs
Normal file
@@ -0,0 +1,331 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer24BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 24 Bit Down";
|
||||
logicUIName = "Buffer 24 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 5;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 5;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 5;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 5;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 5;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 5;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 5;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 5;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 5;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 5;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 5;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 5;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 5;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 5;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 5;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 5;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
331
bricks/gen/newcode/Buffer 24 Bit Up.cs
Normal file
331
bricks/gen/newcode/Buffer 24 Bit Up.cs
Normal file
@@ -0,0 +1,331 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer24BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 24 Bit Up";
|
||||
logicUIName = "Buffer 24 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 4;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 4;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 4;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 4;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 4;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 4;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 4;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 4;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 4;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 4;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 4;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 4;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 4;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 4;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 4;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 4;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer24_Data){
|
||||
datablock fxDtsBrickData(Buffer24Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit";
|
||||
|
||||
@@ -80,6 +80,8 @@ datablock fxDtsBrickData(LogicGate_Buffer24_Data){
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
79
bricks/gen/newcode/Buffer 3 Bit Down.cs
Normal file
79
bricks/gen/newcode/Buffer 3 Bit Down.cs
Normal file
@@ -0,0 +1,79 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer3BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 3 Bit Down";
|
||||
logicUIName = "Buffer 3 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
79
bricks/gen/newcode/Buffer 3 Bit Up.cs
Normal file
79
bricks/gen/newcode/Buffer 3 Bit Up.cs
Normal file
@@ -0,0 +1,79 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer3BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 3 Bit Up";
|
||||
logicUIName = "Buffer 3 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer3_Data){
|
||||
datablock fxDtsBrickData(Buffer3Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit";
|
||||
|
||||
@@ -38,6 +38,8 @@ datablock fxDtsBrickData(LogicGate_Buffer3_Data){
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
427
bricks/gen/newcode/Buffer 32 Bit Down.cs
Normal file
427
bricks/gen/newcode/Buffer 32 Bit Down.cs
Normal file
@@ -0,0 +1,427 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer32BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 32 Bit Down";
|
||||
logicUIName = "Buffer 32 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 65) then " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 49, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 50, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 51, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 52, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 53, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 54, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 55, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 56, Gate.getportstate(gate, 24)) " @
|
||||
" Gate.setportstate(gate, 57, Gate.getportstate(gate, 25)) " @
|
||||
" Gate.setportstate(gate, 58, Gate.getportstate(gate, 26)) " @
|
||||
" Gate.setportstate(gate, 59, Gate.getportstate(gate, 27)) " @
|
||||
" Gate.setportstate(gate, 60, Gate.getportstate(gate, 28)) " @
|
||||
" Gate.setportstate(gate, 61, Gate.getportstate(gate, 29)) " @
|
||||
" Gate.setportstate(gate, 62, Gate.getportstate(gate, 30)) " @
|
||||
" Gate.setportstate(gate, 63, Gate.getportstate(gate, 31)) " @
|
||||
" Gate.setportstate(gate, 64, Gate.getportstate(gate, 32)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" Gate.setportstate(gate, 49, false) " @
|
||||
" Gate.setportstate(gate, 50, false) " @
|
||||
" Gate.setportstate(gate, 51, false) " @
|
||||
" Gate.setportstate(gate, 52, false) " @
|
||||
" Gate.setportstate(gate, 53, false) " @
|
||||
" Gate.setportstate(gate, 54, false) " @
|
||||
" Gate.setportstate(gate, 55, false) " @
|
||||
" Gate.setportstate(gate, 56, false) " @
|
||||
" Gate.setportstate(gate, 57, false) " @
|
||||
" Gate.setportstate(gate, 58, false) " @
|
||||
" Gate.setportstate(gate, 59, false) " @
|
||||
" Gate.setportstate(gate, 60, false) " @
|
||||
" Gate.setportstate(gate, 61, false) " @
|
||||
" Gate.setportstate(gate, 62, false) " @
|
||||
" Gate.setportstate(gate, 63, false) " @
|
||||
" Gate.setportstate(gate, 64, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 0 0";
|
||||
logicPortDir[32] = 5;
|
||||
logicPortUIName[32] = "Out0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 0 0";
|
||||
logicPortDir[33] = 5;
|
||||
logicPortUIName[33] = "Out1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 0 0";
|
||||
logicPortDir[34] = 5;
|
||||
logicPortUIName[34] = "Out2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 0 0";
|
||||
logicPortDir[35] = 5;
|
||||
logicPortUIName[35] = "Out3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 0 0";
|
||||
logicPortDir[36] = 5;
|
||||
logicPortUIName[36] = "Out4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 0 0";
|
||||
logicPortDir[37] = 5;
|
||||
logicPortUIName[37] = "Out5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 0 0";
|
||||
logicPortDir[38] = 5;
|
||||
logicPortUIName[38] = "Out6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 0 0";
|
||||
logicPortDir[39] = 5;
|
||||
logicPortUIName[39] = "Out7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 0 0";
|
||||
logicPortDir[40] = 5;
|
||||
logicPortUIName[40] = "Out8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 0 0";
|
||||
logicPortDir[41] = 5;
|
||||
logicPortUIName[41] = "Out9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 0 0";
|
||||
logicPortDir[42] = 5;
|
||||
logicPortUIName[42] = "Out10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 0 0";
|
||||
logicPortDir[43] = 5;
|
||||
logicPortUIName[43] = "Out11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 0 0";
|
||||
logicPortDir[44] = 5;
|
||||
logicPortUIName[44] = "Out12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 0 0";
|
||||
logicPortDir[45] = 5;
|
||||
logicPortUIName[45] = "Out13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 0 0";
|
||||
logicPortDir[46] = 5;
|
||||
logicPortUIName[46] = "Out14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 0 0";
|
||||
logicPortDir[47] = 5;
|
||||
logicPortUIName[47] = "Out15";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-1 0 0";
|
||||
logicPortDir[48] = 5;
|
||||
logicPortUIName[48] = "Out16";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-3 0 0";
|
||||
logicPortDir[49] = 5;
|
||||
logicPortUIName[49] = "Out17";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-5 0 0";
|
||||
logicPortDir[50] = 5;
|
||||
logicPortUIName[50] = "Out18";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-7 0 0";
|
||||
logicPortDir[51] = 5;
|
||||
logicPortUIName[51] = "Out19";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-9 0 0";
|
||||
logicPortDir[52] = 5;
|
||||
logicPortUIName[52] = "Out20";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-11 0 0";
|
||||
logicPortDir[53] = 5;
|
||||
logicPortUIName[53] = "Out21";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-13 0 0";
|
||||
logicPortDir[54] = 5;
|
||||
logicPortUIName[54] = "Out22";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-15 0 0";
|
||||
logicPortDir[55] = 5;
|
||||
logicPortUIName[55] = "Out23";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-17 0 0";
|
||||
logicPortDir[56] = 5;
|
||||
logicPortUIName[56] = "Out24";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-19 0 0";
|
||||
logicPortDir[57] = 5;
|
||||
logicPortUIName[57] = "Out25";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-21 0 0";
|
||||
logicPortDir[58] = 5;
|
||||
logicPortUIName[58] = "Out26";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-23 0 0";
|
||||
logicPortDir[59] = 5;
|
||||
logicPortUIName[59] = "Out27";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-25 0 0";
|
||||
logicPortDir[60] = 5;
|
||||
logicPortUIName[60] = "Out28";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-27 0 0";
|
||||
logicPortDir[61] = 5;
|
||||
logicPortUIName[61] = "Out29";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-29 0 0";
|
||||
logicPortDir[62] = 5;
|
||||
logicPortUIName[62] = "Out30";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-31 0 0";
|
||||
logicPortDir[63] = 5;
|
||||
logicPortUIName[63] = "Out31";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "31 0 0";
|
||||
logicPortDir[64] = 2;
|
||||
logicPortUIName[64] = "Clock";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
};
|
||||
427
bricks/gen/newcode/Buffer 32 Bit Up.cs
Normal file
427
bricks/gen/newcode/Buffer 32 Bit Up.cs
Normal file
@@ -0,0 +1,427 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer32BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 32 Bit Up";
|
||||
logicUIName = "Buffer 32 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 65) then " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 49, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 50, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 51, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 52, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 53, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 54, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 55, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 56, Gate.getportstate(gate, 24)) " @
|
||||
" Gate.setportstate(gate, 57, Gate.getportstate(gate, 25)) " @
|
||||
" Gate.setportstate(gate, 58, Gate.getportstate(gate, 26)) " @
|
||||
" Gate.setportstate(gate, 59, Gate.getportstate(gate, 27)) " @
|
||||
" Gate.setportstate(gate, 60, Gate.getportstate(gate, 28)) " @
|
||||
" Gate.setportstate(gate, 61, Gate.getportstate(gate, 29)) " @
|
||||
" Gate.setportstate(gate, 62, Gate.getportstate(gate, 30)) " @
|
||||
" Gate.setportstate(gate, 63, Gate.getportstate(gate, 31)) " @
|
||||
" Gate.setportstate(gate, 64, Gate.getportstate(gate, 32)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" Gate.setportstate(gate, 49, false) " @
|
||||
" Gate.setportstate(gate, 50, false) " @
|
||||
" Gate.setportstate(gate, 51, false) " @
|
||||
" Gate.setportstate(gate, 52, false) " @
|
||||
" Gate.setportstate(gate, 53, false) " @
|
||||
" Gate.setportstate(gate, 54, false) " @
|
||||
" Gate.setportstate(gate, 55, false) " @
|
||||
" Gate.setportstate(gate, 56, false) " @
|
||||
" Gate.setportstate(gate, 57, false) " @
|
||||
" Gate.setportstate(gate, 58, false) " @
|
||||
" Gate.setportstate(gate, 59, false) " @
|
||||
" Gate.setportstate(gate, 60, false) " @
|
||||
" Gate.setportstate(gate, 61, false) " @
|
||||
" Gate.setportstate(gate, 62, false) " @
|
||||
" Gate.setportstate(gate, 63, false) " @
|
||||
" Gate.setportstate(gate, 64, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 0 0";
|
||||
logicPortDir[32] = 4;
|
||||
logicPortUIName[32] = "Out0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 0 0";
|
||||
logicPortDir[33] = 4;
|
||||
logicPortUIName[33] = "Out1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 0 0";
|
||||
logicPortDir[34] = 4;
|
||||
logicPortUIName[34] = "Out2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 0 0";
|
||||
logicPortDir[35] = 4;
|
||||
logicPortUIName[35] = "Out3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 0 0";
|
||||
logicPortDir[36] = 4;
|
||||
logicPortUIName[36] = "Out4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 0 0";
|
||||
logicPortDir[37] = 4;
|
||||
logicPortUIName[37] = "Out5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 0 0";
|
||||
logicPortDir[38] = 4;
|
||||
logicPortUIName[38] = "Out6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 0 0";
|
||||
logicPortDir[39] = 4;
|
||||
logicPortUIName[39] = "Out7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 0 0";
|
||||
logicPortDir[40] = 4;
|
||||
logicPortUIName[40] = "Out8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 0 0";
|
||||
logicPortDir[41] = 4;
|
||||
logicPortUIName[41] = "Out9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 0 0";
|
||||
logicPortDir[42] = 4;
|
||||
logicPortUIName[42] = "Out10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 0 0";
|
||||
logicPortDir[43] = 4;
|
||||
logicPortUIName[43] = "Out11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 0 0";
|
||||
logicPortDir[44] = 4;
|
||||
logicPortUIName[44] = "Out12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 0 0";
|
||||
logicPortDir[45] = 4;
|
||||
logicPortUIName[45] = "Out13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 0 0";
|
||||
logicPortDir[46] = 4;
|
||||
logicPortUIName[46] = "Out14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 0 0";
|
||||
logicPortDir[47] = 4;
|
||||
logicPortUIName[47] = "Out15";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-1 0 0";
|
||||
logicPortDir[48] = 4;
|
||||
logicPortUIName[48] = "Out16";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-3 0 0";
|
||||
logicPortDir[49] = 4;
|
||||
logicPortUIName[49] = "Out17";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-5 0 0";
|
||||
logicPortDir[50] = 4;
|
||||
logicPortUIName[50] = "Out18";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-7 0 0";
|
||||
logicPortDir[51] = 4;
|
||||
logicPortUIName[51] = "Out19";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-9 0 0";
|
||||
logicPortDir[52] = 4;
|
||||
logicPortUIName[52] = "Out20";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-11 0 0";
|
||||
logicPortDir[53] = 4;
|
||||
logicPortUIName[53] = "Out21";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-13 0 0";
|
||||
logicPortDir[54] = 4;
|
||||
logicPortUIName[54] = "Out22";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-15 0 0";
|
||||
logicPortDir[55] = 4;
|
||||
logicPortUIName[55] = "Out23";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-17 0 0";
|
||||
logicPortDir[56] = 4;
|
||||
logicPortUIName[56] = "Out24";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-19 0 0";
|
||||
logicPortDir[57] = 4;
|
||||
logicPortUIName[57] = "Out25";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-21 0 0";
|
||||
logicPortDir[58] = 4;
|
||||
logicPortUIName[58] = "Out26";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-23 0 0";
|
||||
logicPortDir[59] = 4;
|
||||
logicPortUIName[59] = "Out27";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-25 0 0";
|
||||
logicPortDir[60] = 4;
|
||||
logicPortUIName[60] = "Out28";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-27 0 0";
|
||||
logicPortDir[61] = 4;
|
||||
logicPortUIName[61] = "Out29";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-29 0 0";
|
||||
logicPortDir[62] = 4;
|
||||
logicPortUIName[62] = "Out30";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-31 0 0";
|
||||
logicPortDir[63] = 4;
|
||||
logicPortUIName[63] = "Out31";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "31 0 0";
|
||||
logicPortDir[64] = 2;
|
||||
logicPortUIName[64] = "Clock";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer32_Data){
|
||||
datablock fxDtsBrickData(Buffer32Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit";
|
||||
|
||||
@@ -96,6 +96,8 @@ datablock fxDtsBrickData(LogicGate_Buffer32_Data){
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
91
bricks/gen/newcode/Buffer 4 Bit Down.cs
Normal file
91
bricks/gen/newcode/Buffer 4 Bit Down.cs
Normal file
@@ -0,0 +1,91 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer4BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 4 Bit Down";
|
||||
logicUIName = "Buffer 4 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 9) then " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 7, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 4)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" Gate.setportstate(gate, 7, false) " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 0 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
91
bricks/gen/newcode/Buffer 4 Bit Up.cs
Normal file
91
bricks/gen/newcode/Buffer 4 Bit Up.cs
Normal file
@@ -0,0 +1,91 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer4BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 4 Bit Up";
|
||||
logicUIName = "Buffer 4 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 9) then " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 7, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 4)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" Gate.setportstate(gate, 7, false) " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 0 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer4_Data){
|
||||
datablock fxDtsBrickData(Buffer4Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit";
|
||||
|
||||
@@ -40,6 +40,8 @@ datablock fxDtsBrickData(LogicGate_Buffer4_Data){
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
619
bricks/gen/newcode/Buffer 48 Bit Down.cs
Normal file
619
bricks/gen/newcode/Buffer 48 Bit Down.cs
Normal file
@@ -0,0 +1,619 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer48BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 48 Bit Down";
|
||||
logicUIName = "Buffer 48 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "48 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 97) then " @
|
||||
" Gate.setportstate(gate, 49, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 50, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 51, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 52, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 53, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 54, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 55, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 56, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 57, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 58, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 59, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 60, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 61, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 62, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 63, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 64, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 65, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 66, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 67, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 68, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 69, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 70, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 71, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 72, Gate.getportstate(gate, 24)) " @
|
||||
" Gate.setportstate(gate, 73, Gate.getportstate(gate, 25)) " @
|
||||
" Gate.setportstate(gate, 74, Gate.getportstate(gate, 26)) " @
|
||||
" Gate.setportstate(gate, 75, Gate.getportstate(gate, 27)) " @
|
||||
" Gate.setportstate(gate, 76, Gate.getportstate(gate, 28)) " @
|
||||
" Gate.setportstate(gate, 77, Gate.getportstate(gate, 29)) " @
|
||||
" Gate.setportstate(gate, 78, Gate.getportstate(gate, 30)) " @
|
||||
" Gate.setportstate(gate, 79, Gate.getportstate(gate, 31)) " @
|
||||
" Gate.setportstate(gate, 80, Gate.getportstate(gate, 32)) " @
|
||||
" Gate.setportstate(gate, 81, Gate.getportstate(gate, 33)) " @
|
||||
" Gate.setportstate(gate, 82, Gate.getportstate(gate, 34)) " @
|
||||
" Gate.setportstate(gate, 83, Gate.getportstate(gate, 35)) " @
|
||||
" Gate.setportstate(gate, 84, Gate.getportstate(gate, 36)) " @
|
||||
" Gate.setportstate(gate, 85, Gate.getportstate(gate, 37)) " @
|
||||
" Gate.setportstate(gate, 86, Gate.getportstate(gate, 38)) " @
|
||||
" Gate.setportstate(gate, 87, Gate.getportstate(gate, 39)) " @
|
||||
" Gate.setportstate(gate, 88, Gate.getportstate(gate, 40)) " @
|
||||
" Gate.setportstate(gate, 89, Gate.getportstate(gate, 41)) " @
|
||||
" Gate.setportstate(gate, 90, Gate.getportstate(gate, 42)) " @
|
||||
" Gate.setportstate(gate, 91, Gate.getportstate(gate, 43)) " @
|
||||
" Gate.setportstate(gate, 92, Gate.getportstate(gate, 44)) " @
|
||||
" Gate.setportstate(gate, 93, Gate.getportstate(gate, 45)) " @
|
||||
" Gate.setportstate(gate, 94, Gate.getportstate(gate, 46)) " @
|
||||
" Gate.setportstate(gate, 95, Gate.getportstate(gate, 47)) " @
|
||||
" Gate.setportstate(gate, 96, Gate.getportstate(gate, 48)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 49, false) " @
|
||||
" Gate.setportstate(gate, 50, false) " @
|
||||
" Gate.setportstate(gate, 51, false) " @
|
||||
" Gate.setportstate(gate, 52, false) " @
|
||||
" Gate.setportstate(gate, 53, false) " @
|
||||
" Gate.setportstate(gate, 54, false) " @
|
||||
" Gate.setportstate(gate, 55, false) " @
|
||||
" Gate.setportstate(gate, 56, false) " @
|
||||
" Gate.setportstate(gate, 57, false) " @
|
||||
" Gate.setportstate(gate, 58, false) " @
|
||||
" Gate.setportstate(gate, 59, false) " @
|
||||
" Gate.setportstate(gate, 60, false) " @
|
||||
" Gate.setportstate(gate, 61, false) " @
|
||||
" Gate.setportstate(gate, 62, false) " @
|
||||
" Gate.setportstate(gate, 63, false) " @
|
||||
" Gate.setportstate(gate, 64, false) " @
|
||||
" Gate.setportstate(gate, 65, false) " @
|
||||
" Gate.setportstate(gate, 66, false) " @
|
||||
" Gate.setportstate(gate, 67, false) " @
|
||||
" Gate.setportstate(gate, 68, false) " @
|
||||
" Gate.setportstate(gate, 69, false) " @
|
||||
" Gate.setportstate(gate, 70, false) " @
|
||||
" Gate.setportstate(gate, 71, false) " @
|
||||
" Gate.setportstate(gate, 72, false) " @
|
||||
" Gate.setportstate(gate, 73, false) " @
|
||||
" Gate.setportstate(gate, 74, false) " @
|
||||
" Gate.setportstate(gate, 75, false) " @
|
||||
" Gate.setportstate(gate, 76, false) " @
|
||||
" Gate.setportstate(gate, 77, false) " @
|
||||
" Gate.setportstate(gate, 78, false) " @
|
||||
" Gate.setportstate(gate, 79, false) " @
|
||||
" Gate.setportstate(gate, 80, false) " @
|
||||
" Gate.setportstate(gate, 81, false) " @
|
||||
" Gate.setportstate(gate, 82, false) " @
|
||||
" Gate.setportstate(gate, 83, false) " @
|
||||
" Gate.setportstate(gate, 84, false) " @
|
||||
" Gate.setportstate(gate, 85, false) " @
|
||||
" Gate.setportstate(gate, 86, false) " @
|
||||
" Gate.setportstate(gate, 87, false) " @
|
||||
" Gate.setportstate(gate, 88, false) " @
|
||||
" Gate.setportstate(gate, 89, false) " @
|
||||
" Gate.setportstate(gate, 90, false) " @
|
||||
" Gate.setportstate(gate, 91, false) " @
|
||||
" Gate.setportstate(gate, 92, false) " @
|
||||
" Gate.setportstate(gate, 93, false) " @
|
||||
" Gate.setportstate(gate, 94, false) " @
|
||||
" Gate.setportstate(gate, 95, false) " @
|
||||
" Gate.setportstate(gate, 96, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 97;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "47 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "45 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "43 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "41 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "39 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "37 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "35 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "33 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "31 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "29 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "27 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "25 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "23 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "21 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "19 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "17 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "-17 0 0";
|
||||
logicPortDir[32] = 4;
|
||||
logicPortUIName[32] = "In32";
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "-19 0 0";
|
||||
logicPortDir[33] = 4;
|
||||
logicPortUIName[33] = "In33";
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "-21 0 0";
|
||||
logicPortDir[34] = 4;
|
||||
logicPortUIName[34] = "In34";
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "-23 0 0";
|
||||
logicPortDir[35] = 4;
|
||||
logicPortUIName[35] = "In35";
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "-25 0 0";
|
||||
logicPortDir[36] = 4;
|
||||
logicPortUIName[36] = "In36";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "-27 0 0";
|
||||
logicPortDir[37] = 4;
|
||||
logicPortUIName[37] = "In37";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "-29 0 0";
|
||||
logicPortDir[38] = 4;
|
||||
logicPortUIName[38] = "In38";
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "-31 0 0";
|
||||
logicPortDir[39] = 4;
|
||||
logicPortUIName[39] = "In39";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "-33 0 0";
|
||||
logicPortDir[40] = 4;
|
||||
logicPortUIName[40] = "In40";
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "-35 0 0";
|
||||
logicPortDir[41] = 4;
|
||||
logicPortUIName[41] = "In41";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "-37 0 0";
|
||||
logicPortDir[42] = 4;
|
||||
logicPortUIName[42] = "In42";
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "-39 0 0";
|
||||
logicPortDir[43] = 4;
|
||||
logicPortUIName[43] = "In43";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "-41 0 0";
|
||||
logicPortDir[44] = 4;
|
||||
logicPortUIName[44] = "In44";
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "-43 0 0";
|
||||
logicPortDir[45] = 4;
|
||||
logicPortUIName[45] = "In45";
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "-45 0 0";
|
||||
logicPortDir[46] = 4;
|
||||
logicPortUIName[46] = "In46";
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "-47 0 0";
|
||||
logicPortDir[47] = 4;
|
||||
logicPortUIName[47] = "In47";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "47 0 0";
|
||||
logicPortDir[48] = 5;
|
||||
logicPortUIName[48] = "Out0";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "45 0 0";
|
||||
logicPortDir[49] = 5;
|
||||
logicPortUIName[49] = "Out1";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "43 0 0";
|
||||
logicPortDir[50] = 5;
|
||||
logicPortUIName[50] = "Out2";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "41 0 0";
|
||||
logicPortDir[51] = 5;
|
||||
logicPortUIName[51] = "Out3";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "39 0 0";
|
||||
logicPortDir[52] = 5;
|
||||
logicPortUIName[52] = "Out4";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "37 0 0";
|
||||
logicPortDir[53] = 5;
|
||||
logicPortUIName[53] = "Out5";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "35 0 0";
|
||||
logicPortDir[54] = 5;
|
||||
logicPortUIName[54] = "Out6";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "33 0 0";
|
||||
logicPortDir[55] = 5;
|
||||
logicPortUIName[55] = "Out7";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "31 0 0";
|
||||
logicPortDir[56] = 5;
|
||||
logicPortUIName[56] = "Out8";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "29 0 0";
|
||||
logicPortDir[57] = 5;
|
||||
logicPortUIName[57] = "Out9";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "27 0 0";
|
||||
logicPortDir[58] = 5;
|
||||
logicPortUIName[58] = "Out10";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "25 0 0";
|
||||
logicPortDir[59] = 5;
|
||||
logicPortUIName[59] = "Out11";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "23 0 0";
|
||||
logicPortDir[60] = 5;
|
||||
logicPortUIName[60] = "Out12";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "21 0 0";
|
||||
logicPortDir[61] = 5;
|
||||
logicPortUIName[61] = "Out13";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "19 0 0";
|
||||
logicPortDir[62] = 5;
|
||||
logicPortUIName[62] = "Out14";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "17 0 0";
|
||||
logicPortDir[63] = 5;
|
||||
logicPortUIName[63] = "Out15";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "15 0 0";
|
||||
logicPortDir[64] = 5;
|
||||
logicPortUIName[64] = "Out16";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "13 0 0";
|
||||
logicPortDir[65] = 5;
|
||||
logicPortUIName[65] = "Out17";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "11 0 0";
|
||||
logicPortDir[66] = 5;
|
||||
logicPortUIName[66] = "Out18";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "9 0 0";
|
||||
logicPortDir[67] = 5;
|
||||
logicPortUIName[67] = "Out19";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "7 0 0";
|
||||
logicPortDir[68] = 5;
|
||||
logicPortUIName[68] = "Out20";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "5 0 0";
|
||||
logicPortDir[69] = 5;
|
||||
logicPortUIName[69] = "Out21";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "3 0 0";
|
||||
logicPortDir[70] = 5;
|
||||
logicPortUIName[70] = "Out22";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "1 0 0";
|
||||
logicPortDir[71] = 5;
|
||||
logicPortUIName[71] = "Out23";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "-1 0 0";
|
||||
logicPortDir[72] = 5;
|
||||
logicPortUIName[72] = "Out24";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "-3 0 0";
|
||||
logicPortDir[73] = 5;
|
||||
logicPortUIName[73] = "Out25";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "-5 0 0";
|
||||
logicPortDir[74] = 5;
|
||||
logicPortUIName[74] = "Out26";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "-7 0 0";
|
||||
logicPortDir[75] = 5;
|
||||
logicPortUIName[75] = "Out27";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "-9 0 0";
|
||||
logicPortDir[76] = 5;
|
||||
logicPortUIName[76] = "Out28";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "-11 0 0";
|
||||
logicPortDir[77] = 5;
|
||||
logicPortUIName[77] = "Out29";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "-13 0 0";
|
||||
logicPortDir[78] = 5;
|
||||
logicPortUIName[78] = "Out30";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "-15 0 0";
|
||||
logicPortDir[79] = 5;
|
||||
logicPortUIName[79] = "Out31";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "-17 0 0";
|
||||
logicPortDir[80] = 5;
|
||||
logicPortUIName[80] = "Out32";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "-19 0 0";
|
||||
logicPortDir[81] = 5;
|
||||
logicPortUIName[81] = "Out33";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "-21 0 0";
|
||||
logicPortDir[82] = 5;
|
||||
logicPortUIName[82] = "Out34";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "-23 0 0";
|
||||
logicPortDir[83] = 5;
|
||||
logicPortUIName[83] = "Out35";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "-25 0 0";
|
||||
logicPortDir[84] = 5;
|
||||
logicPortUIName[84] = "Out36";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "-27 0 0";
|
||||
logicPortDir[85] = 5;
|
||||
logicPortUIName[85] = "Out37";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "-29 0 0";
|
||||
logicPortDir[86] = 5;
|
||||
logicPortUIName[86] = "Out38";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "-31 0 0";
|
||||
logicPortDir[87] = 5;
|
||||
logicPortUIName[87] = "Out39";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "-33 0 0";
|
||||
logicPortDir[88] = 5;
|
||||
logicPortUIName[88] = "Out40";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "-35 0 0";
|
||||
logicPortDir[89] = 5;
|
||||
logicPortUIName[89] = "Out41";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "-37 0 0";
|
||||
logicPortDir[90] = 5;
|
||||
logicPortUIName[90] = "Out42";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "-39 0 0";
|
||||
logicPortDir[91] = 5;
|
||||
logicPortUIName[91] = "Out43";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "-41 0 0";
|
||||
logicPortDir[92] = 5;
|
||||
logicPortUIName[92] = "Out44";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "-43 0 0";
|
||||
logicPortDir[93] = 5;
|
||||
logicPortUIName[93] = "Out45";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "-45 0 0";
|
||||
logicPortDir[94] = 5;
|
||||
logicPortUIName[94] = "Out46";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "-47 0 0";
|
||||
logicPortDir[95] = 5;
|
||||
logicPortUIName[95] = "Out47";
|
||||
|
||||
logicPortType[96] = 1;
|
||||
logicPortPos[96] = "47 0 0";
|
||||
logicPortDir[96] = 2;
|
||||
logicPortUIName[96] = "Clock";
|
||||
logicPortCauseUpdate[96] = true;
|
||||
|
||||
};
|
||||
619
bricks/gen/newcode/Buffer 48 Bit Up.cs
Normal file
619
bricks/gen/newcode/Buffer 48 Bit Up.cs
Normal file
@@ -0,0 +1,619 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer48BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 48 Bit Up";
|
||||
logicUIName = "Buffer 48 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "48 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 97) then " @
|
||||
" Gate.setportstate(gate, 49, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 50, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 51, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 52, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 53, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 54, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 55, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 56, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 57, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 58, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 59, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 60, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 61, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 62, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 63, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 64, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 65, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 66, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 67, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 68, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 69, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 70, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 71, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 72, Gate.getportstate(gate, 24)) " @
|
||||
" Gate.setportstate(gate, 73, Gate.getportstate(gate, 25)) " @
|
||||
" Gate.setportstate(gate, 74, Gate.getportstate(gate, 26)) " @
|
||||
" Gate.setportstate(gate, 75, Gate.getportstate(gate, 27)) " @
|
||||
" Gate.setportstate(gate, 76, Gate.getportstate(gate, 28)) " @
|
||||
" Gate.setportstate(gate, 77, Gate.getportstate(gate, 29)) " @
|
||||
" Gate.setportstate(gate, 78, Gate.getportstate(gate, 30)) " @
|
||||
" Gate.setportstate(gate, 79, Gate.getportstate(gate, 31)) " @
|
||||
" Gate.setportstate(gate, 80, Gate.getportstate(gate, 32)) " @
|
||||
" Gate.setportstate(gate, 81, Gate.getportstate(gate, 33)) " @
|
||||
" Gate.setportstate(gate, 82, Gate.getportstate(gate, 34)) " @
|
||||
" Gate.setportstate(gate, 83, Gate.getportstate(gate, 35)) " @
|
||||
" Gate.setportstate(gate, 84, Gate.getportstate(gate, 36)) " @
|
||||
" Gate.setportstate(gate, 85, Gate.getportstate(gate, 37)) " @
|
||||
" Gate.setportstate(gate, 86, Gate.getportstate(gate, 38)) " @
|
||||
" Gate.setportstate(gate, 87, Gate.getportstate(gate, 39)) " @
|
||||
" Gate.setportstate(gate, 88, Gate.getportstate(gate, 40)) " @
|
||||
" Gate.setportstate(gate, 89, Gate.getportstate(gate, 41)) " @
|
||||
" Gate.setportstate(gate, 90, Gate.getportstate(gate, 42)) " @
|
||||
" Gate.setportstate(gate, 91, Gate.getportstate(gate, 43)) " @
|
||||
" Gate.setportstate(gate, 92, Gate.getportstate(gate, 44)) " @
|
||||
" Gate.setportstate(gate, 93, Gate.getportstate(gate, 45)) " @
|
||||
" Gate.setportstate(gate, 94, Gate.getportstate(gate, 46)) " @
|
||||
" Gate.setportstate(gate, 95, Gate.getportstate(gate, 47)) " @
|
||||
" Gate.setportstate(gate, 96, Gate.getportstate(gate, 48)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 49, false) " @
|
||||
" Gate.setportstate(gate, 50, false) " @
|
||||
" Gate.setportstate(gate, 51, false) " @
|
||||
" Gate.setportstate(gate, 52, false) " @
|
||||
" Gate.setportstate(gate, 53, false) " @
|
||||
" Gate.setportstate(gate, 54, false) " @
|
||||
" Gate.setportstate(gate, 55, false) " @
|
||||
" Gate.setportstate(gate, 56, false) " @
|
||||
" Gate.setportstate(gate, 57, false) " @
|
||||
" Gate.setportstate(gate, 58, false) " @
|
||||
" Gate.setportstate(gate, 59, false) " @
|
||||
" Gate.setportstate(gate, 60, false) " @
|
||||
" Gate.setportstate(gate, 61, false) " @
|
||||
" Gate.setportstate(gate, 62, false) " @
|
||||
" Gate.setportstate(gate, 63, false) " @
|
||||
" Gate.setportstate(gate, 64, false) " @
|
||||
" Gate.setportstate(gate, 65, false) " @
|
||||
" Gate.setportstate(gate, 66, false) " @
|
||||
" Gate.setportstate(gate, 67, false) " @
|
||||
" Gate.setportstate(gate, 68, false) " @
|
||||
" Gate.setportstate(gate, 69, false) " @
|
||||
" Gate.setportstate(gate, 70, false) " @
|
||||
" Gate.setportstate(gate, 71, false) " @
|
||||
" Gate.setportstate(gate, 72, false) " @
|
||||
" Gate.setportstate(gate, 73, false) " @
|
||||
" Gate.setportstate(gate, 74, false) " @
|
||||
" Gate.setportstate(gate, 75, false) " @
|
||||
" Gate.setportstate(gate, 76, false) " @
|
||||
" Gate.setportstate(gate, 77, false) " @
|
||||
" Gate.setportstate(gate, 78, false) " @
|
||||
" Gate.setportstate(gate, 79, false) " @
|
||||
" Gate.setportstate(gate, 80, false) " @
|
||||
" Gate.setportstate(gate, 81, false) " @
|
||||
" Gate.setportstate(gate, 82, false) " @
|
||||
" Gate.setportstate(gate, 83, false) " @
|
||||
" Gate.setportstate(gate, 84, false) " @
|
||||
" Gate.setportstate(gate, 85, false) " @
|
||||
" Gate.setportstate(gate, 86, false) " @
|
||||
" Gate.setportstate(gate, 87, false) " @
|
||||
" Gate.setportstate(gate, 88, false) " @
|
||||
" Gate.setportstate(gate, 89, false) " @
|
||||
" Gate.setportstate(gate, 90, false) " @
|
||||
" Gate.setportstate(gate, 91, false) " @
|
||||
" Gate.setportstate(gate, 92, false) " @
|
||||
" Gate.setportstate(gate, 93, false) " @
|
||||
" Gate.setportstate(gate, 94, false) " @
|
||||
" Gate.setportstate(gate, 95, false) " @
|
||||
" Gate.setportstate(gate, 96, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 97;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "47 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "45 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "43 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "41 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "39 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "37 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "35 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "33 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "31 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "29 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "27 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "25 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "23 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "21 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "19 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "17 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "-17 0 0";
|
||||
logicPortDir[32] = 5;
|
||||
logicPortUIName[32] = "In32";
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "-19 0 0";
|
||||
logicPortDir[33] = 5;
|
||||
logicPortUIName[33] = "In33";
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "-21 0 0";
|
||||
logicPortDir[34] = 5;
|
||||
logicPortUIName[34] = "In34";
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "-23 0 0";
|
||||
logicPortDir[35] = 5;
|
||||
logicPortUIName[35] = "In35";
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "-25 0 0";
|
||||
logicPortDir[36] = 5;
|
||||
logicPortUIName[36] = "In36";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "-27 0 0";
|
||||
logicPortDir[37] = 5;
|
||||
logicPortUIName[37] = "In37";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "-29 0 0";
|
||||
logicPortDir[38] = 5;
|
||||
logicPortUIName[38] = "In38";
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "-31 0 0";
|
||||
logicPortDir[39] = 5;
|
||||
logicPortUIName[39] = "In39";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "-33 0 0";
|
||||
logicPortDir[40] = 5;
|
||||
logicPortUIName[40] = "In40";
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "-35 0 0";
|
||||
logicPortDir[41] = 5;
|
||||
logicPortUIName[41] = "In41";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "-37 0 0";
|
||||
logicPortDir[42] = 5;
|
||||
logicPortUIName[42] = "In42";
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "-39 0 0";
|
||||
logicPortDir[43] = 5;
|
||||
logicPortUIName[43] = "In43";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "-41 0 0";
|
||||
logicPortDir[44] = 5;
|
||||
logicPortUIName[44] = "In44";
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "-43 0 0";
|
||||
logicPortDir[45] = 5;
|
||||
logicPortUIName[45] = "In45";
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "-45 0 0";
|
||||
logicPortDir[46] = 5;
|
||||
logicPortUIName[46] = "In46";
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "-47 0 0";
|
||||
logicPortDir[47] = 5;
|
||||
logicPortUIName[47] = "In47";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "47 0 0";
|
||||
logicPortDir[48] = 4;
|
||||
logicPortUIName[48] = "Out0";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "45 0 0";
|
||||
logicPortDir[49] = 4;
|
||||
logicPortUIName[49] = "Out1";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "43 0 0";
|
||||
logicPortDir[50] = 4;
|
||||
logicPortUIName[50] = "Out2";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "41 0 0";
|
||||
logicPortDir[51] = 4;
|
||||
logicPortUIName[51] = "Out3";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "39 0 0";
|
||||
logicPortDir[52] = 4;
|
||||
logicPortUIName[52] = "Out4";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "37 0 0";
|
||||
logicPortDir[53] = 4;
|
||||
logicPortUIName[53] = "Out5";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "35 0 0";
|
||||
logicPortDir[54] = 4;
|
||||
logicPortUIName[54] = "Out6";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "33 0 0";
|
||||
logicPortDir[55] = 4;
|
||||
logicPortUIName[55] = "Out7";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "31 0 0";
|
||||
logicPortDir[56] = 4;
|
||||
logicPortUIName[56] = "Out8";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "29 0 0";
|
||||
logicPortDir[57] = 4;
|
||||
logicPortUIName[57] = "Out9";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "27 0 0";
|
||||
logicPortDir[58] = 4;
|
||||
logicPortUIName[58] = "Out10";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "25 0 0";
|
||||
logicPortDir[59] = 4;
|
||||
logicPortUIName[59] = "Out11";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "23 0 0";
|
||||
logicPortDir[60] = 4;
|
||||
logicPortUIName[60] = "Out12";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "21 0 0";
|
||||
logicPortDir[61] = 4;
|
||||
logicPortUIName[61] = "Out13";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "19 0 0";
|
||||
logicPortDir[62] = 4;
|
||||
logicPortUIName[62] = "Out14";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "17 0 0";
|
||||
logicPortDir[63] = 4;
|
||||
logicPortUIName[63] = "Out15";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "15 0 0";
|
||||
logicPortDir[64] = 4;
|
||||
logicPortUIName[64] = "Out16";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "13 0 0";
|
||||
logicPortDir[65] = 4;
|
||||
logicPortUIName[65] = "Out17";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "11 0 0";
|
||||
logicPortDir[66] = 4;
|
||||
logicPortUIName[66] = "Out18";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "9 0 0";
|
||||
logicPortDir[67] = 4;
|
||||
logicPortUIName[67] = "Out19";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "7 0 0";
|
||||
logicPortDir[68] = 4;
|
||||
logicPortUIName[68] = "Out20";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "5 0 0";
|
||||
logicPortDir[69] = 4;
|
||||
logicPortUIName[69] = "Out21";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "3 0 0";
|
||||
logicPortDir[70] = 4;
|
||||
logicPortUIName[70] = "Out22";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "1 0 0";
|
||||
logicPortDir[71] = 4;
|
||||
logicPortUIName[71] = "Out23";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "-1 0 0";
|
||||
logicPortDir[72] = 4;
|
||||
logicPortUIName[72] = "Out24";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "-3 0 0";
|
||||
logicPortDir[73] = 4;
|
||||
logicPortUIName[73] = "Out25";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "-5 0 0";
|
||||
logicPortDir[74] = 4;
|
||||
logicPortUIName[74] = "Out26";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "-7 0 0";
|
||||
logicPortDir[75] = 4;
|
||||
logicPortUIName[75] = "Out27";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "-9 0 0";
|
||||
logicPortDir[76] = 4;
|
||||
logicPortUIName[76] = "Out28";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "-11 0 0";
|
||||
logicPortDir[77] = 4;
|
||||
logicPortUIName[77] = "Out29";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "-13 0 0";
|
||||
logicPortDir[78] = 4;
|
||||
logicPortUIName[78] = "Out30";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "-15 0 0";
|
||||
logicPortDir[79] = 4;
|
||||
logicPortUIName[79] = "Out31";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "-17 0 0";
|
||||
logicPortDir[80] = 4;
|
||||
logicPortUIName[80] = "Out32";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "-19 0 0";
|
||||
logicPortDir[81] = 4;
|
||||
logicPortUIName[81] = "Out33";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "-21 0 0";
|
||||
logicPortDir[82] = 4;
|
||||
logicPortUIName[82] = "Out34";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "-23 0 0";
|
||||
logicPortDir[83] = 4;
|
||||
logicPortUIName[83] = "Out35";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "-25 0 0";
|
||||
logicPortDir[84] = 4;
|
||||
logicPortUIName[84] = "Out36";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "-27 0 0";
|
||||
logicPortDir[85] = 4;
|
||||
logicPortUIName[85] = "Out37";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "-29 0 0";
|
||||
logicPortDir[86] = 4;
|
||||
logicPortUIName[86] = "Out38";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "-31 0 0";
|
||||
logicPortDir[87] = 4;
|
||||
logicPortUIName[87] = "Out39";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "-33 0 0";
|
||||
logicPortDir[88] = 4;
|
||||
logicPortUIName[88] = "Out40";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "-35 0 0";
|
||||
logicPortDir[89] = 4;
|
||||
logicPortUIName[89] = "Out41";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "-37 0 0";
|
||||
logicPortDir[90] = 4;
|
||||
logicPortUIName[90] = "Out42";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "-39 0 0";
|
||||
logicPortDir[91] = 4;
|
||||
logicPortUIName[91] = "Out43";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "-41 0 0";
|
||||
logicPortDir[92] = 4;
|
||||
logicPortUIName[92] = "Out44";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "-43 0 0";
|
||||
logicPortDir[93] = 4;
|
||||
logicPortUIName[93] = "Out45";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "-45 0 0";
|
||||
logicPortDir[94] = 4;
|
||||
logicPortUIName[94] = "Out46";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "-47 0 0";
|
||||
logicPortDir[95] = 4;
|
||||
logicPortUIName[95] = "Out47";
|
||||
|
||||
logicPortType[96] = 1;
|
||||
logicPortPos[96] = "47 0 0";
|
||||
logicPortDir[96] = 2;
|
||||
logicPortUIName[96] = "Clock";
|
||||
logicPortCauseUpdate[96] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer48_Data){
|
||||
datablock fxDtsBrickData(Buffer48Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit";
|
||||
|
||||
@@ -128,6 +128,8 @@ datablock fxDtsBrickData(LogicGate_Buffer48_Data){
|
||||
|
||||
numLogicPorts = 97;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "47 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
103
bricks/gen/newcode/Buffer 5 Bit Down.cs
Normal file
103
bricks/gen/newcode/Buffer 5 Bit Down.cs
Normal file
@@ -0,0 +1,103 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer5BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 5 Bit Down";
|
||||
logicUIName = "Buffer 5 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 11) then " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 7, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 5)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" Gate.setportstate(gate, 7, false) " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "4 0 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
103
bricks/gen/newcode/Buffer 5 Bit Up.cs
Normal file
103
bricks/gen/newcode/Buffer 5 Bit Up.cs
Normal file
@@ -0,0 +1,103 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer5BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 5 Bit Up";
|
||||
logicUIName = "Buffer 5 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 11) then " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 7, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 5)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" Gate.setportstate(gate, 7, false) " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "4 0 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer5_Data){
|
||||
datablock fxDtsBrickData(Buffer5Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit";
|
||||
|
||||
@@ -42,6 +42,8 @@ datablock fxDtsBrickData(LogicGate_Buffer5_Data){
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
115
bricks/gen/newcode/Buffer 6 Bit Down.cs
Normal file
115
bricks/gen/newcode/Buffer 6 Bit Down.cs
Normal file
@@ -0,0 +1,115 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer6BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 6 Bit Down";
|
||||
logicUIName = "Buffer 6 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 13) then " @
|
||||
" Gate.setportstate(gate, 7, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 6)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 7, false) " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "3 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "1 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-1 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-3 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-5 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
||||
115
bricks/gen/newcode/Buffer 6 Bit Up.cs
Normal file
115
bricks/gen/newcode/Buffer 6 Bit Up.cs
Normal file
@@ -0,0 +1,115 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer6BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 6 Bit Up";
|
||||
logicUIName = "Buffer 6 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 13) then " @
|
||||
" Gate.setportstate(gate, 7, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 6)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 7, false) " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "3 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "1 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-1 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-3 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-5 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer6_Data){
|
||||
datablock fxDtsBrickData(Buffer6Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit";
|
||||
|
||||
@@ -44,6 +44,8 @@ datablock fxDtsBrickData(LogicGate_Buffer6_Data){
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
811
bricks/gen/newcode/Buffer 64 Bit Down.cs
Normal file
811
bricks/gen/newcode/Buffer 64 Bit Down.cs
Normal file
@@ -0,0 +1,811 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer64BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 64 Bit Down";
|
||||
logicUIName = "Buffer 64 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 129) then " @
|
||||
" Gate.setportstate(gate, 65, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 66, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 67, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 68, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 69, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 70, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 71, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 72, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 73, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 74, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 75, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 76, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 77, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 78, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 79, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 80, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 81, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 82, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 83, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 84, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 85, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 86, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 87, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 88, Gate.getportstate(gate, 24)) " @
|
||||
" Gate.setportstate(gate, 89, Gate.getportstate(gate, 25)) " @
|
||||
" Gate.setportstate(gate, 90, Gate.getportstate(gate, 26)) " @
|
||||
" Gate.setportstate(gate, 91, Gate.getportstate(gate, 27)) " @
|
||||
" Gate.setportstate(gate, 92, Gate.getportstate(gate, 28)) " @
|
||||
" Gate.setportstate(gate, 93, Gate.getportstate(gate, 29)) " @
|
||||
" Gate.setportstate(gate, 94, Gate.getportstate(gate, 30)) " @
|
||||
" Gate.setportstate(gate, 95, Gate.getportstate(gate, 31)) " @
|
||||
" Gate.setportstate(gate, 96, Gate.getportstate(gate, 32)) " @
|
||||
" Gate.setportstate(gate, 97, Gate.getportstate(gate, 33)) " @
|
||||
" Gate.setportstate(gate, 98, Gate.getportstate(gate, 34)) " @
|
||||
" Gate.setportstate(gate, 99, Gate.getportstate(gate, 35)) " @
|
||||
" Gate.setportstate(gate, 100, Gate.getportstate(gate, 36)) " @
|
||||
" Gate.setportstate(gate, 101, Gate.getportstate(gate, 37)) " @
|
||||
" Gate.setportstate(gate, 102, Gate.getportstate(gate, 38)) " @
|
||||
" Gate.setportstate(gate, 103, Gate.getportstate(gate, 39)) " @
|
||||
" Gate.setportstate(gate, 104, Gate.getportstate(gate, 40)) " @
|
||||
" Gate.setportstate(gate, 105, Gate.getportstate(gate, 41)) " @
|
||||
" Gate.setportstate(gate, 106, Gate.getportstate(gate, 42)) " @
|
||||
" Gate.setportstate(gate, 107, Gate.getportstate(gate, 43)) " @
|
||||
" Gate.setportstate(gate, 108, Gate.getportstate(gate, 44)) " @
|
||||
" Gate.setportstate(gate, 109, Gate.getportstate(gate, 45)) " @
|
||||
" Gate.setportstate(gate, 110, Gate.getportstate(gate, 46)) " @
|
||||
" Gate.setportstate(gate, 111, Gate.getportstate(gate, 47)) " @
|
||||
" Gate.setportstate(gate, 112, Gate.getportstate(gate, 48)) " @
|
||||
" Gate.setportstate(gate, 113, Gate.getportstate(gate, 49)) " @
|
||||
" Gate.setportstate(gate, 114, Gate.getportstate(gate, 50)) " @
|
||||
" Gate.setportstate(gate, 115, Gate.getportstate(gate, 51)) " @
|
||||
" Gate.setportstate(gate, 116, Gate.getportstate(gate, 52)) " @
|
||||
" Gate.setportstate(gate, 117, Gate.getportstate(gate, 53)) " @
|
||||
" Gate.setportstate(gate, 118, Gate.getportstate(gate, 54)) " @
|
||||
" Gate.setportstate(gate, 119, Gate.getportstate(gate, 55)) " @
|
||||
" Gate.setportstate(gate, 120, Gate.getportstate(gate, 56)) " @
|
||||
" Gate.setportstate(gate, 121, Gate.getportstate(gate, 57)) " @
|
||||
" Gate.setportstate(gate, 122, Gate.getportstate(gate, 58)) " @
|
||||
" Gate.setportstate(gate, 123, Gate.getportstate(gate, 59)) " @
|
||||
" Gate.setportstate(gate, 124, Gate.getportstate(gate, 60)) " @
|
||||
" Gate.setportstate(gate, 125, Gate.getportstate(gate, 61)) " @
|
||||
" Gate.setportstate(gate, 126, Gate.getportstate(gate, 62)) " @
|
||||
" Gate.setportstate(gate, 127, Gate.getportstate(gate, 63)) " @
|
||||
" Gate.setportstate(gate, 128, Gate.getportstate(gate, 64)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 65, false) " @
|
||||
" Gate.setportstate(gate, 66, false) " @
|
||||
" Gate.setportstate(gate, 67, false) " @
|
||||
" Gate.setportstate(gate, 68, false) " @
|
||||
" Gate.setportstate(gate, 69, false) " @
|
||||
" Gate.setportstate(gate, 70, false) " @
|
||||
" Gate.setportstate(gate, 71, false) " @
|
||||
" Gate.setportstate(gate, 72, false) " @
|
||||
" Gate.setportstate(gate, 73, false) " @
|
||||
" Gate.setportstate(gate, 74, false) " @
|
||||
" Gate.setportstate(gate, 75, false) " @
|
||||
" Gate.setportstate(gate, 76, false) " @
|
||||
" Gate.setportstate(gate, 77, false) " @
|
||||
" Gate.setportstate(gate, 78, false) " @
|
||||
" Gate.setportstate(gate, 79, false) " @
|
||||
" Gate.setportstate(gate, 80, false) " @
|
||||
" Gate.setportstate(gate, 81, false) " @
|
||||
" Gate.setportstate(gate, 82, false) " @
|
||||
" Gate.setportstate(gate, 83, false) " @
|
||||
" Gate.setportstate(gate, 84, false) " @
|
||||
" Gate.setportstate(gate, 85, false) " @
|
||||
" Gate.setportstate(gate, 86, false) " @
|
||||
" Gate.setportstate(gate, 87, false) " @
|
||||
" Gate.setportstate(gate, 88, false) " @
|
||||
" Gate.setportstate(gate, 89, false) " @
|
||||
" Gate.setportstate(gate, 90, false) " @
|
||||
" Gate.setportstate(gate, 91, false) " @
|
||||
" Gate.setportstate(gate, 92, false) " @
|
||||
" Gate.setportstate(gate, 93, false) " @
|
||||
" Gate.setportstate(gate, 94, false) " @
|
||||
" Gate.setportstate(gate, 95, false) " @
|
||||
" Gate.setportstate(gate, 96, false) " @
|
||||
" Gate.setportstate(gate, 97, false) " @
|
||||
" Gate.setportstate(gate, 98, false) " @
|
||||
" Gate.setportstate(gate, 99, false) " @
|
||||
" Gate.setportstate(gate, 100, false) " @
|
||||
" Gate.setportstate(gate, 101, false) " @
|
||||
" Gate.setportstate(gate, 102, false) " @
|
||||
" Gate.setportstate(gate, 103, false) " @
|
||||
" Gate.setportstate(gate, 104, false) " @
|
||||
" Gate.setportstate(gate, 105, false) " @
|
||||
" Gate.setportstate(gate, 106, false) " @
|
||||
" Gate.setportstate(gate, 107, false) " @
|
||||
" Gate.setportstate(gate, 108, false) " @
|
||||
" Gate.setportstate(gate, 109, false) " @
|
||||
" Gate.setportstate(gate, 110, false) " @
|
||||
" Gate.setportstate(gate, 111, false) " @
|
||||
" Gate.setportstate(gate, 112, false) " @
|
||||
" Gate.setportstate(gate, 113, false) " @
|
||||
" Gate.setportstate(gate, 114, false) " @
|
||||
" Gate.setportstate(gate, 115, false) " @
|
||||
" Gate.setportstate(gate, 116, false) " @
|
||||
" Gate.setportstate(gate, 117, false) " @
|
||||
" Gate.setportstate(gate, 118, false) " @
|
||||
" Gate.setportstate(gate, 119, false) " @
|
||||
" Gate.setportstate(gate, 120, false) " @
|
||||
" Gate.setportstate(gate, 121, false) " @
|
||||
" Gate.setportstate(gate, 122, false) " @
|
||||
" Gate.setportstate(gate, 123, false) " @
|
||||
" Gate.setportstate(gate, 124, false) " @
|
||||
" Gate.setportstate(gate, 125, false) " @
|
||||
" Gate.setportstate(gate, 126, false) " @
|
||||
" Gate.setportstate(gate, 127, false) " @
|
||||
" Gate.setportstate(gate, 128, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 129;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "39 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "37 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "35 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "33 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "31 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "29 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "27 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "25 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "23 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "21 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "19 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "17 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "15 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "13 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "11 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "9 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "7 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "5 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "3 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "1 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "-1 0 0";
|
||||
logicPortDir[32] = 4;
|
||||
logicPortUIName[32] = "In32";
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "-3 0 0";
|
||||
logicPortDir[33] = 4;
|
||||
logicPortUIName[33] = "In33";
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "-5 0 0";
|
||||
logicPortDir[34] = 4;
|
||||
logicPortUIName[34] = "In34";
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "-7 0 0";
|
||||
logicPortDir[35] = 4;
|
||||
logicPortUIName[35] = "In35";
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "-9 0 0";
|
||||
logicPortDir[36] = 4;
|
||||
logicPortUIName[36] = "In36";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "-11 0 0";
|
||||
logicPortDir[37] = 4;
|
||||
logicPortUIName[37] = "In37";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "-13 0 0";
|
||||
logicPortDir[38] = 4;
|
||||
logicPortUIName[38] = "In38";
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "-15 0 0";
|
||||
logicPortDir[39] = 4;
|
||||
logicPortUIName[39] = "In39";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "-17 0 0";
|
||||
logicPortDir[40] = 4;
|
||||
logicPortUIName[40] = "In40";
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "-19 0 0";
|
||||
logicPortDir[41] = 4;
|
||||
logicPortUIName[41] = "In41";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "-21 0 0";
|
||||
logicPortDir[42] = 4;
|
||||
logicPortUIName[42] = "In42";
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "-23 0 0";
|
||||
logicPortDir[43] = 4;
|
||||
logicPortUIName[43] = "In43";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "-25 0 0";
|
||||
logicPortDir[44] = 4;
|
||||
logicPortUIName[44] = "In44";
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "-27 0 0";
|
||||
logicPortDir[45] = 4;
|
||||
logicPortUIName[45] = "In45";
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "-29 0 0";
|
||||
logicPortDir[46] = 4;
|
||||
logicPortUIName[46] = "In46";
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "-31 0 0";
|
||||
logicPortDir[47] = 4;
|
||||
logicPortUIName[47] = "In47";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "-33 0 0";
|
||||
logicPortDir[48] = 4;
|
||||
logicPortUIName[48] = "In48";
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "-35 0 0";
|
||||
logicPortDir[49] = 4;
|
||||
logicPortUIName[49] = "In49";
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "-37 0 0";
|
||||
logicPortDir[50] = 4;
|
||||
logicPortUIName[50] = "In50";
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "-39 0 0";
|
||||
logicPortDir[51] = 4;
|
||||
logicPortUIName[51] = "In51";
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "-41 0 0";
|
||||
logicPortDir[52] = 4;
|
||||
logicPortUIName[52] = "In52";
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "-43 0 0";
|
||||
logicPortDir[53] = 4;
|
||||
logicPortUIName[53] = "In53";
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "-45 0 0";
|
||||
logicPortDir[54] = 4;
|
||||
logicPortUIName[54] = "In54";
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "-47 0 0";
|
||||
logicPortDir[55] = 4;
|
||||
logicPortUIName[55] = "In55";
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "-49 0 0";
|
||||
logicPortDir[56] = 4;
|
||||
logicPortUIName[56] = "In56";
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "-51 0 0";
|
||||
logicPortDir[57] = 4;
|
||||
logicPortUIName[57] = "In57";
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "-53 0 0";
|
||||
logicPortDir[58] = 4;
|
||||
logicPortUIName[58] = "In58";
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "-55 0 0";
|
||||
logicPortDir[59] = 4;
|
||||
logicPortUIName[59] = "In59";
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "-57 0 0";
|
||||
logicPortDir[60] = 4;
|
||||
logicPortUIName[60] = "In60";
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "-59 0 0";
|
||||
logicPortDir[61] = 4;
|
||||
logicPortUIName[61] = "In61";
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "-61 0 0";
|
||||
logicPortDir[62] = 4;
|
||||
logicPortUIName[62] = "In62";
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "-63 0 0";
|
||||
logicPortDir[63] = 4;
|
||||
logicPortUIName[63] = "In63";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "63 0 0";
|
||||
logicPortDir[64] = 5;
|
||||
logicPortUIName[64] = "Out0";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "61 0 0";
|
||||
logicPortDir[65] = 5;
|
||||
logicPortUIName[65] = "Out1";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "59 0 0";
|
||||
logicPortDir[66] = 5;
|
||||
logicPortUIName[66] = "Out2";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "57 0 0";
|
||||
logicPortDir[67] = 5;
|
||||
logicPortUIName[67] = "Out3";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "55 0 0";
|
||||
logicPortDir[68] = 5;
|
||||
logicPortUIName[68] = "Out4";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "53 0 0";
|
||||
logicPortDir[69] = 5;
|
||||
logicPortUIName[69] = "Out5";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "51 0 0";
|
||||
logicPortDir[70] = 5;
|
||||
logicPortUIName[70] = "Out6";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "49 0 0";
|
||||
logicPortDir[71] = 5;
|
||||
logicPortUIName[71] = "Out7";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "47 0 0";
|
||||
logicPortDir[72] = 5;
|
||||
logicPortUIName[72] = "Out8";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "45 0 0";
|
||||
logicPortDir[73] = 5;
|
||||
logicPortUIName[73] = "Out9";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "43 0 0";
|
||||
logicPortDir[74] = 5;
|
||||
logicPortUIName[74] = "Out10";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "41 0 0";
|
||||
logicPortDir[75] = 5;
|
||||
logicPortUIName[75] = "Out11";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "39 0 0";
|
||||
logicPortDir[76] = 5;
|
||||
logicPortUIName[76] = "Out12";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "37 0 0";
|
||||
logicPortDir[77] = 5;
|
||||
logicPortUIName[77] = "Out13";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "35 0 0";
|
||||
logicPortDir[78] = 5;
|
||||
logicPortUIName[78] = "Out14";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "33 0 0";
|
||||
logicPortDir[79] = 5;
|
||||
logicPortUIName[79] = "Out15";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "31 0 0";
|
||||
logicPortDir[80] = 5;
|
||||
logicPortUIName[80] = "Out16";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "29 0 0";
|
||||
logicPortDir[81] = 5;
|
||||
logicPortUIName[81] = "Out17";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "27 0 0";
|
||||
logicPortDir[82] = 5;
|
||||
logicPortUIName[82] = "Out18";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "25 0 0";
|
||||
logicPortDir[83] = 5;
|
||||
logicPortUIName[83] = "Out19";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "23 0 0";
|
||||
logicPortDir[84] = 5;
|
||||
logicPortUIName[84] = "Out20";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "21 0 0";
|
||||
logicPortDir[85] = 5;
|
||||
logicPortUIName[85] = "Out21";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "19 0 0";
|
||||
logicPortDir[86] = 5;
|
||||
logicPortUIName[86] = "Out22";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "17 0 0";
|
||||
logicPortDir[87] = 5;
|
||||
logicPortUIName[87] = "Out23";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "15 0 0";
|
||||
logicPortDir[88] = 5;
|
||||
logicPortUIName[88] = "Out24";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "13 0 0";
|
||||
logicPortDir[89] = 5;
|
||||
logicPortUIName[89] = "Out25";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "11 0 0";
|
||||
logicPortDir[90] = 5;
|
||||
logicPortUIName[90] = "Out26";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "9 0 0";
|
||||
logicPortDir[91] = 5;
|
||||
logicPortUIName[91] = "Out27";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "7 0 0";
|
||||
logicPortDir[92] = 5;
|
||||
logicPortUIName[92] = "Out28";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "5 0 0";
|
||||
logicPortDir[93] = 5;
|
||||
logicPortUIName[93] = "Out29";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "3 0 0";
|
||||
logicPortDir[94] = 5;
|
||||
logicPortUIName[94] = "Out30";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "1 0 0";
|
||||
logicPortDir[95] = 5;
|
||||
logicPortUIName[95] = "Out31";
|
||||
|
||||
logicPortType[96] = 0;
|
||||
logicPortPos[96] = "-1 0 0";
|
||||
logicPortDir[96] = 5;
|
||||
logicPortUIName[96] = "Out32";
|
||||
|
||||
logicPortType[97] = 0;
|
||||
logicPortPos[97] = "-3 0 0";
|
||||
logicPortDir[97] = 5;
|
||||
logicPortUIName[97] = "Out33";
|
||||
|
||||
logicPortType[98] = 0;
|
||||
logicPortPos[98] = "-5 0 0";
|
||||
logicPortDir[98] = 5;
|
||||
logicPortUIName[98] = "Out34";
|
||||
|
||||
logicPortType[99] = 0;
|
||||
logicPortPos[99] = "-7 0 0";
|
||||
logicPortDir[99] = 5;
|
||||
logicPortUIName[99] = "Out35";
|
||||
|
||||
logicPortType[100] = 0;
|
||||
logicPortPos[100] = "-9 0 0";
|
||||
logicPortDir[100] = 5;
|
||||
logicPortUIName[100] = "Out36";
|
||||
|
||||
logicPortType[101] = 0;
|
||||
logicPortPos[101] = "-11 0 0";
|
||||
logicPortDir[101] = 5;
|
||||
logicPortUIName[101] = "Out37";
|
||||
|
||||
logicPortType[102] = 0;
|
||||
logicPortPos[102] = "-13 0 0";
|
||||
logicPortDir[102] = 5;
|
||||
logicPortUIName[102] = "Out38";
|
||||
|
||||
logicPortType[103] = 0;
|
||||
logicPortPos[103] = "-15 0 0";
|
||||
logicPortDir[103] = 5;
|
||||
logicPortUIName[103] = "Out39";
|
||||
|
||||
logicPortType[104] = 0;
|
||||
logicPortPos[104] = "-17 0 0";
|
||||
logicPortDir[104] = 5;
|
||||
logicPortUIName[104] = "Out40";
|
||||
|
||||
logicPortType[105] = 0;
|
||||
logicPortPos[105] = "-19 0 0";
|
||||
logicPortDir[105] = 5;
|
||||
logicPortUIName[105] = "Out41";
|
||||
|
||||
logicPortType[106] = 0;
|
||||
logicPortPos[106] = "-21 0 0";
|
||||
logicPortDir[106] = 5;
|
||||
logicPortUIName[106] = "Out42";
|
||||
|
||||
logicPortType[107] = 0;
|
||||
logicPortPos[107] = "-23 0 0";
|
||||
logicPortDir[107] = 5;
|
||||
logicPortUIName[107] = "Out43";
|
||||
|
||||
logicPortType[108] = 0;
|
||||
logicPortPos[108] = "-25 0 0";
|
||||
logicPortDir[108] = 5;
|
||||
logicPortUIName[108] = "Out44";
|
||||
|
||||
logicPortType[109] = 0;
|
||||
logicPortPos[109] = "-27 0 0";
|
||||
logicPortDir[109] = 5;
|
||||
logicPortUIName[109] = "Out45";
|
||||
|
||||
logicPortType[110] = 0;
|
||||
logicPortPos[110] = "-29 0 0";
|
||||
logicPortDir[110] = 5;
|
||||
logicPortUIName[110] = "Out46";
|
||||
|
||||
logicPortType[111] = 0;
|
||||
logicPortPos[111] = "-31 0 0";
|
||||
logicPortDir[111] = 5;
|
||||
logicPortUIName[111] = "Out47";
|
||||
|
||||
logicPortType[112] = 0;
|
||||
logicPortPos[112] = "-33 0 0";
|
||||
logicPortDir[112] = 5;
|
||||
logicPortUIName[112] = "Out48";
|
||||
|
||||
logicPortType[113] = 0;
|
||||
logicPortPos[113] = "-35 0 0";
|
||||
logicPortDir[113] = 5;
|
||||
logicPortUIName[113] = "Out49";
|
||||
|
||||
logicPortType[114] = 0;
|
||||
logicPortPos[114] = "-37 0 0";
|
||||
logicPortDir[114] = 5;
|
||||
logicPortUIName[114] = "Out50";
|
||||
|
||||
logicPortType[115] = 0;
|
||||
logicPortPos[115] = "-39 0 0";
|
||||
logicPortDir[115] = 5;
|
||||
logicPortUIName[115] = "Out51";
|
||||
|
||||
logicPortType[116] = 0;
|
||||
logicPortPos[116] = "-41 0 0";
|
||||
logicPortDir[116] = 5;
|
||||
logicPortUIName[116] = "Out52";
|
||||
|
||||
logicPortType[117] = 0;
|
||||
logicPortPos[117] = "-43 0 0";
|
||||
logicPortDir[117] = 5;
|
||||
logicPortUIName[117] = "Out53";
|
||||
|
||||
logicPortType[118] = 0;
|
||||
logicPortPos[118] = "-45 0 0";
|
||||
logicPortDir[118] = 5;
|
||||
logicPortUIName[118] = "Out54";
|
||||
|
||||
logicPortType[119] = 0;
|
||||
logicPortPos[119] = "-47 0 0";
|
||||
logicPortDir[119] = 5;
|
||||
logicPortUIName[119] = "Out55";
|
||||
|
||||
logicPortType[120] = 0;
|
||||
logicPortPos[120] = "-49 0 0";
|
||||
logicPortDir[120] = 5;
|
||||
logicPortUIName[120] = "Out56";
|
||||
|
||||
logicPortType[121] = 0;
|
||||
logicPortPos[121] = "-51 0 0";
|
||||
logicPortDir[121] = 5;
|
||||
logicPortUIName[121] = "Out57";
|
||||
|
||||
logicPortType[122] = 0;
|
||||
logicPortPos[122] = "-53 0 0";
|
||||
logicPortDir[122] = 5;
|
||||
logicPortUIName[122] = "Out58";
|
||||
|
||||
logicPortType[123] = 0;
|
||||
logicPortPos[123] = "-55 0 0";
|
||||
logicPortDir[123] = 5;
|
||||
logicPortUIName[123] = "Out59";
|
||||
|
||||
logicPortType[124] = 0;
|
||||
logicPortPos[124] = "-57 0 0";
|
||||
logicPortDir[124] = 5;
|
||||
logicPortUIName[124] = "Out60";
|
||||
|
||||
logicPortType[125] = 0;
|
||||
logicPortPos[125] = "-59 0 0";
|
||||
logicPortDir[125] = 5;
|
||||
logicPortUIName[125] = "Out61";
|
||||
|
||||
logicPortType[126] = 0;
|
||||
logicPortPos[126] = "-61 0 0";
|
||||
logicPortDir[126] = 5;
|
||||
logicPortUIName[126] = "Out62";
|
||||
|
||||
logicPortType[127] = 0;
|
||||
logicPortPos[127] = "-63 0 0";
|
||||
logicPortDir[127] = 5;
|
||||
logicPortUIName[127] = "Out63";
|
||||
|
||||
logicPortType[128] = 1;
|
||||
logicPortPos[128] = "63 0 0";
|
||||
logicPortDir[128] = 2;
|
||||
logicPortUIName[128] = "Clock";
|
||||
logicPortCauseUpdate[128] = true;
|
||||
|
||||
};
|
||||
811
bricks/gen/newcode/Buffer 64 Bit Up.cs
Normal file
811
bricks/gen/newcode/Buffer 64 Bit Up.cs
Normal file
@@ -0,0 +1,811 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer64BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 64 Bit Up";
|
||||
logicUIName = "Buffer 64 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 129) then " @
|
||||
" Gate.setportstate(gate, 65, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 66, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 67, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 68, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 69, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 70, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 71, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 72, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 73, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 74, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 75, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 76, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 77, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 78, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 79, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 80, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 81, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 82, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 83, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 84, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 85, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 86, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 87, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 88, Gate.getportstate(gate, 24)) " @
|
||||
" Gate.setportstate(gate, 89, Gate.getportstate(gate, 25)) " @
|
||||
" Gate.setportstate(gate, 90, Gate.getportstate(gate, 26)) " @
|
||||
" Gate.setportstate(gate, 91, Gate.getportstate(gate, 27)) " @
|
||||
" Gate.setportstate(gate, 92, Gate.getportstate(gate, 28)) " @
|
||||
" Gate.setportstate(gate, 93, Gate.getportstate(gate, 29)) " @
|
||||
" Gate.setportstate(gate, 94, Gate.getportstate(gate, 30)) " @
|
||||
" Gate.setportstate(gate, 95, Gate.getportstate(gate, 31)) " @
|
||||
" Gate.setportstate(gate, 96, Gate.getportstate(gate, 32)) " @
|
||||
" Gate.setportstate(gate, 97, Gate.getportstate(gate, 33)) " @
|
||||
" Gate.setportstate(gate, 98, Gate.getportstate(gate, 34)) " @
|
||||
" Gate.setportstate(gate, 99, Gate.getportstate(gate, 35)) " @
|
||||
" Gate.setportstate(gate, 100, Gate.getportstate(gate, 36)) " @
|
||||
" Gate.setportstate(gate, 101, Gate.getportstate(gate, 37)) " @
|
||||
" Gate.setportstate(gate, 102, Gate.getportstate(gate, 38)) " @
|
||||
" Gate.setportstate(gate, 103, Gate.getportstate(gate, 39)) " @
|
||||
" Gate.setportstate(gate, 104, Gate.getportstate(gate, 40)) " @
|
||||
" Gate.setportstate(gate, 105, Gate.getportstate(gate, 41)) " @
|
||||
" Gate.setportstate(gate, 106, Gate.getportstate(gate, 42)) " @
|
||||
" Gate.setportstate(gate, 107, Gate.getportstate(gate, 43)) " @
|
||||
" Gate.setportstate(gate, 108, Gate.getportstate(gate, 44)) " @
|
||||
" Gate.setportstate(gate, 109, Gate.getportstate(gate, 45)) " @
|
||||
" Gate.setportstate(gate, 110, Gate.getportstate(gate, 46)) " @
|
||||
" Gate.setportstate(gate, 111, Gate.getportstate(gate, 47)) " @
|
||||
" Gate.setportstate(gate, 112, Gate.getportstate(gate, 48)) " @
|
||||
" Gate.setportstate(gate, 113, Gate.getportstate(gate, 49)) " @
|
||||
" Gate.setportstate(gate, 114, Gate.getportstate(gate, 50)) " @
|
||||
" Gate.setportstate(gate, 115, Gate.getportstate(gate, 51)) " @
|
||||
" Gate.setportstate(gate, 116, Gate.getportstate(gate, 52)) " @
|
||||
" Gate.setportstate(gate, 117, Gate.getportstate(gate, 53)) " @
|
||||
" Gate.setportstate(gate, 118, Gate.getportstate(gate, 54)) " @
|
||||
" Gate.setportstate(gate, 119, Gate.getportstate(gate, 55)) " @
|
||||
" Gate.setportstate(gate, 120, Gate.getportstate(gate, 56)) " @
|
||||
" Gate.setportstate(gate, 121, Gate.getportstate(gate, 57)) " @
|
||||
" Gate.setportstate(gate, 122, Gate.getportstate(gate, 58)) " @
|
||||
" Gate.setportstate(gate, 123, Gate.getportstate(gate, 59)) " @
|
||||
" Gate.setportstate(gate, 124, Gate.getportstate(gate, 60)) " @
|
||||
" Gate.setportstate(gate, 125, Gate.getportstate(gate, 61)) " @
|
||||
" Gate.setportstate(gate, 126, Gate.getportstate(gate, 62)) " @
|
||||
" Gate.setportstate(gate, 127, Gate.getportstate(gate, 63)) " @
|
||||
" Gate.setportstate(gate, 128, Gate.getportstate(gate, 64)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 65, false) " @
|
||||
" Gate.setportstate(gate, 66, false) " @
|
||||
" Gate.setportstate(gate, 67, false) " @
|
||||
" Gate.setportstate(gate, 68, false) " @
|
||||
" Gate.setportstate(gate, 69, false) " @
|
||||
" Gate.setportstate(gate, 70, false) " @
|
||||
" Gate.setportstate(gate, 71, false) " @
|
||||
" Gate.setportstate(gate, 72, false) " @
|
||||
" Gate.setportstate(gate, 73, false) " @
|
||||
" Gate.setportstate(gate, 74, false) " @
|
||||
" Gate.setportstate(gate, 75, false) " @
|
||||
" Gate.setportstate(gate, 76, false) " @
|
||||
" Gate.setportstate(gate, 77, false) " @
|
||||
" Gate.setportstate(gate, 78, false) " @
|
||||
" Gate.setportstate(gate, 79, false) " @
|
||||
" Gate.setportstate(gate, 80, false) " @
|
||||
" Gate.setportstate(gate, 81, false) " @
|
||||
" Gate.setportstate(gate, 82, false) " @
|
||||
" Gate.setportstate(gate, 83, false) " @
|
||||
" Gate.setportstate(gate, 84, false) " @
|
||||
" Gate.setportstate(gate, 85, false) " @
|
||||
" Gate.setportstate(gate, 86, false) " @
|
||||
" Gate.setportstate(gate, 87, false) " @
|
||||
" Gate.setportstate(gate, 88, false) " @
|
||||
" Gate.setportstate(gate, 89, false) " @
|
||||
" Gate.setportstate(gate, 90, false) " @
|
||||
" Gate.setportstate(gate, 91, false) " @
|
||||
" Gate.setportstate(gate, 92, false) " @
|
||||
" Gate.setportstate(gate, 93, false) " @
|
||||
" Gate.setportstate(gate, 94, false) " @
|
||||
" Gate.setportstate(gate, 95, false) " @
|
||||
" Gate.setportstate(gate, 96, false) " @
|
||||
" Gate.setportstate(gate, 97, false) " @
|
||||
" Gate.setportstate(gate, 98, false) " @
|
||||
" Gate.setportstate(gate, 99, false) " @
|
||||
" Gate.setportstate(gate, 100, false) " @
|
||||
" Gate.setportstate(gate, 101, false) " @
|
||||
" Gate.setportstate(gate, 102, false) " @
|
||||
" Gate.setportstate(gate, 103, false) " @
|
||||
" Gate.setportstate(gate, 104, false) " @
|
||||
" Gate.setportstate(gate, 105, false) " @
|
||||
" Gate.setportstate(gate, 106, false) " @
|
||||
" Gate.setportstate(gate, 107, false) " @
|
||||
" Gate.setportstate(gate, 108, false) " @
|
||||
" Gate.setportstate(gate, 109, false) " @
|
||||
" Gate.setportstate(gate, 110, false) " @
|
||||
" Gate.setportstate(gate, 111, false) " @
|
||||
" Gate.setportstate(gate, 112, false) " @
|
||||
" Gate.setportstate(gate, 113, false) " @
|
||||
" Gate.setportstate(gate, 114, false) " @
|
||||
" Gate.setportstate(gate, 115, false) " @
|
||||
" Gate.setportstate(gate, 116, false) " @
|
||||
" Gate.setportstate(gate, 117, false) " @
|
||||
" Gate.setportstate(gate, 118, false) " @
|
||||
" Gate.setportstate(gate, 119, false) " @
|
||||
" Gate.setportstate(gate, 120, false) " @
|
||||
" Gate.setportstate(gate, 121, false) " @
|
||||
" Gate.setportstate(gate, 122, false) " @
|
||||
" Gate.setportstate(gate, 123, false) " @
|
||||
" Gate.setportstate(gate, 124, false) " @
|
||||
" Gate.setportstate(gate, 125, false) " @
|
||||
" Gate.setportstate(gate, 126, false) " @
|
||||
" Gate.setportstate(gate, 127, false) " @
|
||||
" Gate.setportstate(gate, 128, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 129;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "39 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "37 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "35 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "33 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "31 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "29 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "27 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "25 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "23 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "21 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "19 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "17 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "15 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "13 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "11 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "9 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "7 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "5 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "3 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "1 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "-1 0 0";
|
||||
logicPortDir[32] = 5;
|
||||
logicPortUIName[32] = "In32";
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "-3 0 0";
|
||||
logicPortDir[33] = 5;
|
||||
logicPortUIName[33] = "In33";
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "-5 0 0";
|
||||
logicPortDir[34] = 5;
|
||||
logicPortUIName[34] = "In34";
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "-7 0 0";
|
||||
logicPortDir[35] = 5;
|
||||
logicPortUIName[35] = "In35";
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "-9 0 0";
|
||||
logicPortDir[36] = 5;
|
||||
logicPortUIName[36] = "In36";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "-11 0 0";
|
||||
logicPortDir[37] = 5;
|
||||
logicPortUIName[37] = "In37";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "-13 0 0";
|
||||
logicPortDir[38] = 5;
|
||||
logicPortUIName[38] = "In38";
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "-15 0 0";
|
||||
logicPortDir[39] = 5;
|
||||
logicPortUIName[39] = "In39";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "-17 0 0";
|
||||
logicPortDir[40] = 5;
|
||||
logicPortUIName[40] = "In40";
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "-19 0 0";
|
||||
logicPortDir[41] = 5;
|
||||
logicPortUIName[41] = "In41";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "-21 0 0";
|
||||
logicPortDir[42] = 5;
|
||||
logicPortUIName[42] = "In42";
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "-23 0 0";
|
||||
logicPortDir[43] = 5;
|
||||
logicPortUIName[43] = "In43";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "-25 0 0";
|
||||
logicPortDir[44] = 5;
|
||||
logicPortUIName[44] = "In44";
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "-27 0 0";
|
||||
logicPortDir[45] = 5;
|
||||
logicPortUIName[45] = "In45";
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "-29 0 0";
|
||||
logicPortDir[46] = 5;
|
||||
logicPortUIName[46] = "In46";
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "-31 0 0";
|
||||
logicPortDir[47] = 5;
|
||||
logicPortUIName[47] = "In47";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "-33 0 0";
|
||||
logicPortDir[48] = 5;
|
||||
logicPortUIName[48] = "In48";
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "-35 0 0";
|
||||
logicPortDir[49] = 5;
|
||||
logicPortUIName[49] = "In49";
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "-37 0 0";
|
||||
logicPortDir[50] = 5;
|
||||
logicPortUIName[50] = "In50";
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "-39 0 0";
|
||||
logicPortDir[51] = 5;
|
||||
logicPortUIName[51] = "In51";
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "-41 0 0";
|
||||
logicPortDir[52] = 5;
|
||||
logicPortUIName[52] = "In52";
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "-43 0 0";
|
||||
logicPortDir[53] = 5;
|
||||
logicPortUIName[53] = "In53";
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "-45 0 0";
|
||||
logicPortDir[54] = 5;
|
||||
logicPortUIName[54] = "In54";
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "-47 0 0";
|
||||
logicPortDir[55] = 5;
|
||||
logicPortUIName[55] = "In55";
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "-49 0 0";
|
||||
logicPortDir[56] = 5;
|
||||
logicPortUIName[56] = "In56";
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "-51 0 0";
|
||||
logicPortDir[57] = 5;
|
||||
logicPortUIName[57] = "In57";
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "-53 0 0";
|
||||
logicPortDir[58] = 5;
|
||||
logicPortUIName[58] = "In58";
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "-55 0 0";
|
||||
logicPortDir[59] = 5;
|
||||
logicPortUIName[59] = "In59";
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "-57 0 0";
|
||||
logicPortDir[60] = 5;
|
||||
logicPortUIName[60] = "In60";
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "-59 0 0";
|
||||
logicPortDir[61] = 5;
|
||||
logicPortUIName[61] = "In61";
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "-61 0 0";
|
||||
logicPortDir[62] = 5;
|
||||
logicPortUIName[62] = "In62";
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "-63 0 0";
|
||||
logicPortDir[63] = 5;
|
||||
logicPortUIName[63] = "In63";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "63 0 0";
|
||||
logicPortDir[64] = 4;
|
||||
logicPortUIName[64] = "Out0";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "61 0 0";
|
||||
logicPortDir[65] = 4;
|
||||
logicPortUIName[65] = "Out1";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "59 0 0";
|
||||
logicPortDir[66] = 4;
|
||||
logicPortUIName[66] = "Out2";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "57 0 0";
|
||||
logicPortDir[67] = 4;
|
||||
logicPortUIName[67] = "Out3";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "55 0 0";
|
||||
logicPortDir[68] = 4;
|
||||
logicPortUIName[68] = "Out4";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "53 0 0";
|
||||
logicPortDir[69] = 4;
|
||||
logicPortUIName[69] = "Out5";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "51 0 0";
|
||||
logicPortDir[70] = 4;
|
||||
logicPortUIName[70] = "Out6";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "49 0 0";
|
||||
logicPortDir[71] = 4;
|
||||
logicPortUIName[71] = "Out7";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "47 0 0";
|
||||
logicPortDir[72] = 4;
|
||||
logicPortUIName[72] = "Out8";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "45 0 0";
|
||||
logicPortDir[73] = 4;
|
||||
logicPortUIName[73] = "Out9";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "43 0 0";
|
||||
logicPortDir[74] = 4;
|
||||
logicPortUIName[74] = "Out10";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "41 0 0";
|
||||
logicPortDir[75] = 4;
|
||||
logicPortUIName[75] = "Out11";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "39 0 0";
|
||||
logicPortDir[76] = 4;
|
||||
logicPortUIName[76] = "Out12";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "37 0 0";
|
||||
logicPortDir[77] = 4;
|
||||
logicPortUIName[77] = "Out13";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "35 0 0";
|
||||
logicPortDir[78] = 4;
|
||||
logicPortUIName[78] = "Out14";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "33 0 0";
|
||||
logicPortDir[79] = 4;
|
||||
logicPortUIName[79] = "Out15";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "31 0 0";
|
||||
logicPortDir[80] = 4;
|
||||
logicPortUIName[80] = "Out16";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "29 0 0";
|
||||
logicPortDir[81] = 4;
|
||||
logicPortUIName[81] = "Out17";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "27 0 0";
|
||||
logicPortDir[82] = 4;
|
||||
logicPortUIName[82] = "Out18";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "25 0 0";
|
||||
logicPortDir[83] = 4;
|
||||
logicPortUIName[83] = "Out19";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "23 0 0";
|
||||
logicPortDir[84] = 4;
|
||||
logicPortUIName[84] = "Out20";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "21 0 0";
|
||||
logicPortDir[85] = 4;
|
||||
logicPortUIName[85] = "Out21";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "19 0 0";
|
||||
logicPortDir[86] = 4;
|
||||
logicPortUIName[86] = "Out22";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "17 0 0";
|
||||
logicPortDir[87] = 4;
|
||||
logicPortUIName[87] = "Out23";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "15 0 0";
|
||||
logicPortDir[88] = 4;
|
||||
logicPortUIName[88] = "Out24";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "13 0 0";
|
||||
logicPortDir[89] = 4;
|
||||
logicPortUIName[89] = "Out25";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "11 0 0";
|
||||
logicPortDir[90] = 4;
|
||||
logicPortUIName[90] = "Out26";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "9 0 0";
|
||||
logicPortDir[91] = 4;
|
||||
logicPortUIName[91] = "Out27";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "7 0 0";
|
||||
logicPortDir[92] = 4;
|
||||
logicPortUIName[92] = "Out28";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "5 0 0";
|
||||
logicPortDir[93] = 4;
|
||||
logicPortUIName[93] = "Out29";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "3 0 0";
|
||||
logicPortDir[94] = 4;
|
||||
logicPortUIName[94] = "Out30";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "1 0 0";
|
||||
logicPortDir[95] = 4;
|
||||
logicPortUIName[95] = "Out31";
|
||||
|
||||
logicPortType[96] = 0;
|
||||
logicPortPos[96] = "-1 0 0";
|
||||
logicPortDir[96] = 4;
|
||||
logicPortUIName[96] = "Out32";
|
||||
|
||||
logicPortType[97] = 0;
|
||||
logicPortPos[97] = "-3 0 0";
|
||||
logicPortDir[97] = 4;
|
||||
logicPortUIName[97] = "Out33";
|
||||
|
||||
logicPortType[98] = 0;
|
||||
logicPortPos[98] = "-5 0 0";
|
||||
logicPortDir[98] = 4;
|
||||
logicPortUIName[98] = "Out34";
|
||||
|
||||
logicPortType[99] = 0;
|
||||
logicPortPos[99] = "-7 0 0";
|
||||
logicPortDir[99] = 4;
|
||||
logicPortUIName[99] = "Out35";
|
||||
|
||||
logicPortType[100] = 0;
|
||||
logicPortPos[100] = "-9 0 0";
|
||||
logicPortDir[100] = 4;
|
||||
logicPortUIName[100] = "Out36";
|
||||
|
||||
logicPortType[101] = 0;
|
||||
logicPortPos[101] = "-11 0 0";
|
||||
logicPortDir[101] = 4;
|
||||
logicPortUIName[101] = "Out37";
|
||||
|
||||
logicPortType[102] = 0;
|
||||
logicPortPos[102] = "-13 0 0";
|
||||
logicPortDir[102] = 4;
|
||||
logicPortUIName[102] = "Out38";
|
||||
|
||||
logicPortType[103] = 0;
|
||||
logicPortPos[103] = "-15 0 0";
|
||||
logicPortDir[103] = 4;
|
||||
logicPortUIName[103] = "Out39";
|
||||
|
||||
logicPortType[104] = 0;
|
||||
logicPortPos[104] = "-17 0 0";
|
||||
logicPortDir[104] = 4;
|
||||
logicPortUIName[104] = "Out40";
|
||||
|
||||
logicPortType[105] = 0;
|
||||
logicPortPos[105] = "-19 0 0";
|
||||
logicPortDir[105] = 4;
|
||||
logicPortUIName[105] = "Out41";
|
||||
|
||||
logicPortType[106] = 0;
|
||||
logicPortPos[106] = "-21 0 0";
|
||||
logicPortDir[106] = 4;
|
||||
logicPortUIName[106] = "Out42";
|
||||
|
||||
logicPortType[107] = 0;
|
||||
logicPortPos[107] = "-23 0 0";
|
||||
logicPortDir[107] = 4;
|
||||
logicPortUIName[107] = "Out43";
|
||||
|
||||
logicPortType[108] = 0;
|
||||
logicPortPos[108] = "-25 0 0";
|
||||
logicPortDir[108] = 4;
|
||||
logicPortUIName[108] = "Out44";
|
||||
|
||||
logicPortType[109] = 0;
|
||||
logicPortPos[109] = "-27 0 0";
|
||||
logicPortDir[109] = 4;
|
||||
logicPortUIName[109] = "Out45";
|
||||
|
||||
logicPortType[110] = 0;
|
||||
logicPortPos[110] = "-29 0 0";
|
||||
logicPortDir[110] = 4;
|
||||
logicPortUIName[110] = "Out46";
|
||||
|
||||
logicPortType[111] = 0;
|
||||
logicPortPos[111] = "-31 0 0";
|
||||
logicPortDir[111] = 4;
|
||||
logicPortUIName[111] = "Out47";
|
||||
|
||||
logicPortType[112] = 0;
|
||||
logicPortPos[112] = "-33 0 0";
|
||||
logicPortDir[112] = 4;
|
||||
logicPortUIName[112] = "Out48";
|
||||
|
||||
logicPortType[113] = 0;
|
||||
logicPortPos[113] = "-35 0 0";
|
||||
logicPortDir[113] = 4;
|
||||
logicPortUIName[113] = "Out49";
|
||||
|
||||
logicPortType[114] = 0;
|
||||
logicPortPos[114] = "-37 0 0";
|
||||
logicPortDir[114] = 4;
|
||||
logicPortUIName[114] = "Out50";
|
||||
|
||||
logicPortType[115] = 0;
|
||||
logicPortPos[115] = "-39 0 0";
|
||||
logicPortDir[115] = 4;
|
||||
logicPortUIName[115] = "Out51";
|
||||
|
||||
logicPortType[116] = 0;
|
||||
logicPortPos[116] = "-41 0 0";
|
||||
logicPortDir[116] = 4;
|
||||
logicPortUIName[116] = "Out52";
|
||||
|
||||
logicPortType[117] = 0;
|
||||
logicPortPos[117] = "-43 0 0";
|
||||
logicPortDir[117] = 4;
|
||||
logicPortUIName[117] = "Out53";
|
||||
|
||||
logicPortType[118] = 0;
|
||||
logicPortPos[118] = "-45 0 0";
|
||||
logicPortDir[118] = 4;
|
||||
logicPortUIName[118] = "Out54";
|
||||
|
||||
logicPortType[119] = 0;
|
||||
logicPortPos[119] = "-47 0 0";
|
||||
logicPortDir[119] = 4;
|
||||
logicPortUIName[119] = "Out55";
|
||||
|
||||
logicPortType[120] = 0;
|
||||
logicPortPos[120] = "-49 0 0";
|
||||
logicPortDir[120] = 4;
|
||||
logicPortUIName[120] = "Out56";
|
||||
|
||||
logicPortType[121] = 0;
|
||||
logicPortPos[121] = "-51 0 0";
|
||||
logicPortDir[121] = 4;
|
||||
logicPortUIName[121] = "Out57";
|
||||
|
||||
logicPortType[122] = 0;
|
||||
logicPortPos[122] = "-53 0 0";
|
||||
logicPortDir[122] = 4;
|
||||
logicPortUIName[122] = "Out58";
|
||||
|
||||
logicPortType[123] = 0;
|
||||
logicPortPos[123] = "-55 0 0";
|
||||
logicPortDir[123] = 4;
|
||||
logicPortUIName[123] = "Out59";
|
||||
|
||||
logicPortType[124] = 0;
|
||||
logicPortPos[124] = "-57 0 0";
|
||||
logicPortDir[124] = 4;
|
||||
logicPortUIName[124] = "Out60";
|
||||
|
||||
logicPortType[125] = 0;
|
||||
logicPortPos[125] = "-59 0 0";
|
||||
logicPortDir[125] = 4;
|
||||
logicPortUIName[125] = "Out61";
|
||||
|
||||
logicPortType[126] = 0;
|
||||
logicPortPos[126] = "-61 0 0";
|
||||
logicPortDir[126] = 4;
|
||||
logicPortUIName[126] = "Out62";
|
||||
|
||||
logicPortType[127] = 0;
|
||||
logicPortPos[127] = "-63 0 0";
|
||||
logicPortDir[127] = 4;
|
||||
logicPortUIName[127] = "Out63";
|
||||
|
||||
logicPortType[128] = 1;
|
||||
logicPortPos[128] = "63 0 0";
|
||||
logicPortDir[128] = 2;
|
||||
logicPortUIName[128] = "Clock";
|
||||
logicPortCauseUpdate[128] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer64_Data){
|
||||
datablock fxDtsBrickData(Buffer64Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit";
|
||||
|
||||
@@ -160,6 +160,8 @@ datablock fxDtsBrickData(LogicGate_Buffer64_Data){
|
||||
|
||||
numLogicPorts = 129;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
127
bricks/gen/newcode/Buffer 7 Bit Down.cs
Normal file
127
bricks/gen/newcode/Buffer 7 Bit Down.cs
Normal file
@@ -0,0 +1,127 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer7BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 7 Bit Down";
|
||||
logicUIName = "Buffer 7 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 15) then " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 7)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "4 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "2 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-2 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-4 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-6 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "6 0 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
||||
127
bricks/gen/newcode/Buffer 7 Bit Up.cs
Normal file
127
bricks/gen/newcode/Buffer 7 Bit Up.cs
Normal file
@@ -0,0 +1,127 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer7BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 7 Bit Up";
|
||||
logicUIName = "Buffer 7 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 15) then " @
|
||||
" Gate.setportstate(gate, 8, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 7)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 8, false) " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "4 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "2 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-2 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-4 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-6 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "6 0 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer7_Data){
|
||||
datablock fxDtsBrickData(Buffer7Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit";
|
||||
|
||||
@@ -46,6 +46,8 @@ datablock fxDtsBrickData(LogicGate_Buffer7_Data){
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
139
bricks/gen/newcode/Buffer 8 Bit Down.cs
Normal file
139
bricks/gen/newcode/Buffer 8 Bit Down.cs
Normal file
@@ -0,0 +1,139 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer8BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 8 Bit Down";
|
||||
logicUIName = "Buffer 8 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 17) then " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 8)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "Out0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "Out1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "Out2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "7 0 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
||||
139
bricks/gen/newcode/Buffer 8 Bit Up.cs
Normal file
139
bricks/gen/newcode/Buffer 8 Bit Up.cs
Normal file
@@ -0,0 +1,139 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer8BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 8 Bit Up";
|
||||
logicUIName = "Buffer 8 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 17) then " @
|
||||
" Gate.setportstate(gate, 9, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 8)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 9, false) " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "Out0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "Out1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "7 0 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer8_Data){
|
||||
datablock fxDtsBrickData(Buffer8Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit";
|
||||
|
||||
@@ -48,6 +48,8 @@ datablock fxDtsBrickData(LogicGate_Buffer8_Data){
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
151
bricks/gen/newcode/Buffer 9 Bit Down.cs
Normal file
151
bricks/gen/newcode/Buffer 9 Bit Down.cs
Normal file
@@ -0,0 +1,151 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer9BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 9 Bit Down";
|
||||
logicUIName = "Buffer 9 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "9 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 19) then " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 9)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "6 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "4 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-4 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-6 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-8 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "8 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "Out0";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "6 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "Out1";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "4 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out2";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "2 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out3";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out4";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-2 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out5";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-4 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out6";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-6 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out7";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-8 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out8";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
151
bricks/gen/newcode/Buffer 9 Bit Up.cs
Normal file
151
bricks/gen/newcode/Buffer 9 Bit Up.cs
Normal file
@@ -0,0 +1,151 @@
|
||||
|
||||
datablock fxDtsBrickData(Buffer9BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 9 Bit Up";
|
||||
logicUIName = "Buffer 9 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "9 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 19) then " @
|
||||
" Gate.setportstate(gate, 10, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 9)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 10, false) " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "6 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "4 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-4 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-6 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-8 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "8 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "Out0";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "6 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out1";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "4 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out2";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "2 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out3";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out4";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-2 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out5";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-4 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out6";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-6 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out7";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-8 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out8";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer9_Data){
|
||||
datablock fxDtsBrickData(Buffer9Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit";
|
||||
|
||||
@@ -50,6 +50,8 @@ datablock fxDtsBrickData(LogicGate_Buffer9_Data){
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
55
bricks/gen/newcode/Buffer Active Low 1 Bit Down.cs
Normal file
55
bricks/gen/newcode/Buffer Active Low 1 Bit Down.cs
Normal file
@@ -0,0 +1,55 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl1BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 1 Bit Down";
|
||||
logicUIName = "Buffer Active Low 1 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 3) then " @
|
||||
" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 2, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
55
bricks/gen/newcode/Buffer Active Low 1 Bit Up.cs
Normal file
55
bricks/gen/newcode/Buffer Active Low 1 Bit Up.cs
Normal file
@@ -0,0 +1,55 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl1BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 1 Bit Up";
|
||||
logicUIName = "Buffer Active Low 1 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 3) then " @
|
||||
" Gate.setportstate(gate, 2, Gate.getportstate(gate, 1)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 2, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl1_Data){
|
||||
datablock fxDtsBrickData(BufferAl1Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit";
|
||||
|
||||
@@ -34,6 +34,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl1_Data){
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
163
bricks/gen/newcode/Buffer Active Low 10 Bit Down.cs
Normal file
163
bricks/gen/newcode/Buffer Active Low 10 Bit Down.cs
Normal file
@@ -0,0 +1,163 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl10BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 10 Bit Down";
|
||||
logicUIName = "Buffer Active Low 10 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 21) then " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
163
bricks/gen/newcode/Buffer Active Low 10 Bit Up.cs
Normal file
163
bricks/gen/newcode/Buffer Active Low 10 Bit Up.cs
Normal file
@@ -0,0 +1,163 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl10BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 10 Bit Up";
|
||||
logicUIName = "Buffer Active Low 10 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 21) then " @
|
||||
" Gate.setportstate(gate, 11, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 10)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 11, false) " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl10_Data){
|
||||
datablock fxDtsBrickData(BufferAl10Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit";
|
||||
|
||||
@@ -52,6 +52,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl10_Data){
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
175
bricks/gen/newcode/Buffer Active Low 11 Bit Down.cs
Normal file
175
bricks/gen/newcode/Buffer Active Low 11 Bit Down.cs
Normal file
@@ -0,0 +1,175 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl11BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 11 Bit Down";
|
||||
logicUIName = "Buffer Active Low 11 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
175
bricks/gen/newcode/Buffer Active Low 11 Bit Up.cs
Normal file
175
bricks/gen/newcode/Buffer Active Low 11 Bit Up.cs
Normal file
@@ -0,0 +1,175 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl11BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 11 Bit Up";
|
||||
logicUIName = "Buffer Active Low 11 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 23) then " @
|
||||
" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 12, false) " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl11_Data){
|
||||
datablock fxDtsBrickData(BufferAl11Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit";
|
||||
|
||||
@@ -54,6 +54,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl11_Data){
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
187
bricks/gen/newcode/Buffer Active Low 12 Bit Down.cs
Normal file
187
bricks/gen/newcode/Buffer Active Low 12 Bit Down.cs
Normal file
@@ -0,0 +1,187 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl12BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 12 Bit Down";
|
||||
logicUIName = "Buffer Active Low 12 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
187
bricks/gen/newcode/Buffer Active Low 12 Bit Up.cs
Normal file
187
bricks/gen/newcode/Buffer Active Low 12 Bit Up.cs
Normal file
@@ -0,0 +1,187 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl12BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 12 Bit Up";
|
||||
logicUIName = "Buffer Active Low 12 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 25) then " @
|
||||
" Gate.setportstate(gate, 13, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 12)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 13, false) " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl12_Data){
|
||||
datablock fxDtsBrickData(BufferAl12Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit";
|
||||
|
||||
@@ -56,6 +56,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl12_Data){
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
199
bricks/gen/newcode/Buffer Active Low 13 Bit Down.cs
Normal file
199
bricks/gen/newcode/Buffer Active Low 13 Bit Down.cs
Normal file
@@ -0,0 +1,199 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl13BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 13 Bit Down";
|
||||
logicUIName = "Buffer Active Low 13 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
199
bricks/gen/newcode/Buffer Active Low 13 Bit Up.cs
Normal file
199
bricks/gen/newcode/Buffer Active Low 13 Bit Up.cs
Normal file
@@ -0,0 +1,199 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl13BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 13 Bit Up";
|
||||
logicUIName = "Buffer Active Low 13 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 27) then " @
|
||||
" Gate.setportstate(gate, 14, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 13)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 14, false) " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl13_Data){
|
||||
datablock fxDtsBrickData(BufferAl13Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit";
|
||||
|
||||
@@ -58,6 +58,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl13_Data){
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
211
bricks/gen/newcode/Buffer Active Low 14 Bit Down.cs
Normal file
211
bricks/gen/newcode/Buffer Active Low 14 Bit Down.cs
Normal file
@@ -0,0 +1,211 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl14BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 14 Bit Down";
|
||||
logicUIName = "Buffer Active Low 14 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
211
bricks/gen/newcode/Buffer Active Low 14 Bit Up.cs
Normal file
211
bricks/gen/newcode/Buffer Active Low 14 Bit Up.cs
Normal file
@@ -0,0 +1,211 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl14BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 14 Bit Up";
|
||||
logicUIName = "Buffer Active Low 14 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 29) then " @
|
||||
" Gate.setportstate(gate, 15, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 14)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 15, false) " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl14_Data){
|
||||
datablock fxDtsBrickData(BufferAl14Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit";
|
||||
|
||||
@@ -60,6 +60,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl14_Data){
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
223
bricks/gen/newcode/Buffer Active Low 15 Bit Down.cs
Normal file
223
bricks/gen/newcode/Buffer Active Low 15 Bit Down.cs
Normal file
@@ -0,0 +1,223 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl15BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 15 Bit Down";
|
||||
logicUIName = "Buffer Active Low 15 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
223
bricks/gen/newcode/Buffer Active Low 15 Bit Up.cs
Normal file
223
bricks/gen/newcode/Buffer Active Low 15 Bit Up.cs
Normal file
@@ -0,0 +1,223 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl15BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 15 Bit Up";
|
||||
logicUIName = "Buffer Active Low 15 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 31) then " @
|
||||
" Gate.setportstate(gate, 16, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 15)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 16, false) " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl15_Data){
|
||||
datablock fxDtsBrickData(BufferAl15Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit";
|
||||
|
||||
@@ -62,6 +62,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl15_Data){
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
235
bricks/gen/newcode/Buffer Active Low 16 Bit Down.cs
Normal file
235
bricks/gen/newcode/Buffer Active Low 16 Bit Down.cs
Normal file
@@ -0,0 +1,235 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl16BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 16 Bit Down";
|
||||
logicUIName = "Buffer Active Low 16 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
235
bricks/gen/newcode/Buffer Active Low 16 Bit Up.cs
Normal file
235
bricks/gen/newcode/Buffer Active Low 16 Bit Up.cs
Normal file
@@ -0,0 +1,235 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl16BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 16 Bit Up";
|
||||
logicUIName = "Buffer Active Low 16 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 33) then " @
|
||||
" Gate.setportstate(gate, 17, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 18, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 19, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 20, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 21, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 22, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 23, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 24, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 16)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 17, false) " @
|
||||
" Gate.setportstate(gate, 18, false) " @
|
||||
" Gate.setportstate(gate, 19, false) " @
|
||||
" Gate.setportstate(gate, 20, false) " @
|
||||
" Gate.setportstate(gate, 21, false) " @
|
||||
" Gate.setportstate(gate, 22, false) " @
|
||||
" Gate.setportstate(gate, 23, false) " @
|
||||
" Gate.setportstate(gate, 24, false) " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl16_Data){
|
||||
datablock fxDtsBrickData(BufferAl16Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit";
|
||||
|
||||
@@ -64,6 +64,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl16_Data){
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
67
bricks/gen/newcode/Buffer Active Low 2 Bit Down.cs
Normal file
67
bricks/gen/newcode/Buffer Active Low 2 Bit Down.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl2BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 2 Bit Down";
|
||||
logicUIName = "Buffer Active Low 2 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
67
bricks/gen/newcode/Buffer Active Low 2 Bit Up.cs
Normal file
67
bricks/gen/newcode/Buffer Active Low 2 Bit Up.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl2BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 2 Bit Up";
|
||||
logicUIName = "Buffer Active Low 2 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 5) then " @
|
||||
" Gate.setportstate(gate, 3, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 2)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 3, false) " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl2_Data){
|
||||
datablock fxDtsBrickData(BufferAl2Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit";
|
||||
|
||||
@@ -36,6 +36,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl2_Data){
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
331
bricks/gen/newcode/Buffer Active Low 24 Bit Down.cs
Normal file
331
bricks/gen/newcode/Buffer Active Low 24 Bit Down.cs
Normal file
@@ -0,0 +1,331 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl24BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 24 Bit Down";
|
||||
logicUIName = "Buffer Active Low 24 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 4;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 4;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 4;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 4;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 4;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 4;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 4;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 4;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 4;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 4;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 4;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 4;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 4;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 4;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 4;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 4;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 4;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 4;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 5;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 5;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 5;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 5;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 5;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 5;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 5;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 5;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 5;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 5;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 5;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 5;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 5;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 5;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 5;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 5;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 5;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 5;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 5;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 5;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 5;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 5;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 5;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 5;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
331
bricks/gen/newcode/Buffer Active Low 24 Bit Up.cs
Normal file
331
bricks/gen/newcode/Buffer Active Low 24 Bit Up.cs
Normal file
@@ -0,0 +1,331 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl24BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 24 Bit Up";
|
||||
logicUIName = "Buffer Active Low 24 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 49) then " @
|
||||
" Gate.setportstate(gate, 25, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 26, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 27, Gate.getportstate(gate, 3)) " @
|
||||
" Gate.setportstate(gate, 28, Gate.getportstate(gate, 4)) " @
|
||||
" Gate.setportstate(gate, 29, Gate.getportstate(gate, 5)) " @
|
||||
" Gate.setportstate(gate, 30, Gate.getportstate(gate, 6)) " @
|
||||
" Gate.setportstate(gate, 31, Gate.getportstate(gate, 7)) " @
|
||||
" Gate.setportstate(gate, 32, Gate.getportstate(gate, 8)) " @
|
||||
" Gate.setportstate(gate, 33, Gate.getportstate(gate, 9)) " @
|
||||
" Gate.setportstate(gate, 34, Gate.getportstate(gate, 10)) " @
|
||||
" Gate.setportstate(gate, 35, Gate.getportstate(gate, 11)) " @
|
||||
" Gate.setportstate(gate, 36, Gate.getportstate(gate, 12)) " @
|
||||
" Gate.setportstate(gate, 37, Gate.getportstate(gate, 13)) " @
|
||||
" Gate.setportstate(gate, 38, Gate.getportstate(gate, 14)) " @
|
||||
" Gate.setportstate(gate, 39, Gate.getportstate(gate, 15)) " @
|
||||
" Gate.setportstate(gate, 40, Gate.getportstate(gate, 16)) " @
|
||||
" Gate.setportstate(gate, 41, Gate.getportstate(gate, 17)) " @
|
||||
" Gate.setportstate(gate, 42, Gate.getportstate(gate, 18)) " @
|
||||
" Gate.setportstate(gate, 43, Gate.getportstate(gate, 19)) " @
|
||||
" Gate.setportstate(gate, 44, Gate.getportstate(gate, 20)) " @
|
||||
" Gate.setportstate(gate, 45, Gate.getportstate(gate, 21)) " @
|
||||
" Gate.setportstate(gate, 46, Gate.getportstate(gate, 22)) " @
|
||||
" Gate.setportstate(gate, 47, Gate.getportstate(gate, 23)) " @
|
||||
" Gate.setportstate(gate, 48, Gate.getportstate(gate, 24)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 25, false) " @
|
||||
" Gate.setportstate(gate, 26, false) " @
|
||||
" Gate.setportstate(gate, 27, false) " @
|
||||
" Gate.setportstate(gate, 28, false) " @
|
||||
" Gate.setportstate(gate, 29, false) " @
|
||||
" Gate.setportstate(gate, 30, false) " @
|
||||
" Gate.setportstate(gate, 31, false) " @
|
||||
" Gate.setportstate(gate, 32, false) " @
|
||||
" Gate.setportstate(gate, 33, false) " @
|
||||
" Gate.setportstate(gate, 34, false) " @
|
||||
" Gate.setportstate(gate, 35, false) " @
|
||||
" Gate.setportstate(gate, 36, false) " @
|
||||
" Gate.setportstate(gate, 37, false) " @
|
||||
" Gate.setportstate(gate, 38, false) " @
|
||||
" Gate.setportstate(gate, 39, false) " @
|
||||
" Gate.setportstate(gate, 40, false) " @
|
||||
" Gate.setportstate(gate, 41, false) " @
|
||||
" Gate.setportstate(gate, 42, false) " @
|
||||
" Gate.setportstate(gate, 43, false) " @
|
||||
" Gate.setportstate(gate, 44, false) " @
|
||||
" Gate.setportstate(gate, 45, false) " @
|
||||
" Gate.setportstate(gate, 46, false) " @
|
||||
" Gate.setportstate(gate, 47, false) " @
|
||||
" Gate.setportstate(gate, 48, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 5;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 5;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 5;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 5;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 5;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 5;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 5;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 5;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 5;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 5;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 5;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 5;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 5;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 5;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 5;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 5;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 5;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 5;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 4;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 4;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 4;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 4;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 4;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 4;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 4;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 4;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 4;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 4;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 4;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 4;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 4;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 4;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 4;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 4;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 4;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 4;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 4;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 4;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 4;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 4;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 4;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 4;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl24_Data){
|
||||
datablock fxDtsBrickData(BufferAl24Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit";
|
||||
|
||||
@@ -80,6 +80,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl24_Data){
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
79
bricks/gen/newcode/Buffer Active Low 3 Bit Down.cs
Normal file
79
bricks/gen/newcode/Buffer Active Low 3 Bit Down.cs
Normal file
@@ -0,0 +1,79 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl3BitDown){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit Down.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit Down";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 3 Bit Down";
|
||||
logicUIName = "Buffer Active Low 3 Bit Down";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 4;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 4;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 4;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 5;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 5;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 5;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
79
bricks/gen/newcode/Buffer Active Low 3 Bit Up.cs
Normal file
79
bricks/gen/newcode/Buffer Active Low 3 Bit Up.cs
Normal file
@@ -0,0 +1,79 @@
|
||||
|
||||
datablock fxDtsBrickData(BufferAl3BitUp){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit Up.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit Up";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 3 Bit Up";
|
||||
logicUIName = "Buffer Active Low 3 Bit Up";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not Gate.getportstate(gate, 7) then " @
|
||||
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1)) " @
|
||||
" Gate.setportstate(gate, 5, Gate.getportstate(gate, 2)) " @
|
||||
" Gate.setportstate(gate, 6, Gate.getportstate(gate, 3)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 4, false) " @
|
||||
" Gate.setportstate(gate, 5, false) " @
|
||||
" Gate.setportstate(gate, 6, false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 5;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 5;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 5;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 4;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 4;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 4;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl3_Data){
|
||||
datablock fxDtsBrickData(BufferAl3Bit){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit";
|
||||
|
||||
@@ -38,6 +38,8 @@ datablock fxDtsBrickData(LogicGate_BufferAl3_Data){
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user