datablock fxDtsBrickData(LogicGate_Rom8x8_Data){
	brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 8x8.blb";
	iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 8x8";
	
	category = "Logic Bricks";
	subCategory = "Special I/O";
	uiName = "ROM 8x8";
	logicUIName = "ROM 8x8";
	logicUIDesc = "";
	
	hasPrint = 1;
	printAspectRatio = "Logic";
	
	logicBrickSize = "8 8 1";
	orientationFix = 3;
	
	isLogic = true;
	isLogicGate = true;
	isLogicInput = false;
	
	logicInit = 
		"return function(gate) " @
		"	gate.romdata = {} " @
		"	for i = 0, 63 do " @
		"		gate.romdata[i] = false " @
		"	end " @
		"end"
	;
	logicInput = 
		"return function(gate, args) " @
		"	local data = args[1] " @
		"	for i = 1, #data do " @
		"		local c = data:sub(i, i) " @
		"		gate.romdata[i-1] = (c==\"1\") " @
		"	end " @
		"	Gate.queue(gate, 0) " @
		"end"
	;
	logicUpdate = 
		"return function(gate) " @
		"	if Gate.getportstate(gate, 8) then " @
		"		Gate.setportstate(gate, 7, gate.romdata[( " @
		"			(Gate.getportstate(gate, 1) and 1 or 0) " @
		"			+ (Gate.getportstate(gate, 2) and 2 or 0) " @
		"			+ (Gate.getportstate(gate, 3) and 4 or 0) " @
		"			+ (Gate.getportstate(gate, 4) and 8 or 0) " @
		"			+ (Gate.getportstate(gate, 5) and 16 or 0) " @
		"			+ (Gate.getportstate(gate, 6) and 32 or 0) " @
		"		)]) " @
		"	else " @
		"		Gate.setportstate(gate, 7, false) " @
		"	end " @
		"end"
	;
	logicGlobal = "";
	
	numLogicPorts = 8;
	
	isLogicRom = true;
	logicRomY = 8;
	logicRomX = 8;
	
	logicPortType[0] = 1;
	logicPortPos[0] = "7 -7 0";
	logicPortDir[0] = 3;
	logicPortUIName[0] = "Addr0";
	logicPortCauseUpdate[0] = true;
	
	logicPortType[1] = 1;
	logicPortPos[1] = "5 -7 0";
	logicPortDir[1] = 3;
	logicPortUIName[1] = "Addr1";
	logicPortCauseUpdate[1] = true;
	
	logicPortType[2] = 1;
	logicPortPos[2] = "3 -7 0";
	logicPortDir[2] = 3;
	logicPortUIName[2] = "Addr2";
	logicPortCauseUpdate[2] = true;
	
	logicPortType[3] = 1;
	logicPortPos[3] = "1 -7 0";
	logicPortDir[3] = 3;
	logicPortUIName[3] = "Addr3";
	logicPortCauseUpdate[3] = true;
	
	logicPortType[4] = 1;
	logicPortPos[4] = "-1 -7 0";
	logicPortDir[4] = 3;
	logicPortUIName[4] = "Addr4";
	logicPortCauseUpdate[4] = true;
	
	logicPortType[5] = 1;
	logicPortPos[5] = "-3 -7 0";
	logicPortDir[5] = 3;
	logicPortUIName[5] = "Addr5";
	logicPortCauseUpdate[5] = true;
	
	logicPortType[6] = 0;
	logicPortPos[6] = "7 7 0";
	logicPortDir[6] = 1;
	logicPortUIName[6] = "Out";
	
	logicPortType[7] = 1;
	logicPortPos[7] = "7 -7 0";
	logicPortDir[7] = 2;
	logicPortUIName[7] = "In";
	logicPortCauseUpdate[7] = true;
	
};

function LogicGate_Rom8x8_Data::Logic_onAdd(%data, %brick) {
	lualogic_rom_updatedata(%brick);
}