119 lines
2.8 KiB
C#
119 lines
2.8 KiB
C#
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datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16";
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category = "Logic Bricks";
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subCategory = "Special I/O";
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uiName = "ROM 16x16";
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logicUIName = "ROM 16x16";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "16 16 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit =
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"return function(gate) " @
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" gate.romdata = {} " @
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" for i = 0, 255 do " @
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" gate.romdata[i] = false " @
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" end " @
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"end"
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;
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logicInput =
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"return function(gate, args) " @
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" local data = args[1] " @
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" for i = 1, #data do " @
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" local c = data:sub(i, i) " @
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" gate.romdata[i-1] = (c==\"1\") " @
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" end " @
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" Gate.queue(gate, 0) " @
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"end"
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;
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logicUpdate =
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"return function(gate) " @
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" local addr = (Gate.getportstate(gate, 1) and 1 or 0) " @
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" + (Gate.getportstate(gate, 2) and 2 or 0) " @
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" + (Gate.getportstate(gate, 3) and 4 or 0) " @
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" + (Gate.getportstate(gate, 4) and 8 or 0) " @
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" + (Gate.getportstate(gate, 5) and 16 or 0) " @
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" + (Gate.getportstate(gate, 6) and 32 or 0) " @
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" + (Gate.getportstate(gate, 7) and 64 or 0) " @
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" + (Gate.getportstate(gate, 8) and 128 or 0) " @
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" Gate.setportstate(gate, 9, gate.romdata[addr]) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 9;
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isLogicRom = true;
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logicRomY = 16;
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logicRomX = 16;
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logicPortType[0] = 1;
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logicPortPos[0] = "15 -15 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "Addr0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "13 -15 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "Addr1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "11 -15 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "Addr2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "9 -15 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "Addr3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "7 -15 0";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "Addr4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 1;
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logicPortPos[5] = "5 -15 0";
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logicPortDir[5] = 3;
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logicPortUIName[5] = "Addr5";
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logicPortCauseUpdate[5] = true;
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logicPortType[6] = 1;
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logicPortPos[6] = "3 -15 0";
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logicPortDir[6] = 3;
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logicPortUIName[6] = "Addr6";
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logicPortCauseUpdate[6] = true;
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logicPortType[7] = 1;
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logicPortPos[7] = "1 -15 0";
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logicPortDir[7] = 3;
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logicPortUIName[7] = "Addr7";
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logicPortCauseUpdate[7] = true;
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logicPortType[8] = 0;
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logicPortPos[8] = "15 15 0";
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logicPortDir[8] = 1;
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logicPortUIName[8] = "Out";
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};
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function LogicGate_Rom16x16_Data::Logic_onAdd(%data, %brick) {
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lualogic_rom_updatedata(%brick);
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}
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