fix errors
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parent
cdbf3ed089
commit
0ac3f3e495
@ -2,33 +2,15 @@
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local ffi = FFI or require("ffi")
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Simulation = Simulation or {}
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ffi.cdef[[
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struct Net {
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int in_queue;
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int num_out_ports_on;
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int state;
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int update_tick;
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struct Gate* gates_update[0];
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};
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struct OutPort {
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struct Net* net;
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int state;
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};
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struct Gate {
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int in_queue;
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struct OutPort out_ports[0];
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};
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]]
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function Simulation.compile_code(sim, text)
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-- todo: compile some kind of DSL into machine code
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return code, size
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end
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local net_program_code = Simulation.compile_code( [[
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]] )
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--local net_program_code = Simulation.compile_code( [[
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--
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--]] )
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function Simulation.compile(sim)
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sim.compilation = {
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@ -15,7 +15,7 @@ function GateDefinition.new(objref, name, description, init, logic, input, code,
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description = collapseescape(description)
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code = collapseescape(code)
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local compiled_size, compiled_code = Simulation.compile_code(nil, code)
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--local compiled_size, compiled_code = Simulation.compile_code(nil, code)
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local def = {
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objref = objref,
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@ -66,7 +66,7 @@ function GateDefinition.new(objref, name, description, init, logic, input, code,
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def.num_out_ports = def.num_out_ports + 1
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elseif portd.type==PortTypes.input then
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def.num_in_ports = def.num_in_ports + 1
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else error("invalid port type: "..name.." port "..i..) end
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else error("invalid port type: "..name.." port "..i) end
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end
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return def
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@ -1,6 +1,16 @@
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local ffi = FFI
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ffi.cdef[[
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struct Net {
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int in_queue;
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int num_out_ports_on;
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int state;
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int update_tick;
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struct Gate* gates_update[0];
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};
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]]
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Group = {}
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function Group.new()
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@ -76,11 +76,11 @@ function network_update()
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local logic = data[i+5]
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local input = data[i+6]
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local global = data[i+7]
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local code = data[i+8]
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local numports = tonumber(data[i+9])
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--local code = data[i+8]
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local numports = tonumber(data[i+8])
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local ports = {}
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for a = i+10, numports*5+i+9, 5 do
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for a = i+9, numports*5+i+8, 5 do
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local portd = {
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type = tonumber(data[a]),
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position = vectotable(data[a+1]),
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@ -93,10 +93,10 @@ function network_update()
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if not portd.direction then print(line) end
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end
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local definition = GateDefinition.new(objref, name, desc, init, logic, input, global, ports, code)
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local definition = GateDefinition.new(objref, name, desc, init, logic, input, global, ports)
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Simulation.addgatedefinition(sim, definition)
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i = i + 9 + numports*5
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i = i + 8 + numports*5
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elseif data[i] == "SL" then
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local wire = Simulation.getwirebyref(sim, tonumber(data[i+1]))
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if wire ~= nil then
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