start adding c structs for gates and ports

This commit is contained in:
Redo0 2021-05-25 14:54:26 -05:00
parent be2df1ef33
commit 8561940777
7 changed files with 86 additions and 43 deletions

View File

@ -1,6 +1,14 @@
Gate = {}
FFI.cdef[[
struct Gate {
int objref;
int definition_objref;
struct Port ports[1];
};
]]
function Gate.new(self, objref, definition, sim)
local o = {
objref = objref,
@ -57,3 +65,21 @@ end
function Gate.getsim(gate)
return gate.sim
end
function Gate.getdefinition(gate)
return gate.definition
end
-- Logic functions
function Gate.init(gate)
Gate.getdefinition(gate).init(gate)
end
function Gate.logic(gate)
Gate.getdefinition(gate).logic(gate)
end
function Gate.input(gate, argv)
Gate.getdefinition(gate).input(gate, argv)
end

View File

@ -58,11 +58,11 @@ function GateDefinition.new(self, objref, name, description, init, logic, input,
return o
end
function GateDefinition.constructgate(self, objref, position, rotation, sim)
local gate = Gate.new(Gate, objref, self, sim)
function GateDefinition.constructgate(def, objref, position, rotation, sim)
local gate = Gate.new(Gate, objref, def, sim)
for i = 1, #self.ports do
local portd = self.ports[i]
for i = 1, #def.ports do
local portd = def.ports[i]
local type = portd.type
local pos = {portd.position[1], portd.position[2], portd.position[3]}
local dir = portd.direction

View File

@ -59,7 +59,7 @@ function Group.removewire(self, wire)
end
for k, wire in pairs(self.wires) do
Simulation.connectwire(sim. wire)
Simulation.connectwire(sim, wire)
end
for k, port in pairs(self.out_ports) do

View File

@ -14,15 +14,15 @@ local ffi = require("ffi")
dofile("iosafe.lua")
FFI = ffi
dofile("utility.lua")
dofile("simulation.lua")
dofile("group.lua")
dofile("wire.lua")
dofile("gatedef.lua")
dofile("gate.lua")
dofile("port.lua")
dofile("gate.lua")
dofile("save.lua")
FFI = ffi
dofile("compile.lua")
FFI = nil
@ -49,6 +49,7 @@ local avgticks = {}
local totalticks = 0
local sim = Simulation.new(Simulation)
GSim = sim
local units = {
"uHz",
@ -164,8 +165,8 @@ while 1 do
Simulation.addgate(sim, gate)
--print(gate.objref)
gate.definition.init(gate)
gate.definition.logic(gate)
Gate.init(gate)
Gate.logic(gate)
i = i + 4
elseif data[i] == "RW" then
@ -254,31 +255,32 @@ while 1 do
local userid = data[i+1]
local objref = tonumber(data[i+2])
local obj = Simulation.getwirebyref(sim, objref) or Simulation.getgatebyref(sim, objref)
local info = ""
if obj ~= nil then
local info = ""
local wire = Simulation.getwirebyref(sim, objref)
if wire then
local numportsi = 0; for k, wire2 in pairs(Wire.getgroup(wire).in_ports ) do numportsi = numportsi+1 end
local numportso = 0; for k, wire2 in pairs(Wire.getgroup(wire).out_ports) do numportso = numportso+1 end
local numwires = 0; for k, wire2 in pairs(Wire.getgroup(wire).wires ) do numwires = numwires +1 end
if obj.logictype == 0 then
local numportsi = 0; for k, wire in pairs(Wire.getgroup(obj).in_ports ) do numportsi = numportsi+1 end
local numportso = 0; for k, wire in pairs(Wire.getgroup(obj).out_ports) do numportso = numportso+1 end
local numwires = 0; for k, wire in pairs(Wire.getgroup(obj).wires ) do numwires = numwires +1 end
info = "\\c5Net " .. tostring(wire.group):match("table: 0x(.+)"):upper() .. "\n" .. (Wire.getgroup(wire).state and "\\c2On" or "\\c0Off") .. "\n" ..
"Wires: "..numwires.."\n"..
"In Ports: " ..numportsi.."\n"..
"Out Ports: "..numportso
;
end
info = "\\c5Net " .. tostring(obj.group):match("table: 0x(.+)"):upper() .. "\n" .. (Wire.getgroup(obj).state and "\\c2On" or "\\c0Off") .. "\n" ..
"Wires: "..numwires.."\n"..
"In Ports: " ..numportsi.."\n"..
"Out Ports: "..numportso
;
else
info = "\\c5" .. obj.definition.name .. "<br>"
for i = 1, #obj.ports do
info = info .. (obj.ports[i].state and "\\c2" or "\\c0") .. obj.definition.ports[i].name .. (i ~= #obj.ports and " " or "")
end
local gate = Simulation.getgatebyref(sim, objref)
if gate then
local def = Gate.getdefinition(gate)
info = "\\c5" .. def.name .. "<br>"
for i = 1, #gate.ports do
info = info .. (gate.ports[i].state and "\\c2" or "\\c0") .. def.ports[i].name .. (i ~= #gate.ports and " " or "")
end
end
if info ~= "" then
client:send("GINFO\t" .. userid .. "\t" .. expandescape(info) .. "\n")
end
if info ~= "" then
client:send("GINFO\t" .. userid .. "\t" .. expandescape(info) .. "\n")
end
i = i + 2

View File

@ -1,7 +1,7 @@
PortTypes = {
output = 0,
input = 1
input = 1,
}
PortDirections = {
@ -13,9 +13,20 @@ PortDirections = {
[5] = {0, 0, -1}
}
Port = {
logictype = 1,
}
Port = {}
FFI.cdef[[
struct Gate;
struct Port {
bool state;
char type;
char direction;
bool causeupdate;
int position[3];
struct Gate* gate;
struct Net* group;
};
]]
function Port.new(self, type, direction, position, causeupdate, sim)
local o = {

View File

@ -169,13 +169,19 @@ function Simulation.removegate(self, objref)
self.ngates = self.ngates - 1
end
local function is_wire(obj)
return obj.layer~=nil
end
function Simulation.connectwireat(self, wire, x, y, z)
local objs = Simulation.getfromworld(self, x, y, z)
for k, obj in pairs(objs) do
if obj ~= wire and obj.group ~= nil then
if obj.logictype == 0 and Wire.getlayer(obj) == Wire.getlayer(wire) then
if is_wire(obj) then -- wire
if Wire.getlayer(obj) == Wire.getlayer(wire) then -- same layer
Group.addwire(obj.group, wire)
elseif obj.logictype == 1 then
end
else -- port
Group.addwire(obj.group, wire)
end
end
@ -273,13 +279,13 @@ function Simulation.tick(self)
self.groupqueue = {}
for k, gate in pairs(self.initqueue) do
gate.definition.init(gate)
Gate.init(gate)
end
self.initqueue = {}
for gate, inputs in pairs(self.inputqueue) do
for inputidx, argv in ipairs(inputs) do
gate.definition.input(gate, argv)
Gate.input(gate, argv)
end
end
self.inputqueue = {}
@ -292,7 +298,7 @@ function Simulation.tick(self)
end
for k, gate in pairs(self.gatequeue) do
gate.definition.logic(gate)
Gate.logic(gate)
end
self.gatequeue = {}

View File

@ -1,7 +1,5 @@
Wire = {
logictype = 0
}
Wire = {}
function Wire.new(self, objref, layer, bounds, sim)
local o = {