Group = {} function Group.new(self) local o = { state = false, fxstate = false, updatetick = 0, wires = {}, out_ports = {}, in_ports = {}, nwires = 0, nout_ports = 0, nin_ports = 0 } setmetatable(o, self) self.__index = self return o end function Group.getsize(self) return self.nwires + self.nout_ports + self.nin_ports end function Group.addwire(self, wire) if wire.group ~= self then if wire.group ~= nil then self:mergewith(wire.group) else self.wires[wire] = wire self.nwires = self.nwires + 1 wire.group = self wire:update() sim:queuegroup(self) end end end function Group.removewire(self, wire) wire.group = nil self.wires[wire] = nil for k, wire in pairs(self.wires) do wire.group = nil end for k, port in pairs(self.out_ports) do port.group = nil end for k, port in pairs(self.in_ports) do port.group = nil end for k, wire in pairs(self.wires) do sim:connectwire(wire) end for k, port in pairs(self.out_ports) do sim:connectport(port) end for k, port in pairs(self.in_ports) do sim:connectport(port) end self.wires = {} self.out_ports = {} self.in_ports = {} self.nwires = 0 self.nout_ports = 0 self.nin_ports = 0 end function Group.addport(self, port) port.group = self if port.type == PortTypes.output then self.out_ports[port] = port self.nout_ports = self.nout_ports + 1 sim:queuegroup(self) elseif port.type == PortTypes.input then self.in_ports[port] = port self.nin_ports = self.nin_ports + 1 port:setinputstate(self.state) end end function Group.removeport(self, port) if port.type == PortTypes.output then self.out_ports[port] = nil self.nout_ports = self.nout_ports - 1 elseif port.type == PortTypes.input then self.in_ports[port] = nil self.nin_ports = self.nin_ports - 1 end Simulation.queuegroup(sim, self) end function Group.mergewith(self, group) if self:getsize() >= group:getsize() then Group.mergeinto(group, self) return self else Group.mergeinto(self, group) return group end end function Group.mergeinto(self, group) for k, wire in pairs(self.wires) do wire.group = nil Group.addwire(group, wire) end for k, port in pairs(self.out_ports) do Group.addport(group, port) end for k, port in pairs(self.in_ports) do Group.addport(group, port) end self.wires = {} self.out_ports = {} self.in_ports = {} self.nwires = 0 self.nout_ports = 0 self.nin_ports = 0 end function Group.setstate(self, state) if state ~= self.state then self.state = state self.updatetick = sim.currenttick for k, port in pairs(self.in_ports) do Port.setinputstate(port, state) end Simulation.queuegroupfx(sim, self) end end