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update readme, add 16-bit arith and pointer increments

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This commit is contained in:
Redo
2022-11-01 13:39:26 -06:00
parent 7ec5152d72
commit c1fd3d1d30
4 changed files with 76 additions and 25 deletions
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8
assembler-8608.lua
View File

@ -36,8 +36,8 @@ local function mnemFromLine(line, instrs, validWords)
local function addNum(n)
n = trim(n)
local val, len = decodeNumber(n)
local linei8 = line:gsub(n, "imm8", 1, true)
local linei16 = line:gsub(n, "imm16", 1, true)
local linei8 = line:gsub(n, "imm8", 1, true):lower()
local linei16 = line:gsub(n, "imm16", 1, true):lower()
if len==1 and (not instrs[linei8]) and instrs[linei16] then len = 2 end
table.insert(imms, { val = val, len = len } )
return " imm"..(len*8).." "
@ -45,7 +45,7 @@ local function mnemFromLine(line, instrs, validWords)
local function addLabel(n)
n = trim(n)
local len = 2
local linei8 = line:gsub(n, "imm8", 1, true)
local linei8 = line:gsub(n, "imm8", 1, true):lower()
if instrs[linei8] then len = 1 end
table.insert(imms, { label = n, len = len } )
return " imm"..(len*8).." "
@ -59,7 +59,7 @@ local function mnemFromLine(line, instrs, validWords)
mnem = mnem:gsub(" %-?[0-9a-fA-F]+h " , function(n) if not validWords[trim(n)] then return addNum (n) end end)
mnem = mnem:gsub(" %-?[0-9]+ " , function(n) if not validWords[trim(n)] then return addNum (n) end end)
mnem = mnem:gsub(" [a-zA-Z_][a-zA-Z0-9_%.]* ", function(n) if not validWords[trim(n)] then return addLabel(n) end end)
mnem = trim(mnem):gsub(" +", " ")
mnem = trim(mnem):gsub(" +", " "):lower()
if not instrs[mnem] then mnem = mnem:gsub("%+ imm", "imm") end

35
instructionList.txt
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@ -30,6 +30,11 @@ dec *s+imm8 2C 4 *(S+imm8)--, set flags
icc *s+imm8 2D 4 *(S+imm8)+=CF, set flags
tst *s+imm8 2E 3 Set flags according to *(S+imm8)-0
16-bit Arithmetic (X):
adp imm8 4A 2 P+=imm8 signed
adq imm8 4B 2 Q+=imm8 signed
ads imm8 4C 2 S+=imm8 signed
8-bit Arithmetic/Logic (A):
add imm8 24 2 A+=imm8, set flags
adb imm8 72 2 B+=imm8, set flags
@ -90,10 +95,10 @@ jsr q 67 1 I=Q, Q=I
jpr imm8 31 2 I+=imm8
jnz imm8 30 2 I+=imm8 if !Zero
jpz imm8 32 2 I+=imm8 if Zero
jge imm8 33 2 I+=imm8 if !Carry
jlt imm8 34 2 I+=imm8 if Carry
jgt imm8 35 2 I+=imm8 if !Zero&!Carry
jle imm8 36 2 I+=imm8 if Zero|Carry
jlt imm8 33 2 I+=imm8 if !Carry
jge imm8 34 2 I+=imm8 if Carry
jgt imm8 35 2 I+=imm8 if !Zero & Carry
jle imm8 36 2 I+=imm8 if Zero | !Carry
Stack (S):
pha 40 2 *(S++)=A
@ -135,6 +140,18 @@ ldc *p 5F 2 C=*P
lda *q 55 2 A=*Q
ldb *q 61 2 B=*Q
ldc *q 62 2 C=*Q
sta *p++ C0 2 *P++=A
stb *p++ C1 2 *P++=B
stc *p++ C2 2 *P++=C
sta *q++ C3 2 *Q++=A
stb *q++ C4 2 *Q++=B
stc *q++ C5 2 *Q++=C
lda *p++ C6 2 A=*P++
ldb *p++ C7 2 B=*P++
ldc *p++ C8 2 C=*P++
lda *q++ C9 2 A=*Q++
ldb *q++ CA 2 B=*Q++
ldc *q++ CB 2 C=*Q++
16-bit Load/Store (W):
ldp imm16 21 3 P=imm16
@ -155,6 +172,10 @@ ldp *q 94 3 P=*Q
ldq *q 95 3 Q=*Q
stp *q 7C 3 *Q=P
stq *p 7D 3 *P=Q
ldq *p++ CC 3 Q=*P++
ldp *q++ CD 3 P=*Q++
stp *q++ CE 3 *Q++=P
stq *p++ CF 3 *P++=Q
Moves (M):
lda b 80 1 A=B
@ -176,13 +197,13 @@ ldq p 8E 1 Q=P
lds p 8F 1 S=P
ldv p 90 1 V=P
Opcodes used: 164/255
Opcodes used: 183/255
0123456789ABCDEF
00 | C---------------
10 | UUIIUIIUUUUUUUUU
20 | BWWWAWBBBBBUUUU-
30 | JJJJJJJ---------
40 | SSSSSSSSSS------
40 | SSSSSSSSSSXXX---
50 | BBBBBBBBBBBBBBBB
60 | JBBJJJJJWWWWWWWW
70 | AAAAAAAAAAWWWWWW
@ -190,7 +211,7 @@ Opcodes used: 164/255
90 | MMWWWWBBBAAAAAAA
A0 | AAAAAAAAAAAAAAAA
B0 | AAAAAAAAAAAAAA--
C0 | ----------------
C0 | BBBBBBBBBBBBWWWW
D0 | ----------------
E0 | ----------------
F0 | CCCCC-----------

6
readme.txt
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@ -3,10 +3,12 @@
How to use the assembler:
1. Install bllua3 from https://notabug.org/redo/bllua3
2. Clone this repo into the Blockland folder
2. Download this repo somewhere into the Blockland folder
3. In BL console,
luaexec("your_path/assembler-8608.lua");
4. To assemble a program, place a 1x1f ghost brick on the top-left corner of the ROM, face forward, and in BL console do
AssembleFile("other_path/filename.asm", "RomX RomY RomZ"); where RomX is the width of the ROM, RomY is the depth front to back, and RomZ is the height in bits.
AssembleFile("other_path/filename.asm", "RomX RomY RomZ"); where RomX is the width of the ROM, RomY is the depth front to back, and RomZ is the height in bits, i.e. "16 16 8"
You can also run the assembler from the command line to get a memory dump and disassembly in stdout, if you have lua installed:
luajit "your_path/assembler-8608.lua" "other_path/filename.asm"
For a list of instructions, see instructionList.txt

52
rom-8608-defs.lua
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@ -77,6 +77,13 @@ operations = {
adrrUT = {"adrrhU","adrrlT"},
adwrCB = {"adwrhC","adwrlB"},
adwIncUT = {"adwrUT","adwInc"},
adwP = {"adwlP","adwSaveP"},
adwQ = {"adwlQ","adwSaveQ"},
adwS = {"adwlS","adwSaveS"},
incP = {"adwP","adwInc"},
incQ = {"adwQ","adwInc"},
incP2 = {"adwP","adwr2"},
incQ2 = {"adwP","adwr2"},
jmpRelT = {"instrNext","adrrTX"},
jmpAbs = {"base","loadInstr","adrSaveI"},
@ -126,6 +133,11 @@ instructions = {
{ mnem="icc *s+imm8", opcode=0x2D, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU", "aluCinC", "aluAdd","aluSaveCarry","aluSaveNZ","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)+=CF, set flags" },
{ mnem="tst *s+imm8", opcode=0x2E, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"alulU","aluRun","aluRInv","aluCinOn","aluAdd","aluSaveCarry","aluSaveNZ","instrNext"}, desc="Set flags according to *(S+imm8)-0" },
{ category = "16-bit Arithmetic", catlet = "X"},
{ mnem="adp imm8" , opcode=0x4A, {"loadImmedT","instrSub1"}, {"adwP","adwrTX","instrNext"}, desc="P+=imm8 signed"},
{ mnem="adq imm8" , opcode=0x4B, {"loadImmedT","instrSub1"}, {"adwQ","adwrTX","instrNext"}, desc="Q+=imm8 signed"},
{ mnem="ads imm8" , opcode=0x4C, {"loadImmedT","instrSub1"}, {"adwS","adwrTX","instrNext"}, desc="S+=imm8 signed"},
{ category = "8-bit Arithmetic/Logic", catlet="A" },
{ mnem="add imm8" , opcode=0x24, {"loadImmedT","instrSub1"}, {"aluA", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="A+=imm8, set flags" },
{ mnem="adb imm8" , opcode=0x72, {"loadImmedT","instrSub1"}, {"aluB", "alurT","aluAdd", "aluSaveCarry","aluSaveNZ","instrNext"}, desc="B+=imm8, set flags" },
@ -219,18 +231,30 @@ instructions = {
{ mnem="sta *imm16" , opcode=0x50, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurA","instrSub3"}, {"instrNext"}, desc="*imm16=A" },
{ mnem="stb *imm16" , opcode=0x58, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurB","instrSub3"}, {"instrNext"}, desc="*imm16=B" },
{ mnem="stc *imm16" , opcode=0x59, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurC","instrSub3"}, {"instrNext"}, desc="*imm16=C" },
{ mnem="sta *p" , opcode=0x52, {"adrlP","storeReg","alurA","instrSub1"}, {"instrNext"}, desc="*P=A" },
{ mnem="stb *p" , opcode=0x5A, {"adrlP","storeReg","alurB","instrSub1"}, {"instrNext"}, desc="*P=B" },
{ mnem="stc *p" , opcode=0x5B, {"adrlP","storeReg","alurC","instrSub1"}, {"instrNext"}, desc="*P=C" },
{ mnem="sta *q" , opcode=0x54, {"adrlQ","storeReg","alurA","instrSub1"}, {"instrNext"}, desc="*Q=A" },
{ mnem="stb *q" , opcode=0x5C, {"adrlQ","storeReg","alurB","instrSub1"}, {"instrNext"}, desc="*Q=B" },
{ mnem="stc *q" , opcode=0x5D, {"adrlQ","storeReg","alurC","instrSub1"}, {"instrNext"}, desc="*Q=C" },
{ mnem="lda *p" , opcode=0x53, {"adrlP","loadReg","memSaveA","instrSub1"}, {"instrNext"}, desc="A=*P" },
{ mnem="ldb *p" , opcode=0x5E, {"adrlP","loadReg","memSaveB","instrSub1"}, {"instrNext"}, desc="B=*P" },
{ mnem="ldc *p" , opcode=0x5F, {"adrlP","loadReg","memSaveC","instrSub1"}, {"instrNext"}, desc="C=*P" },
{ mnem="lda *q" , opcode=0x55, {"adrlQ","loadReg","memSaveA","instrSub1"}, {"instrNext"}, desc="A=*Q" },
{ mnem="ldb *q" , opcode=0x61, {"adrlQ","loadReg","memSaveB","instrSub1"}, {"instrNext"}, desc="B=*Q" },
{ mnem="ldc *q" , opcode=0x62, {"adrlQ","loadReg","memSaveC","instrSub1"}, {"instrNext"}, desc="C=*Q" },
{ mnem="sta *p" , opcode=0x52, {"adrlP","storeReg","alurA", "instrSub1"}, {"instrNext"}, desc="*P=A" },
{ mnem="stb *p" , opcode=0x5A, {"adrlP","storeReg","alurB", "instrSub1"}, {"instrNext"}, desc="*P=B" },
{ mnem="stc *p" , opcode=0x5B, {"adrlP","storeReg","alurC", "instrSub1"}, {"instrNext"}, desc="*P=C" },
{ mnem="sta *q" , opcode=0x54, {"adrlQ","storeReg","alurA", "instrSub1"}, {"instrNext"}, desc="*Q=A" },
{ mnem="stb *q" , opcode=0x5C, {"adrlQ","storeReg","alurB", "instrSub1"}, {"instrNext"}, desc="*Q=B" },
{ mnem="stc *q" , opcode=0x5D, {"adrlQ","storeReg","alurC", "instrSub1"}, {"instrNext"}, desc="*Q=C" },
{ mnem="lda *p" , opcode=0x53, {"adrlP","loadReg","memSaveA", "instrSub1"}, {"instrNext"}, desc="A=*P" },
{ mnem="ldb *p" , opcode=0x5E, {"adrlP","loadReg","memSaveB", "instrSub1"}, {"instrNext"}, desc="B=*P" },
{ mnem="ldc *p" , opcode=0x5F, {"adrlP","loadReg","memSaveC", "instrSub1"}, {"instrNext"}, desc="C=*P" },
{ mnem="lda *q" , opcode=0x55, {"adrlQ","loadReg","memSaveA", "instrSub1"}, {"instrNext"}, desc="A=*Q" },
{ mnem="ldb *q" , opcode=0x61, {"adrlQ","loadReg","memSaveB", "instrSub1"}, {"instrNext"}, desc="B=*Q" },
{ mnem="ldc *q" , opcode=0x62, {"adrlQ","loadReg","memSaveC", "instrSub1"}, {"instrNext"}, desc="C=*Q" },
{ mnem="sta *p++" , opcode=0xC0, {"adrlP","storeReg","alurA", "incP","instrSub1"}, {"instrNext"}, desc="*P++=A" },
{ mnem="stb *p++" , opcode=0xC1, {"adrlP","storeReg","alurB", "incP","instrSub1"}, {"instrNext"}, desc="*P++=B" },
{ mnem="stc *p++" , opcode=0xC2, {"adrlP","storeReg","alurC", "incP","instrSub1"}, {"instrNext"}, desc="*P++=C" },
{ mnem="sta *q++" , opcode=0xC3, {"adrlQ","storeReg","alurA", "incQ","instrSub1"}, {"instrNext"}, desc="*Q++=A" },
{ mnem="stb *q++" , opcode=0xC4, {"adrlQ","storeReg","alurB", "incQ","instrSub1"}, {"instrNext"}, desc="*Q++=B" },
{ mnem="stc *q++" , opcode=0xC5, {"adrlQ","storeReg","alurC", "incQ","instrSub1"}, {"instrNext"}, desc="*Q++=C" },
{ mnem="lda *p++" , opcode=0xC6, {"adrlP","loadReg","memSaveA","incP","instrSub1"}, {"instrNext"}, desc="A=*P++" },
{ mnem="ldb *p++" , opcode=0xC7, {"adrlP","loadReg","memSaveB","incP","instrSub1"}, {"instrNext"}, desc="B=*P++" },
{ mnem="ldc *p++" , opcode=0xC8, {"adrlP","loadReg","memSaveC","incP","instrSub1"}, {"instrNext"}, desc="C=*P++" },
{ mnem="lda *q++" , opcode=0xC9, {"adrlQ","loadReg","memSaveA","incQ","instrSub1"}, {"instrNext"}, desc="A=*Q++" },
{ mnem="ldb *q++" , opcode=0xCA, {"adrlQ","loadReg","memSaveB","incQ","instrSub1"}, {"instrNext"}, desc="B=*Q++" },
{ mnem="ldc *q++" , opcode=0xCB, {"adrlQ","loadReg","memSaveC","incQ","instrSub1"}, {"instrNext"}, desc="C=*Q++" },
{ category = "16-bit Load/Store", catlet="W" },
{ mnem="ldp imm16" , opcode=0x21, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=imm16" },
@ -251,6 +275,10 @@ instructions = {
{ mnem="ldq *q" , opcode=0x95, {"adrlQ","load161","instrSub1"}, {"adrlQ","load162","instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*Q" },
{ mnem="stp *q" , opcode=0x7C, {"adrlQ","store161","alurPH","instrSub1"}, {"adrlQ","store162","alurPL","instrSub2"}, {"instrNext"}, desc="*Q=P" },
{ mnem="stq *p" , opcode=0x7D, {"adrlP","store161","alurQH","instrSub1"}, {"adrlP","store162","alurQL","instrSub2"}, {"instrNext"}, desc="*P=Q" },
{ mnem="ldq *p++" , opcode=0xCC, {"adrlP","load161","instrSub1"}, {"adrlP","load162","instrSub2","incP2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*P++++" },
{ mnem="ldp *q++" , opcode=0xCD, {"adrlQ","load161","instrSub1"}, {"adrlQ","load162","instrSub2","incQ2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*Q++++" },
{ mnem="stp *q++" , opcode=0xCE, {"adrlQ","store161","alurPH","instrSub1"}, {"adrlQ","store162","alurPL","instrSub2","incQ2"}, {"instrNext"}, desc="*Q++++=P" },
{ mnem="stq *p++" , opcode=0xCF, {"adrlP","store161","alurQH","instrSub1"}, {"adrlP","store162","alurQL","instrSub2","incP2"}, {"instrNext"}, desc="*P++++=Q" },
{ category = "Moves", catlet="M" },
{ mnem="lda b" , opcode=0x80, {"alurB" ,"aluAdd","aluSaveA","instrNext"}, desc="A=B" },