redo/Brick_LuaLogic
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make states numbers instead of booleans

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Redo0
2021-05-29 13:14:50 -05:00
parent b08c3cd0c4
commit 16c1a9f75f
309 changed files with 2819 additions and 2819 deletions
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10
bricks/math/8bitAdder.cs
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@ -18,16 +18,16 @@ datablock fxDTSBrickData(LogicGate_8bitAdder_Data)
logicUpdate =
"return function(gate) " @
" local c = bool_to_int[Gate.getportstate(gate, 17)] " @
" local c = Gate.getportstate(gate, 17) " @
" local a = 0 " @
" local b = 0 " @
" for i = 1, 8 do " @
" a = bool_to_int[Gate.getportstate(gate, i )] " @
" b = bool_to_int[Gate.getportstate(gate, i+8)] " @
" Gate.setportstate(gate, i+17, bit.bxor(bit.bxor(a, b), c) == 1) " @
" a = Gate.getportstate(gate, i ) " @
" b = Gate.getportstate(gate, i+8) " @
" Gate.setportstate(gate, i+17, bit.bxor(bit.bxor(a, b), c)) " @
" c = bit.bor(bit.band(a, b), bit.band(c, bit.bor(a, b))) " @
" end " @
" Gate.setportstate(gate, 26, c == 1) " @
" Gate.setportstate(gate, 26, c) " @
"end"
;

12
bricks/math/8bitDivider.cs
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@ -21,21 +21,21 @@ datablock fxDTSBrickData(LogicGate_8bitDivider_Data)
" local a, b, n = 0, 0 " @
" for i = 1, 8 do " @
" local n = 2^(i-1) " @
" a = a + bool_to_int[Gate.getportstate(gate, i )] * n " @
" b = b + bool_to_int[Gate.getportstate(gate, i+8)] * n " @
" a = a + Gate.getportstate(gate, i ) * n " @
" b = b + Gate.getportstate(gate, i+8) * n " @
" end " @
" if b ~= 0 then " @
" local q = math.floor(a/b) " @
" local r = a-q*b " @
" for i = 1, 8 do " @
" local n = 2^(i-1) " @
" Gate.setportstate(gate, i+16, bit.band(q, n) > 0) " @
" Gate.setportstate(gate, i+24, bit.band(r, n) > 0) " @
" Gate.setportstate(gate, i+16, (bit.band(q, n) > 0) and 1 or 0) " @
" Gate.setportstate(gate, i+24, (bit.band(r, n) > 0) and 1 or 0) " @
" end " @
" else " @
" for i = 1, 8 do " @
" Gate.setportstate(gate, i+16, false) " @
" Gate.setportstate(gate, i+24, false) " @
" Gate.setportstate(gate, i+16, 0) " @
" Gate.setportstate(gate, i+24, 0) " @
" end " @
" end " @
"end"

6
bricks/math/8bitMultiplier.cs
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@ -20,12 +20,12 @@ datablock fxDTSBrickData(LogicGate_8bitMultiplier_Data)
"return function(gate) local a, b = 0, 0 " @
" local sum = 0 " @
" for i = 1, 8 do " @
" a = a + bool_to_int[Gate.getportstate(gate, i )] * 2^(i-1) " @
" b = b + bool_to_int[Gate.getportstate(gate, i+8)] * 2^(i-1) " @
" a = a + Gate.getportstate(gate, i ) * 2^(i-1) " @
" b = b + Gate.getportstate(gate, i+8) * 2^(i-1) " @
" end " @
" local sum = a * b " @
" for i = 1, 16 do " @
" Gate.setportstate(gate, i+16, bit.band(sum, 2^(i-1)) > 0) " @
" Gate.setportstate(gate, i+16, (bit.band(sum, 2^(i-1)) > 0) and 1 or 0) " @
" end " @
"end"
;

10
bricks/math/8bitSubtractor.cs
View File

@ -18,16 +18,16 @@ datablock fxDTSBrickData(LogicGate_8bitSubtractor_Data)
logicUpdate =
"return function(gate) " @
" local c = bool_to_int[Gate.getportstate(gate, 17)] " @
" local c = Gate.getportstate(gate, 17) " @
" local a = 0 " @
" local b = 0 " @
" for i = 1, 8 do " @
" a = bool_to_int[Gate.getportstate(gate, i )] " @
" b = bool_to_int[Gate.getportstate(gate, i+8)] " @
" Gate.setportstate(gate, i+17, bit.bxor(bit.bxor(a, b), c) == 1) " @
" a = Gate.getportstate(gate, i ) " @
" b = Gate.getportstate(gate, i+8) " @
" Gate.setportstate(gate, i+17, bit.bxor(bit.bxor(a, b), c)) " @
" c = bit.bor(bit.bor(bit.band(bool_to_int[a == 0], b), bit.band(bool_to_int[a == 0], c)), bit.band(b, c)) " @
" end " @
" Gate.setportstate(gate, 26, c == 1) " @
" Gate.setportstate(gate, 26, c) " @
"end"
;

6
bricks/math/FullAdder.cs
View File

@ -18,9 +18,9 @@ datablock fxDTSBrickData(LogicGate_FullAdder_Data)
logicUpdate =
"return function(gate) " @
" local a, b, c = bool_to_int[Gate.getportstate(gate, 1)], bool_to_int[Gate.getportstate(gate, 2)], bool_to_int[Gate.getportstate(gate, 3)] " @
" Gate.setportstate(gate, 4, bit.bxor(bit.bxor(a, b), c) == 1) " @
" Gate.setportstate(gate, 5, bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b)) == 1) " @
" local a, b, c = Gate.getportstate(gate, 1), Gate.getportstate(gate, 2), Gate.getportstate(gate, 3) " @
" Gate.setportstate(gate, 4, bit.bxor(bit.bxor(a, b), c)) " @
" Gate.setportstate(gate, 5, bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b))) " @
"end"
;

4
bricks/math/HalfAdder.cs
View File

@ -18,8 +18,8 @@ datablock fxDTSBrickData(LogicGate_HalfAdder_Data)
logicUpdate =
"return function(gate) " @
" Gate.setportstate(gate, 3, bit.bxor(bool_to_int[Gate.getportstate(gate, 1)], bool_to_int[Gate.getportstate(gate, 2)]) == 1) " @
" Gate.setportstate(gate, 4, Gate.getportstate(gate, 1) and Gate.getportstate(gate, 2)) " @
" Gate.setportstate(gate, 3, bit.bxor(Gate.getportstate(gate, 1), Gate.getportstate(gate, 2)) == 1) " @
" Gate.setportstate(gate, 4, (Gate.getportstate(gate, 1) and Gate.getportstate(gate, 2)) and 1 or 0) " @
"end"
;