add enabler, wider buses, and pixel brick
This commit is contained in:
parent
1fad9fd375
commit
4095d193ff
294
bricks/blb/TextBrickUpsidedown.blb
Normal file
294
bricks/blb/TextBrickUpsidedown.blb
Normal file
@ -0,0 +1,294 @@
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1 1 2
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SPECIAL
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u
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d
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1
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0 0 0
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1 1 2
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COVERAGE:
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1 : 1
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1 : 1
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1 : 2
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1 : 2
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1 : 2
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1 : 2
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----------------top quads:
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1
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TEX:TOP
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POSITION:
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0.5 0.5 1
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0.5 -0.5 1
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-0.5 -0.5 1
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-0.5 0.5 1
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UV COORDS:
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0 1
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0 0
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1 0
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1 1
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NORMALS:
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0 0 1
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0 0 1
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0 0 1
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0 0 1
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----------------bottom quads:
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4
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TEX:BOTTOMEDGE
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POSITION:
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-0.5 -0.5 -1
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0.5 -0.5 -1
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0 0 -1
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0 0 -1
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UV COORDS:
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-0.5 0
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0.5 0
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0 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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0.5 0.5 -1
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-0.5 0.5 -1
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0 0 -1
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0 0 -1
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UV COORDS:
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-0.5 0
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0.5 0
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0 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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0.5 -0.5 -1
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0.5 0.5 -1
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0 0 -1
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0 0 -1
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UV COORDS:
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-0.5 0
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0.5 0
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0 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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-0.5 0.5 -1
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-0.5 -0.5 -1
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0 0 -1
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0 0 -1
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UV COORDS:
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-0.5 0
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0.5 0
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0 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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----------------north quads:
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1
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TEX:PRINT
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POSITION:
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-0.5 0.5 1
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-0.5 0.5 -1
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0.5 0.5 -1
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0.5 0.5 1
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UV COORDS:
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1 0
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1 1
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0 1
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0 0
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NORMALS:
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0 1 0
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0 1 0
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0 1 0
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0 1 0
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----------------east quads:
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1
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TEX:SIDE
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POSITION:
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0.5 -0.5 1
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0.5 0.5 1
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0.5 0.5 -1
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0.5 -0.5 -1
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UV COORDS:
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-0.0214844 -0.0322266
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1.02148 -0.0322266
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1.02148 1.03223
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-0.0214844 1.03223
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NORMALS:
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1 0 0
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1 0 0
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1 0 0
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1 0 0
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----------------south quads:
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6
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TEX:SIDE
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POSITION:
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0.5 -0.5 1
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0.5 -0.5 -1
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-0.5 -0.5 -1
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-0.5 -0.5 1
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UV COORDS:
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1.02148 -0.0322266
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1.02148 1.03223
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-0.0214844 1.03223
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-0.0214844 -0.0322266
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NORMALS:
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0 -1 0
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0 -1 0
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0 -1 0
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0 -1 0
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TEX:SIDE
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POSITION:
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-0.4 -0.64 0.2
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0.4 -0.64 0.2
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0.4 -0.5 0.2
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-0.4 -0.5 0.2
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:SIDE
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POSITION:
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-0.4 -0.64 0.2
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-0.4 -0.64 0.8
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0.4 -0.64 0.8
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0.4 -0.64 0.2
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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0 -1 0
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0 -1 0
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0 -1 0
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0 -1 0
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TEX:SIDE
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POSITION:
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0.4 -0.64 0.8
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-0.4 -0.64 0.8
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-0.4 -0.5 0.8
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0.4 -0.5 0.8
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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0 0 1
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0 0 1
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0 0 1
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0 0 1
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TEX:SIDE
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POSITION:
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0.4 -0.64 0.2
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0.4 -0.64 0.8
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0.4 -0.5 0.8
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0.4 -0.5 0.2
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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1 0 0
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1 0 0
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1 0 0
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1 0 0
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TEX:SIDE
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POSITION:
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-0.4 -0.64 0.8
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-0.4 -0.64 0.2
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-0.4 -0.5 0.2
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-0.4 -0.5 0.8
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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-1 0 0
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-1 0 0
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-1 0 0
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-1 0 0
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----------------west quads:
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1
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TEX:SIDE
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POSITION:
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-0.5 -0.5 -1
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-0.5 0.5 -1
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-0.5 0.5 1
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-0.5 -0.5 1
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UV COORDS:
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1.02148 1.03223
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-0.0214844 1.03223
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-0.0214844 -0.0322266
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1.02148 -0.0322266
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NORMALS:
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-1 0 0
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-1 0 0
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-1 0 0
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-1 0 0
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----------------omni quads:
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0
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@ -19,6 +19,7 @@ exec("./math/8bitDivider.cs");
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exec("./math/FullAdder.cs");
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exec("./math/FullAdder.cs");
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exec("./math/HalfAdder.cs");
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exec("./math/HalfAdder.cs");
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exec("./outputs/Pixel3.cs");
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exec("./outputs/TextBrick2.cs");
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exec("./outputs/TextBrick2.cs");
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exec("./special/EventGate.cs");
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exec("./special/EventGate.cs");
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@ -118,6 +118,8 @@ exec("./newcode/D FlipFlop 15 Bit.cs");
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exec("./newcode/D FlipFlop 16 Bit.cs");
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exec("./newcode/D FlipFlop 16 Bit.cs");
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exec("./newcode/D FlipFlop 24 Bit.cs");
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exec("./newcode/D FlipFlop 24 Bit.cs");
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exec("./newcode/D FlipFlop 32 Bit.cs");
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exec("./newcode/D FlipFlop 32 Bit.cs");
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exec("./newcode/D FlipFlop 48 Bit.cs");
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exec("./newcode/D FlipFlop 64 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 1 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 1 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 2 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 2 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 3 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 3 Bit.cs");
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@ -136,6 +138,8 @@ exec("./newcode/D FlipFlop Active Low 15 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 16 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 16 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 24 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 24 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 32 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 32 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 48 Bit.cs");
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exec("./newcode/D FlipFlop Active Low 64 Bit.cs");
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exec("./newcode/Buffer 1 Bit.cs");
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exec("./newcode/Buffer 1 Bit.cs");
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exec("./newcode/Buffer 2 Bit.cs");
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exec("./newcode/Buffer 2 Bit.cs");
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exec("./newcode/Buffer 3 Bit.cs");
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exec("./newcode/Buffer 3 Bit.cs");
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@ -154,6 +158,8 @@ exec("./newcode/Buffer 15 Bit.cs");
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exec("./newcode/Buffer 16 Bit.cs");
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exec("./newcode/Buffer 16 Bit.cs");
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exec("./newcode/Buffer 24 Bit.cs");
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exec("./newcode/Buffer 24 Bit.cs");
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exec("./newcode/Buffer 32 Bit.cs");
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exec("./newcode/Buffer 32 Bit.cs");
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exec("./newcode/Buffer 48 Bit.cs");
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exec("./newcode/Buffer 64 Bit.cs");
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exec("./newcode/Buffer Active Low 1 Bit.cs");
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exec("./newcode/Buffer Active Low 1 Bit.cs");
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exec("./newcode/Buffer Active Low 2 Bit.cs");
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exec("./newcode/Buffer Active Low 2 Bit.cs");
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exec("./newcode/Buffer Active Low 3 Bit.cs");
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exec("./newcode/Buffer Active Low 3 Bit.cs");
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@ -172,6 +178,48 @@ exec("./newcode/Buffer Active Low 15 Bit.cs");
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exec("./newcode/Buffer Active Low 16 Bit.cs");
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exec("./newcode/Buffer Active Low 16 Bit.cs");
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exec("./newcode/Buffer Active Low 24 Bit.cs");
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exec("./newcode/Buffer Active Low 24 Bit.cs");
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exec("./newcode/Buffer Active Low 32 Bit.cs");
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exec("./newcode/Buffer Active Low 32 Bit.cs");
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exec("./newcode/Buffer Active Low 48 Bit.cs");
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exec("./newcode/Buffer Active Low 64 Bit.cs");
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exec("./newcode/Enabler 1 Bit.cs");
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exec("./newcode/Enabler 2 Bit.cs");
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exec("./newcode/Enabler 3 Bit.cs");
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exec("./newcode/Enabler 4 Bit.cs");
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exec("./newcode/Enabler 5 Bit.cs");
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exec("./newcode/Enabler 6 Bit.cs");
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exec("./newcode/Enabler 7 Bit.cs");
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exec("./newcode/Enabler 8 Bit.cs");
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exec("./newcode/Enabler 9 Bit.cs");
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exec("./newcode/Enabler 10 Bit.cs");
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exec("./newcode/Enabler 11 Bit.cs");
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exec("./newcode/Enabler 12 Bit.cs");
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exec("./newcode/Enabler 13 Bit.cs");
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exec("./newcode/Enabler 14 Bit.cs");
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exec("./newcode/Enabler 15 Bit.cs");
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exec("./newcode/Enabler 16 Bit.cs");
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exec("./newcode/Enabler 24 Bit.cs");
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exec("./newcode/Enabler 32 Bit.cs");
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exec("./newcode/Enabler 48 Bit.cs");
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exec("./newcode/Enabler 64 Bit.cs");
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exec("./newcode/Enabler Active Low 1 Bit.cs");
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exec("./newcode/Enabler Active Low 2 Bit.cs");
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exec("./newcode/Enabler Active Low 3 Bit.cs");
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exec("./newcode/Enabler Active Low 4 Bit.cs");
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exec("./newcode/Enabler Active Low 5 Bit.cs");
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exec("./newcode/Enabler Active Low 6 Bit.cs");
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exec("./newcode/Enabler Active Low 7 Bit.cs");
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exec("./newcode/Enabler Active Low 8 Bit.cs");
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exec("./newcode/Enabler Active Low 9 Bit.cs");
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exec("./newcode/Enabler Active Low 10 Bit.cs");
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exec("./newcode/Enabler Active Low 11 Bit.cs");
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exec("./newcode/Enabler Active Low 12 Bit.cs");
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exec("./newcode/Enabler Active Low 13 Bit.cs");
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exec("./newcode/Enabler Active Low 14 Bit.cs");
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exec("./newcode/Enabler Active Low 15 Bit.cs");
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exec("./newcode/Enabler Active Low 16 Bit.cs");
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exec("./newcode/Enabler Active Low 24 Bit.cs");
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exec("./newcode/Enabler Active Low 32 Bit.cs");
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exec("./newcode/Enabler Active Low 48 Bit.cs");
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exec("./newcode/Enabler Active Low 64 Bit.cs");
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exec("./newcode/Demux 1 Bit.cs");
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exec("./newcode/Demux 1 Bit.cs");
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exec("./newcode/Demux 2 Bit.cs");
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exec("./newcode/Demux 2 Bit.cs");
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exec("./newcode/Demux 3 Bit.cs");
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exec("./newcode/Demux 3 Bit.cs");
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10853
bricks/gen/newbricks/Buffer 48 Bit.blb
Normal file
10853
bricks/gen/newbricks/Buffer 48 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
14373
bricks/gen/newbricks/Buffer 64 Bit.blb
Normal file
14373
bricks/gen/newbricks/Buffer 64 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
10853
bricks/gen/newbricks/Buffer Active Low 48 Bit.blb
Normal file
10853
bricks/gen/newbricks/Buffer Active Low 48 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
14373
bricks/gen/newbricks/Buffer Active Low 64 Bit.blb
Normal file
14373
bricks/gen/newbricks/Buffer Active Low 64 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
10853
bricks/gen/newbricks/D FlipFlop 48 Bit.blb
Normal file
10853
bricks/gen/newbricks/D FlipFlop 48 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
14373
bricks/gen/newbricks/D FlipFlop 64 Bit.blb
Normal file
14373
bricks/gen/newbricks/D FlipFlop 64 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
10853
bricks/gen/newbricks/D FlipFlop Active Low 48 Bit.blb
Normal file
10853
bricks/gen/newbricks/D FlipFlop Active Low 48 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
14373
bricks/gen/newbricks/D FlipFlop Active Low 64 Bit.blb
Normal file
14373
bricks/gen/newbricks/D FlipFlop Active Low 64 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
513
bricks/gen/newbricks/Enabler 1 Bit.blb
Normal file
513
bricks/gen/newbricks/Enabler 1 Bit.blb
Normal file
@ -0,0 +1,513 @@
|
|||||||
|
1 1 1
|
||||||
|
SPECIAL
|
||||||
|
|
||||||
|
b
|
||||||
|
|
||||||
|
1
|
||||||
|
|
||||||
|
0 0 0
|
||||||
|
1 1 1
|
||||||
|
COVERAGE:
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
----------------top quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:PRINT
|
||||||
|
POSITION:
|
||||||
|
0.5 0.5 0.5
|
||||||
|
0.5 -0.5 0.5
|
||||||
|
-0.5 -0.5 0.5
|
||||||
|
-0.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 0
|
||||||
|
1 1
|
||||||
|
0 1
|
||||||
|
0 0
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
----------------bottom quads:
|
||||||
|
4
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
----------------north quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.5 0.5 0.5
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
0.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.4 0.5 0.3
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
----------------east quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.5 -0.5 0.5
|
||||||
|
0.5 0.5 0.5
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 -0.4 -0.3
|
||||||
|
0.64 0.4 -0.3
|
||||||
|
0.5 0.4 -0.3
|
||||||
|
0.5 -0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 -0.4 -0.3
|
||||||
|
0.64 -0.4 0.3
|
||||||
|
0.64 0.4 0.3
|
||||||
|
0.64 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 0.4 0.3
|
||||||
|
0.64 -0.4 0.3
|
||||||
|
0.5 -0.4 0.3
|
||||||
|
0.5 0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 0.4 -0.3
|
||||||
|
0.64 0.4 0.3
|
||||||
|
0.5 0.4 0.3
|
||||||
|
0.5 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 -0.4 0.3
|
||||||
|
0.64 -0.4 -0.3
|
||||||
|
0.5 -0.4 -0.3
|
||||||
|
0.5 -0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
----------------south quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.5 -0.5 0.5
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
-0.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------west quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
-0.5 0.5 0.5
|
||||||
|
-0.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------omni quads:
|
||||||
|
0
|
2493
bricks/gen/newbricks/Enabler 10 Bit.blb
Normal file
2493
bricks/gen/newbricks/Enabler 10 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2713
bricks/gen/newbricks/Enabler 11 Bit.blb
Normal file
2713
bricks/gen/newbricks/Enabler 11 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2933
bricks/gen/newbricks/Enabler 12 Bit.blb
Normal file
2933
bricks/gen/newbricks/Enabler 12 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3153
bricks/gen/newbricks/Enabler 13 Bit.blb
Normal file
3153
bricks/gen/newbricks/Enabler 13 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3373
bricks/gen/newbricks/Enabler 14 Bit.blb
Normal file
3373
bricks/gen/newbricks/Enabler 14 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3593
bricks/gen/newbricks/Enabler 15 Bit.blb
Normal file
3593
bricks/gen/newbricks/Enabler 15 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3813
bricks/gen/newbricks/Enabler 16 Bit.blb
Normal file
3813
bricks/gen/newbricks/Enabler 16 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
733
bricks/gen/newbricks/Enabler 2 Bit.blb
Normal file
733
bricks/gen/newbricks/Enabler 2 Bit.blb
Normal file
@ -0,0 +1,733 @@
|
|||||||
|
2 1 1
|
||||||
|
SPECIAL
|
||||||
|
|
||||||
|
bb
|
||||||
|
|
||||||
|
1
|
||||||
|
|
||||||
|
0 0 0
|
||||||
|
2 1 1
|
||||||
|
COVERAGE:
|
||||||
|
1 : 2
|
||||||
|
1 : 2
|
||||||
|
1 : 2
|
||||||
|
1 : 1
|
||||||
|
1 : 2
|
||||||
|
1 : 1
|
||||||
|
----------------top quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:PRINT
|
||||||
|
POSITION:
|
||||||
|
1 0.5 0.5
|
||||||
|
1 -0.5 0.5
|
||||||
|
-1 -0.5 0.5
|
||||||
|
-1 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 0
|
||||||
|
1 1
|
||||||
|
0 1
|
||||||
|
0 0
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
----------------bottom quads:
|
||||||
|
4
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
1 -0.5 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
1.5 0
|
||||||
|
1 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1 0.5 -0.5
|
||||||
|
-1 0.5 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
1.5 0
|
||||||
|
1 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1 -0.5 -0.5
|
||||||
|
1 0.5 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1 0.5 -0.5
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
----------------north quads:
|
||||||
|
11
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1 0.5 0.5
|
||||||
|
-1 0.5 -0.5
|
||||||
|
1 0.5 -0.5
|
||||||
|
1 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 -0.0859375
|
||||||
|
1 1.0859375
|
||||||
|
0 1.0859375
|
||||||
|
0 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.82 0.75 -0.24
|
||||||
|
0.18 0.75 -0.24
|
||||||
|
0.1 0.5 -0.3
|
||||||
|
0.9 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.82 0.75 -0.24
|
||||||
|
0.82 0.75 0.24
|
||||||
|
0.18 0.75 0.24
|
||||||
|
0.18 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.18 0.75 0.24
|
||||||
|
0.82 0.75 0.24
|
||||||
|
0.9 0.5 0.3
|
||||||
|
0.1 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.18 0.75 -0.24
|
||||||
|
0.18 0.75 0.24
|
||||||
|
0.1 0.5 0.3
|
||||||
|
0.1 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.82 0.75 0.24
|
||||||
|
0.82 0.75 -0.24
|
||||||
|
0.9 0.5 -0.3
|
||||||
|
0.9 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.18 0.75 -0.24
|
||||||
|
-0.82 0.75 -0.24
|
||||||
|
-0.9 0.5 -0.3
|
||||||
|
-0.1 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.18 0.75 -0.24
|
||||||
|
-0.18 0.75 0.24
|
||||||
|
-0.82 0.75 0.24
|
||||||
|
-0.82 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.82 0.75 0.24
|
||||||
|
-0.18 0.75 0.24
|
||||||
|
-0.1 0.5 0.3
|
||||||
|
-0.9 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.82 0.75 -0.24
|
||||||
|
-0.82 0.75 0.24
|
||||||
|
-0.9 0.5 0.3
|
||||||
|
-0.9 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.18 0.75 0.24
|
||||||
|
-0.18 0.75 -0.24
|
||||||
|
-0.1 0.5 -0.3
|
||||||
|
-0.1 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
----------------east quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1 -0.5 0.5
|
||||||
|
1 0.5 0.5
|
||||||
|
1 0.5 -0.5
|
||||||
|
1 -0.5 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 -0.4 -0.3
|
||||||
|
1.14 0.4 -0.3
|
||||||
|
1 0.4 -0.3
|
||||||
|
1 -0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 -0.4 -0.3
|
||||||
|
1.14 -0.4 0.3
|
||||||
|
1.14 0.4 0.3
|
||||||
|
1.14 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 0.4 0.3
|
||||||
|
1.14 -0.4 0.3
|
||||||
|
1 -0.4 0.3
|
||||||
|
1 0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 0.4 -0.3
|
||||||
|
1.14 0.4 0.3
|
||||||
|
1 0.4 0.3
|
||||||
|
1 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 -0.4 0.3
|
||||||
|
1.14 -0.4 -0.3
|
||||||
|
1 -0.4 -0.3
|
||||||
|
1 -0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
----------------south quads:
|
||||||
|
11
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1 -0.5 0.5
|
||||||
|
1 -0.5 -0.5
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
-1 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 -0.0859375
|
||||||
|
1 1.0859375
|
||||||
|
0 1.0859375
|
||||||
|
0 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.1 -0.64 -0.3
|
||||||
|
0.9 -0.64 -0.3
|
||||||
|
0.9 -0.5 -0.3
|
||||||
|
0.1 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.1 -0.64 -0.3
|
||||||
|
0.1 -0.64 0.3
|
||||||
|
0.9 -0.64 0.3
|
||||||
|
0.9 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.9 -0.64 0.3
|
||||||
|
0.1 -0.64 0.3
|
||||||
|
0.1 -0.5 0.3
|
||||||
|
0.9 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.9 -0.64 -0.3
|
||||||
|
0.9 -0.64 0.3
|
||||||
|
0.9 -0.5 0.3
|
||||||
|
0.9 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.1 -0.64 0.3
|
||||||
|
0.1 -0.64 -0.3
|
||||||
|
0.1 -0.5 -0.3
|
||||||
|
0.1 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.9 -0.64 -0.3
|
||||||
|
-0.1 -0.64 -0.3
|
||||||
|
-0.1 -0.5 -0.3
|
||||||
|
-0.9 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.9 -0.64 -0.3
|
||||||
|
-0.9 -0.64 0.3
|
||||||
|
-0.1 -0.64 0.3
|
||||||
|
-0.1 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.1 -0.64 0.3
|
||||||
|
-0.9 -0.64 0.3
|
||||||
|
-0.9 -0.5 0.3
|
||||||
|
-0.1 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.1 -0.64 -0.3
|
||||||
|
-0.1 -0.64 0.3
|
||||||
|
-0.1 -0.5 0.3
|
||||||
|
-0.1 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.9 -0.64 0.3
|
||||||
|
-0.9 -0.64 -0.3
|
||||||
|
-0.9 -0.5 -0.3
|
||||||
|
-0.9 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------west quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
-1 0.5 -0.5
|
||||||
|
-1 0.5 0.5
|
||||||
|
-1 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------omni quads:
|
||||||
|
0
|
5573
bricks/gen/newbricks/Enabler 24 Bit.blb
Normal file
5573
bricks/gen/newbricks/Enabler 24 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
953
bricks/gen/newbricks/Enabler 3 Bit.blb
Normal file
953
bricks/gen/newbricks/Enabler 3 Bit.blb
Normal file
@ -0,0 +1,953 @@
|
|||||||
|
3 1 1
|
||||||
|
SPECIAL
|
||||||
|
|
||||||
|
bbb
|
||||||
|
|
||||||
|
1
|
||||||
|
|
||||||
|
0 0 0
|
||||||
|
3 1 1
|
||||||
|
COVERAGE:
|
||||||
|
1 : 3
|
||||||
|
1 : 3
|
||||||
|
1 : 3
|
||||||
|
1 : 1
|
||||||
|
1 : 3
|
||||||
|
1 : 1
|
||||||
|
----------------top quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:PRINT
|
||||||
|
POSITION:
|
||||||
|
1.5 0.5 0.5
|
||||||
|
1.5 -0.5 0.5
|
||||||
|
-1.5 -0.5 0.5
|
||||||
|
-1.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 0
|
||||||
|
1 1
|
||||||
|
0 1
|
||||||
|
0 0
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
----------------bottom quads:
|
||||||
|
4
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
2.5 0
|
||||||
|
2 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
2.5 0
|
||||||
|
2 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
----------------north quads:
|
||||||
|
16
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.5 0.5 0.5
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
1.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
0.99283854166667 -0.0859375
|
||||||
|
0.99283854166667 1.0859375
|
||||||
|
0.0071614583333333 1.0859375
|
||||||
|
0.0071614583333333 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.32 0.75 -0.24
|
||||||
|
0.68 0.75 -0.24
|
||||||
|
0.6 0.5 -0.3
|
||||||
|
1.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.32 0.75 -0.24
|
||||||
|
1.32 0.75 0.24
|
||||||
|
0.68 0.75 0.24
|
||||||
|
0.68 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.68 0.75 0.24
|
||||||
|
1.32 0.75 0.24
|
||||||
|
1.4 0.5 0.3
|
||||||
|
0.6 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.68 0.75 -0.24
|
||||||
|
0.68 0.75 0.24
|
||||||
|
0.6 0.5 0.3
|
||||||
|
0.6 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.32 0.75 0.24
|
||||||
|
1.32 0.75 -0.24
|
||||||
|
1.4 0.5 -0.3
|
||||||
|
1.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.4 0.5 0.3
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.68 0.75 -0.24
|
||||||
|
-1.32 0.75 -0.24
|
||||||
|
-1.4 0.5 -0.3
|
||||||
|
-0.6 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.68 0.75 -0.24
|
||||||
|
-0.68 0.75 0.24
|
||||||
|
-1.32 0.75 0.24
|
||||||
|
-1.32 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.32 0.75 0.24
|
||||||
|
-0.68 0.75 0.24
|
||||||
|
-0.6 0.5 0.3
|
||||||
|
-1.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.32 0.75 -0.24
|
||||||
|
-1.32 0.75 0.24
|
||||||
|
-1.4 0.5 0.3
|
||||||
|
-1.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.68 0.75 0.24
|
||||||
|
-0.68 0.75 -0.24
|
||||||
|
-0.6 0.5 -0.3
|
||||||
|
-0.6 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
----------------east quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.5 -0.5 0.5
|
||||||
|
1.5 0.5 0.5
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 -0.4 -0.3
|
||||||
|
1.64 0.4 -0.3
|
||||||
|
1.5 0.4 -0.3
|
||||||
|
1.5 -0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 -0.4 -0.3
|
||||||
|
1.64 -0.4 0.3
|
||||||
|
1.64 0.4 0.3
|
||||||
|
1.64 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 0.4 0.3
|
||||||
|
1.64 -0.4 0.3
|
||||||
|
1.5 -0.4 0.3
|
||||||
|
1.5 0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 0.4 -0.3
|
||||||
|
1.64 0.4 0.3
|
||||||
|
1.5 0.4 0.3
|
||||||
|
1.5 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 -0.4 0.3
|
||||||
|
1.64 -0.4 -0.3
|
||||||
|
1.5 -0.4 -0.3
|
||||||
|
1.5 -0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
----------------south quads:
|
||||||
|
16
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.5 -0.5 0.5
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
-1.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
0.99283854166667 -0.0859375
|
||||||
|
0.99283854166667 1.0859375
|
||||||
|
0.0071614583333333 1.0859375
|
||||||
|
0.0071614583333333 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.6 -0.64 -0.3
|
||||||
|
1.4 -0.64 -0.3
|
||||||
|
1.4 -0.5 -0.3
|
||||||
|
0.6 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.6 -0.64 -0.3
|
||||||
|
0.6 -0.64 0.3
|
||||||
|
1.4 -0.64 0.3
|
||||||
|
1.4 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.4 -0.64 0.3
|
||||||
|
0.6 -0.64 0.3
|
||||||
|
0.6 -0.5 0.3
|
||||||
|
1.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.4 -0.64 -0.3
|
||||||
|
1.4 -0.64 0.3
|
||||||
|
1.4 -0.5 0.3
|
||||||
|
1.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.6 -0.64 0.3
|
||||||
|
0.6 -0.64 -0.3
|
||||||
|
0.6 -0.5 -0.3
|
||||||
|
0.6 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.4 -0.64 -0.3
|
||||||
|
-0.6 -0.64 -0.3
|
||||||
|
-0.6 -0.5 -0.3
|
||||||
|
-1.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.4 -0.64 -0.3
|
||||||
|
-1.4 -0.64 0.3
|
||||||
|
-0.6 -0.64 0.3
|
||||||
|
-0.6 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.6 -0.64 0.3
|
||||||
|
-1.4 -0.64 0.3
|
||||||
|
-1.4 -0.5 0.3
|
||||||
|
-0.6 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.6 -0.64 -0.3
|
||||||
|
-0.6 -0.64 0.3
|
||||||
|
-0.6 -0.5 0.3
|
||||||
|
-0.6 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.4 -0.64 0.3
|
||||||
|
-1.4 -0.64 -0.3
|
||||||
|
-1.4 -0.5 -0.3
|
||||||
|
-1.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------west quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
-1.5 0.5 0.5
|
||||||
|
-1.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------omni quads:
|
||||||
|
0
|
7333
bricks/gen/newbricks/Enabler 32 Bit.blb
Normal file
7333
bricks/gen/newbricks/Enabler 32 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1173
bricks/gen/newbricks/Enabler 4 Bit.blb
Normal file
1173
bricks/gen/newbricks/Enabler 4 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
10853
bricks/gen/newbricks/Enabler 48 Bit.blb
Normal file
10853
bricks/gen/newbricks/Enabler 48 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1393
bricks/gen/newbricks/Enabler 5 Bit.blb
Normal file
1393
bricks/gen/newbricks/Enabler 5 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1613
bricks/gen/newbricks/Enabler 6 Bit.blb
Normal file
1613
bricks/gen/newbricks/Enabler 6 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
14373
bricks/gen/newbricks/Enabler 64 Bit.blb
Normal file
14373
bricks/gen/newbricks/Enabler 64 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1833
bricks/gen/newbricks/Enabler 7 Bit.blb
Normal file
1833
bricks/gen/newbricks/Enabler 7 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2053
bricks/gen/newbricks/Enabler 8 Bit.blb
Normal file
2053
bricks/gen/newbricks/Enabler 8 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2273
bricks/gen/newbricks/Enabler 9 Bit.blb
Normal file
2273
bricks/gen/newbricks/Enabler 9 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
513
bricks/gen/newbricks/Enabler Active Low 1 Bit.blb
Normal file
513
bricks/gen/newbricks/Enabler Active Low 1 Bit.blb
Normal file
@ -0,0 +1,513 @@
|
|||||||
|
1 1 1
|
||||||
|
SPECIAL
|
||||||
|
|
||||||
|
b
|
||||||
|
|
||||||
|
1
|
||||||
|
|
||||||
|
0 0 0
|
||||||
|
1 1 1
|
||||||
|
COVERAGE:
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
1 : 1
|
||||||
|
----------------top quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:PRINT
|
||||||
|
POSITION:
|
||||||
|
0.5 0.5 0.5
|
||||||
|
0.5 -0.5 0.5
|
||||||
|
-0.5 -0.5 0.5
|
||||||
|
-0.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 0
|
||||||
|
1 1
|
||||||
|
0 1
|
||||||
|
0 0
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
----------------bottom quads:
|
||||||
|
4
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
0 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
----------------north quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.5 0.5 0.5
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
0.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.4 0.5 0.3
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
----------------east quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.5 -0.5 0.5
|
||||||
|
0.5 0.5 0.5
|
||||||
|
0.5 0.5 -0.5
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 -0.4 -0.3
|
||||||
|
0.64 0.4 -0.3
|
||||||
|
0.5 0.4 -0.3
|
||||||
|
0.5 -0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 -0.4 -0.3
|
||||||
|
0.64 -0.4 0.3
|
||||||
|
0.64 0.4 0.3
|
||||||
|
0.64 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 0.4 0.3
|
||||||
|
0.64 -0.4 0.3
|
||||||
|
0.5 -0.4 0.3
|
||||||
|
0.5 0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 0.4 -0.3
|
||||||
|
0.64 0.4 0.3
|
||||||
|
0.5 0.4 0.3
|
||||||
|
0.5 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.64 -0.4 0.3
|
||||||
|
0.64 -0.4 -0.3
|
||||||
|
0.5 -0.4 -0.3
|
||||||
|
0.5 -0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
----------------south quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.5 -0.5 0.5
|
||||||
|
0.5 -0.5 -0.5
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
-0.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------west quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.5 -0.5 -0.5
|
||||||
|
-0.5 0.5 -0.5
|
||||||
|
-0.5 0.5 0.5
|
||||||
|
-0.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------omni quads:
|
||||||
|
0
|
2493
bricks/gen/newbricks/Enabler Active Low 10 Bit.blb
Normal file
2493
bricks/gen/newbricks/Enabler Active Low 10 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2713
bricks/gen/newbricks/Enabler Active Low 11 Bit.blb
Normal file
2713
bricks/gen/newbricks/Enabler Active Low 11 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2933
bricks/gen/newbricks/Enabler Active Low 12 Bit.blb
Normal file
2933
bricks/gen/newbricks/Enabler Active Low 12 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3153
bricks/gen/newbricks/Enabler Active Low 13 Bit.blb
Normal file
3153
bricks/gen/newbricks/Enabler Active Low 13 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3373
bricks/gen/newbricks/Enabler Active Low 14 Bit.blb
Normal file
3373
bricks/gen/newbricks/Enabler Active Low 14 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3593
bricks/gen/newbricks/Enabler Active Low 15 Bit.blb
Normal file
3593
bricks/gen/newbricks/Enabler Active Low 15 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3813
bricks/gen/newbricks/Enabler Active Low 16 Bit.blb
Normal file
3813
bricks/gen/newbricks/Enabler Active Low 16 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
733
bricks/gen/newbricks/Enabler Active Low 2 Bit.blb
Normal file
733
bricks/gen/newbricks/Enabler Active Low 2 Bit.blb
Normal file
@ -0,0 +1,733 @@
|
|||||||
|
2 1 1
|
||||||
|
SPECIAL
|
||||||
|
|
||||||
|
bb
|
||||||
|
|
||||||
|
1
|
||||||
|
|
||||||
|
0 0 0
|
||||||
|
2 1 1
|
||||||
|
COVERAGE:
|
||||||
|
1 : 2
|
||||||
|
1 : 2
|
||||||
|
1 : 2
|
||||||
|
1 : 1
|
||||||
|
1 : 2
|
||||||
|
1 : 1
|
||||||
|
----------------top quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:PRINT
|
||||||
|
POSITION:
|
||||||
|
1 0.5 0.5
|
||||||
|
1 -0.5 0.5
|
||||||
|
-1 -0.5 0.5
|
||||||
|
-1 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 0
|
||||||
|
1 1
|
||||||
|
0 1
|
||||||
|
0 0
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
----------------bottom quads:
|
||||||
|
4
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
1 -0.5 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
1.5 0
|
||||||
|
1 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1 0.5 -0.5
|
||||||
|
-1 0.5 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
1.5 0
|
||||||
|
1 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1 -0.5 -0.5
|
||||||
|
1 0.5 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1 0.5 -0.5
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
-0.5 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
----------------north quads:
|
||||||
|
11
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1 0.5 0.5
|
||||||
|
-1 0.5 -0.5
|
||||||
|
1 0.5 -0.5
|
||||||
|
1 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 -0.0859375
|
||||||
|
1 1.0859375
|
||||||
|
0 1.0859375
|
||||||
|
0 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.82 0.75 -0.24
|
||||||
|
0.18 0.75 -0.24
|
||||||
|
0.1 0.5 -0.3
|
||||||
|
0.9 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.82 0.75 -0.24
|
||||||
|
0.82 0.75 0.24
|
||||||
|
0.18 0.75 0.24
|
||||||
|
0.18 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.18 0.75 0.24
|
||||||
|
0.82 0.75 0.24
|
||||||
|
0.9 0.5 0.3
|
||||||
|
0.1 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.18 0.75 -0.24
|
||||||
|
0.18 0.75 0.24
|
||||||
|
0.1 0.5 0.3
|
||||||
|
0.1 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.82 0.75 0.24
|
||||||
|
0.82 0.75 -0.24
|
||||||
|
0.9 0.5 -0.3
|
||||||
|
0.9 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.18 0.75 -0.24
|
||||||
|
-0.82 0.75 -0.24
|
||||||
|
-0.9 0.5 -0.3
|
||||||
|
-0.1 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.18 0.75 -0.24
|
||||||
|
-0.18 0.75 0.24
|
||||||
|
-0.82 0.75 0.24
|
||||||
|
-0.82 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.82 0.75 0.24
|
||||||
|
-0.18 0.75 0.24
|
||||||
|
-0.1 0.5 0.3
|
||||||
|
-0.9 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.82 0.75 -0.24
|
||||||
|
-0.82 0.75 0.24
|
||||||
|
-0.9 0.5 0.3
|
||||||
|
-0.9 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.18 0.75 0.24
|
||||||
|
-0.18 0.75 -0.24
|
||||||
|
-0.1 0.5 -0.3
|
||||||
|
-0.1 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
----------------east quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1 -0.5 0.5
|
||||||
|
1 0.5 0.5
|
||||||
|
1 0.5 -0.5
|
||||||
|
1 -0.5 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 -0.4 -0.3
|
||||||
|
1.14 0.4 -0.3
|
||||||
|
1 0.4 -0.3
|
||||||
|
1 -0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 -0.4 -0.3
|
||||||
|
1.14 -0.4 0.3
|
||||||
|
1.14 0.4 0.3
|
||||||
|
1.14 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 0.4 0.3
|
||||||
|
1.14 -0.4 0.3
|
||||||
|
1 -0.4 0.3
|
||||||
|
1 0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 0.4 -0.3
|
||||||
|
1.14 0.4 0.3
|
||||||
|
1 0.4 0.3
|
||||||
|
1 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.14 -0.4 0.3
|
||||||
|
1.14 -0.4 -0.3
|
||||||
|
1 -0.4 -0.3
|
||||||
|
1 -0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
----------------south quads:
|
||||||
|
11
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1 -0.5 0.5
|
||||||
|
1 -0.5 -0.5
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
-1 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 -0.0859375
|
||||||
|
1 1.0859375
|
||||||
|
0 1.0859375
|
||||||
|
0 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.1 -0.64 -0.3
|
||||||
|
0.9 -0.64 -0.3
|
||||||
|
0.9 -0.5 -0.3
|
||||||
|
0.1 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.1 -0.64 -0.3
|
||||||
|
0.1 -0.64 0.3
|
||||||
|
0.9 -0.64 0.3
|
||||||
|
0.9 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.9 -0.64 0.3
|
||||||
|
0.1 -0.64 0.3
|
||||||
|
0.1 -0.5 0.3
|
||||||
|
0.9 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.9 -0.64 -0.3
|
||||||
|
0.9 -0.64 0.3
|
||||||
|
0.9 -0.5 0.3
|
||||||
|
0.9 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.1 -0.64 0.3
|
||||||
|
0.1 -0.64 -0.3
|
||||||
|
0.1 -0.5 -0.3
|
||||||
|
0.1 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.9 -0.64 -0.3
|
||||||
|
-0.1 -0.64 -0.3
|
||||||
|
-0.1 -0.5 -0.3
|
||||||
|
-0.9 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.9 -0.64 -0.3
|
||||||
|
-0.9 -0.64 0.3
|
||||||
|
-0.1 -0.64 0.3
|
||||||
|
-0.1 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.1 -0.64 0.3
|
||||||
|
-0.9 -0.64 0.3
|
||||||
|
-0.9 -0.5 0.3
|
||||||
|
-0.1 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.1 -0.64 -0.3
|
||||||
|
-0.1 -0.64 0.3
|
||||||
|
-0.1 -0.5 0.3
|
||||||
|
-0.1 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.9 -0.64 0.3
|
||||||
|
-0.9 -0.64 -0.3
|
||||||
|
-0.9 -0.5 -0.3
|
||||||
|
-0.9 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------west quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1 -0.5 -0.5
|
||||||
|
-1 0.5 -0.5
|
||||||
|
-1 0.5 0.5
|
||||||
|
-1 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------omni quads:
|
||||||
|
0
|
5573
bricks/gen/newbricks/Enabler Active Low 24 Bit.blb
Normal file
5573
bricks/gen/newbricks/Enabler Active Low 24 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
953
bricks/gen/newbricks/Enabler Active Low 3 Bit.blb
Normal file
953
bricks/gen/newbricks/Enabler Active Low 3 Bit.blb
Normal file
@ -0,0 +1,953 @@
|
|||||||
|
3 1 1
|
||||||
|
SPECIAL
|
||||||
|
|
||||||
|
bbb
|
||||||
|
|
||||||
|
1
|
||||||
|
|
||||||
|
0 0 0
|
||||||
|
3 1 1
|
||||||
|
COVERAGE:
|
||||||
|
1 : 3
|
||||||
|
1 : 3
|
||||||
|
1 : 3
|
||||||
|
1 : 1
|
||||||
|
1 : 3
|
||||||
|
1 : 1
|
||||||
|
----------------top quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:PRINT
|
||||||
|
POSITION:
|
||||||
|
1.5 0.5 0.5
|
||||||
|
1.5 -0.5 0.5
|
||||||
|
-1.5 -0.5 0.5
|
||||||
|
-1.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1 0
|
||||||
|
1 1
|
||||||
|
0 1
|
||||||
|
0 0
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
----------------bottom quads:
|
||||||
|
4
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
2.5 0
|
||||||
|
2 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
2.5 0
|
||||||
|
2 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:BOTTOMEDGE
|
||||||
|
POSITION:
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
-1 0 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.5 0
|
||||||
|
0.5 0
|
||||||
|
0 0.5
|
||||||
|
0 0.5
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
----------------north quads:
|
||||||
|
16
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.5 0.5 0.5
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
1.5 0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
0.99283854166667 -0.0859375
|
||||||
|
0.99283854166667 1.0859375
|
||||||
|
0.0071614583333333 1.0859375
|
||||||
|
0.0071614583333333 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.32 0.75 -0.24
|
||||||
|
0.68 0.75 -0.24
|
||||||
|
0.6 0.5 -0.3
|
||||||
|
1.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.32 0.75 -0.24
|
||||||
|
1.32 0.75 0.24
|
||||||
|
0.68 0.75 0.24
|
||||||
|
0.68 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.68 0.75 0.24
|
||||||
|
1.32 0.75 0.24
|
||||||
|
1.4 0.5 0.3
|
||||||
|
0.6 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.68 0.75 -0.24
|
||||||
|
0.68 0.75 0.24
|
||||||
|
0.6 0.5 0.3
|
||||||
|
0.6 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.32 0.75 0.24
|
||||||
|
1.32 0.75 -0.24
|
||||||
|
1.4 0.5 -0.3
|
||||||
|
1.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.4 0.5 0.3
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.32 0.75 -0.24
|
||||||
|
-0.32 0.75 0.24
|
||||||
|
-0.4 0.5 0.3
|
||||||
|
-0.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.32 0.75 0.24
|
||||||
|
0.32 0.75 -0.24
|
||||||
|
0.4 0.5 -0.3
|
||||||
|
0.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.68 0.75 -0.24
|
||||||
|
-1.32 0.75 -0.24
|
||||||
|
-1.4 0.5 -0.3
|
||||||
|
-0.6 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
-0 0.095561 -0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.68 0.75 -0.24
|
||||||
|
-0.68 0.75 0.24
|
||||||
|
-1.32 0.75 0.24
|
||||||
|
-1.32 0.75 -0.24
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.32 0.75 0.24
|
||||||
|
-0.68 0.75 0.24
|
||||||
|
-0.6 0.5 0.3
|
||||||
|
-1.4 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
-0 0.095561 0.995424
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.32 0.75 -0.24
|
||||||
|
-1.32 0.75 0.24
|
||||||
|
-1.4 0.5 0.3
|
||||||
|
-1.4 0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
-0.952424 0.304776 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.68 0.75 0.24
|
||||||
|
-0.68 0.75 -0.24
|
||||||
|
-0.6 0.5 -0.3
|
||||||
|
-0.6 0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
0.952424 0.304776 0
|
||||||
|
----------------east quads:
|
||||||
|
6
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.5 -0.5 0.5
|
||||||
|
1.5 0.5 0.5
|
||||||
|
1.5 0.5 -0.5
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
UV COORDS:
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 -0.4 -0.3
|
||||||
|
1.64 0.4 -0.3
|
||||||
|
1.5 0.4 -0.3
|
||||||
|
1.5 -0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 -0.4 -0.3
|
||||||
|
1.64 -0.4 0.3
|
||||||
|
1.64 0.4 0.3
|
||||||
|
1.64 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 0.4 0.3
|
||||||
|
1.64 -0.4 0.3
|
||||||
|
1.5 -0.4 0.3
|
||||||
|
1.5 0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 0.4 -0.3
|
||||||
|
1.64 0.4 0.3
|
||||||
|
1.5 0.4 0.3
|
||||||
|
1.5 0.4 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
0 1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.64 -0.4 0.3
|
||||||
|
1.64 -0.4 -0.3
|
||||||
|
1.5 -0.4 -0.3
|
||||||
|
1.5 -0.4 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
----------------south quads:
|
||||||
|
16
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.5 -0.5 0.5
|
||||||
|
1.5 -0.5 -0.5
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
-1.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
0.99283854166667 -0.0859375
|
||||||
|
0.99283854166667 1.0859375
|
||||||
|
0.0071614583333333 1.0859375
|
||||||
|
0.0071614583333333 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.6 -0.64 -0.3
|
||||||
|
1.4 -0.64 -0.3
|
||||||
|
1.4 -0.5 -0.3
|
||||||
|
0.6 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.6 -0.64 -0.3
|
||||||
|
0.6 -0.64 0.3
|
||||||
|
1.4 -0.64 0.3
|
||||||
|
1.4 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.4 -0.64 0.3
|
||||||
|
0.6 -0.64 0.3
|
||||||
|
0.6 -0.5 0.3
|
||||||
|
1.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
1.4 -0.64 -0.3
|
||||||
|
1.4 -0.64 0.3
|
||||||
|
1.4 -0.5 0.3
|
||||||
|
1.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.6 -0.64 0.3
|
||||||
|
0.6 -0.64 -0.3
|
||||||
|
0.6 -0.5 -0.3
|
||||||
|
0.6 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
0.4 -0.64 -0.3
|
||||||
|
0.4 -0.64 0.3
|
||||||
|
0.4 -0.5 0.3
|
||||||
|
0.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.4 -0.64 0.3
|
||||||
|
-0.4 -0.64 -0.3
|
||||||
|
-0.4 -0.5 -0.3
|
||||||
|
-0.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.4 -0.64 -0.3
|
||||||
|
-0.6 -0.64 -0.3
|
||||||
|
-0.6 -0.5 -0.3
|
||||||
|
-1.4 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
0 0 -1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.4 -0.64 -0.3
|
||||||
|
-1.4 -0.64 0.3
|
||||||
|
-0.6 -0.64 0.3
|
||||||
|
-0.6 -0.64 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
0 -1 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.6 -0.64 0.3
|
||||||
|
-1.4 -0.64 0.3
|
||||||
|
-1.4 -0.5 0.3
|
||||||
|
-0.6 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
0 0 1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-0.6 -0.64 -0.3
|
||||||
|
-0.6 -0.64 0.3
|
||||||
|
-0.6 -0.5 0.3
|
||||||
|
-0.6 -0.5 -0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
1 0 0
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.4 -0.64 0.3
|
||||||
|
-1.4 -0.64 -0.3
|
||||||
|
-1.4 -0.5 -0.3
|
||||||
|
-1.4 -0.5 0.3
|
||||||
|
UV COORDS:
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
0.5 0.5
|
||||||
|
COLORS:
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
1 1 1 1
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------west quads:
|
||||||
|
1
|
||||||
|
|
||||||
|
TEX:SIDE
|
||||||
|
POSITION:
|
||||||
|
-1.5 -0.5 -0.5
|
||||||
|
-1.5 0.5 -0.5
|
||||||
|
-1.5 0.5 0.5
|
||||||
|
-1.5 -0.5 0.5
|
||||||
|
UV COORDS:
|
||||||
|
1.021484375 1.0859375
|
||||||
|
-0.021484375 1.0859375
|
||||||
|
-0.021484375 -0.0859375
|
||||||
|
1.021484375 -0.0859375
|
||||||
|
NORMALS:
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
-1 0 0
|
||||||
|
----------------omni quads:
|
||||||
|
0
|
7333
bricks/gen/newbricks/Enabler Active Low 32 Bit.blb
Normal file
7333
bricks/gen/newbricks/Enabler Active Low 32 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1173
bricks/gen/newbricks/Enabler Active Low 4 Bit.blb
Normal file
1173
bricks/gen/newbricks/Enabler Active Low 4 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
10853
bricks/gen/newbricks/Enabler Active Low 48 Bit.blb
Normal file
10853
bricks/gen/newbricks/Enabler Active Low 48 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1393
bricks/gen/newbricks/Enabler Active Low 5 Bit.blb
Normal file
1393
bricks/gen/newbricks/Enabler Active Low 5 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1613
bricks/gen/newbricks/Enabler Active Low 6 Bit.blb
Normal file
1613
bricks/gen/newbricks/Enabler Active Low 6 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
14373
bricks/gen/newbricks/Enabler Active Low 64 Bit.blb
Normal file
14373
bricks/gen/newbricks/Enabler Active Low 64 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1833
bricks/gen/newbricks/Enabler Active Low 7 Bit.blb
Normal file
1833
bricks/gen/newbricks/Enabler Active Low 7 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2053
bricks/gen/newbricks/Enabler Active Low 8 Bit.blb
Normal file
2053
bricks/gen/newbricks/Enabler Active Low 8 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2273
bricks/gen/newbricks/Enabler Active Low 9 Bit.blb
Normal file
2273
bricks/gen/newbricks/Enabler Active Low 9 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
617
bricks/gen/newcode/Buffer 48 Bit.cs
Normal file
617
bricks/gen/newcode/Buffer 48 Bit.cs
Normal file
@ -0,0 +1,617 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Buffer48_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Buffer 48 Bit";
|
||||||
|
logicUIName = "Buffer 48 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "48 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[97].state then " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[48].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[49]:setstate(false) " @
|
||||||
|
" gate.ports[50]:setstate(false) " @
|
||||||
|
" gate.ports[51]:setstate(false) " @
|
||||||
|
" gate.ports[52]:setstate(false) " @
|
||||||
|
" gate.ports[53]:setstate(false) " @
|
||||||
|
" gate.ports[54]:setstate(false) " @
|
||||||
|
" gate.ports[55]:setstate(false) " @
|
||||||
|
" gate.ports[56]:setstate(false) " @
|
||||||
|
" gate.ports[57]:setstate(false) " @
|
||||||
|
" gate.ports[58]:setstate(false) " @
|
||||||
|
" gate.ports[59]:setstate(false) " @
|
||||||
|
" gate.ports[60]:setstate(false) " @
|
||||||
|
" gate.ports[61]:setstate(false) " @
|
||||||
|
" gate.ports[62]:setstate(false) " @
|
||||||
|
" gate.ports[63]:setstate(false) " @
|
||||||
|
" gate.ports[64]:setstate(false) " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 97;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "47 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "45 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "43 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "41 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "39 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "37 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "35 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "33 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "31 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "29 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "27 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "25 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "23 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "21 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "19 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "17 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-17 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-19 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-21 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-23 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-25 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-27 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-29 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-31 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-33 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-35 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-37 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-39 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-41 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-43 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-45 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-47 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "47 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "45 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "43 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "41 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "39 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "37 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "35 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "33 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "31 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "29 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "27 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "25 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "23 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "21 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "19 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "17 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "15 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "13 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "11 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "9 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "7 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "5 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "3 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "1 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-1 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-3 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-5 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-7 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-9 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-11 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-13 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-15 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-17 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-19 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-21 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-23 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-25 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-27 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-29 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-31 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-33 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-35 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-37 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-39 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-41 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-43 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-45 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-47 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "47 0 0";
|
||||||
|
logicPortDir[96] = 2;
|
||||||
|
logicPortUIName[96] = "Clock";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
};
|
809
bricks/gen/newcode/Buffer 64 Bit.cs
Normal file
809
bricks/gen/newcode/Buffer 64 Bit.cs
Normal file
@ -0,0 +1,809 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Buffer64_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 64 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 64 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Buffer 64 Bit";
|
||||||
|
logicUIName = "Buffer 64 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[129].state then " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[97]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[98]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[99]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[100]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[101]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[102]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[103]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[104]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[105]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[106]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[107]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[108]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[109]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[110]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[111]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[112]:setstate(gate.ports[48].state) " @
|
||||||
|
" gate.ports[113]:setstate(gate.ports[49].state) " @
|
||||||
|
" gate.ports[114]:setstate(gate.ports[50].state) " @
|
||||||
|
" gate.ports[115]:setstate(gate.ports[51].state) " @
|
||||||
|
" gate.ports[116]:setstate(gate.ports[52].state) " @
|
||||||
|
" gate.ports[117]:setstate(gate.ports[53].state) " @
|
||||||
|
" gate.ports[118]:setstate(gate.ports[54].state) " @
|
||||||
|
" gate.ports[119]:setstate(gate.ports[55].state) " @
|
||||||
|
" gate.ports[120]:setstate(gate.ports[56].state) " @
|
||||||
|
" gate.ports[121]:setstate(gate.ports[57].state) " @
|
||||||
|
" gate.ports[122]:setstate(gate.ports[58].state) " @
|
||||||
|
" gate.ports[123]:setstate(gate.ports[59].state) " @
|
||||||
|
" gate.ports[124]:setstate(gate.ports[60].state) " @
|
||||||
|
" gate.ports[125]:setstate(gate.ports[61].state) " @
|
||||||
|
" gate.ports[126]:setstate(gate.ports[62].state) " @
|
||||||
|
" gate.ports[127]:setstate(gate.ports[63].state) " @
|
||||||
|
" gate.ports[128]:setstate(gate.ports[64].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" gate.ports[97]:setstate(false) " @
|
||||||
|
" gate.ports[98]:setstate(false) " @
|
||||||
|
" gate.ports[99]:setstate(false) " @
|
||||||
|
" gate.ports[100]:setstate(false) " @
|
||||||
|
" gate.ports[101]:setstate(false) " @
|
||||||
|
" gate.ports[102]:setstate(false) " @
|
||||||
|
" gate.ports[103]:setstate(false) " @
|
||||||
|
" gate.ports[104]:setstate(false) " @
|
||||||
|
" gate.ports[105]:setstate(false) " @
|
||||||
|
" gate.ports[106]:setstate(false) " @
|
||||||
|
" gate.ports[107]:setstate(false) " @
|
||||||
|
" gate.ports[108]:setstate(false) " @
|
||||||
|
" gate.ports[109]:setstate(false) " @
|
||||||
|
" gate.ports[110]:setstate(false) " @
|
||||||
|
" gate.ports[111]:setstate(false) " @
|
||||||
|
" gate.ports[112]:setstate(false) " @
|
||||||
|
" gate.ports[113]:setstate(false) " @
|
||||||
|
" gate.ports[114]:setstate(false) " @
|
||||||
|
" gate.ports[115]:setstate(false) " @
|
||||||
|
" gate.ports[116]:setstate(false) " @
|
||||||
|
" gate.ports[117]:setstate(false) " @
|
||||||
|
" gate.ports[118]:setstate(false) " @
|
||||||
|
" gate.ports[119]:setstate(false) " @
|
||||||
|
" gate.ports[120]:setstate(false) " @
|
||||||
|
" gate.ports[121]:setstate(false) " @
|
||||||
|
" gate.ports[122]:setstate(false) " @
|
||||||
|
" gate.ports[123]:setstate(false) " @
|
||||||
|
" gate.ports[124]:setstate(false) " @
|
||||||
|
" gate.ports[125]:setstate(false) " @
|
||||||
|
" gate.ports[126]:setstate(false) " @
|
||||||
|
" gate.ports[127]:setstate(false) " @
|
||||||
|
" gate.ports[128]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 129;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 0 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "In48";
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 0 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "In49";
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 0 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "In50";
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 0 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "In51";
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 0 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "In52";
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 0 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "In53";
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 0 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "In54";
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 0 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "In55";
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 0 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "In56";
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 0 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "In57";
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 0 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "In58";
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 0 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "In59";
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 0 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "In60";
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 0 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "In61";
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 0 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "In62";
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 0 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "In63";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 0 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 0 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 0 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 0 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 0 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 0 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 0 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 0 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 0 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 0 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 0 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 0 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 0 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 0 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 0 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 0 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 0 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "Out48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 0 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "Out49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 0 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "Out50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 0 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "Out51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 0 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "Out52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 0 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "Out53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 0 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "Out54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 0 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "Out55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 0 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "Out56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 0 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "Out57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 0 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "Out58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 0 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "Out59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 0 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "Out60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 0 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "Out61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 0 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "Out62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 0 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "Out63";
|
||||||
|
|
||||||
|
logicPortType[128] = 1;
|
||||||
|
logicPortPos[128] = "63 0 0";
|
||||||
|
logicPortDir[128] = 2;
|
||||||
|
logicPortUIName[128] = "Clock";
|
||||||
|
logicPortCauseUpdate[128] = true;
|
||||||
|
|
||||||
|
};
|
617
bricks/gen/newcode/Buffer Active Low 48 Bit.cs
Normal file
617
bricks/gen/newcode/Buffer Active Low 48 Bit.cs
Normal file
@ -0,0 +1,617 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_BufferAl48_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 48 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 48 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Buffer Active Low 48 Bit";
|
||||||
|
logicUIName = "Buffer Active Low 48 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "48 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[97].state then " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[48].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[49]:setstate(false) " @
|
||||||
|
" gate.ports[50]:setstate(false) " @
|
||||||
|
" gate.ports[51]:setstate(false) " @
|
||||||
|
" gate.ports[52]:setstate(false) " @
|
||||||
|
" gate.ports[53]:setstate(false) " @
|
||||||
|
" gate.ports[54]:setstate(false) " @
|
||||||
|
" gate.ports[55]:setstate(false) " @
|
||||||
|
" gate.ports[56]:setstate(false) " @
|
||||||
|
" gate.ports[57]:setstate(false) " @
|
||||||
|
" gate.ports[58]:setstate(false) " @
|
||||||
|
" gate.ports[59]:setstate(false) " @
|
||||||
|
" gate.ports[60]:setstate(false) " @
|
||||||
|
" gate.ports[61]:setstate(false) " @
|
||||||
|
" gate.ports[62]:setstate(false) " @
|
||||||
|
" gate.ports[63]:setstate(false) " @
|
||||||
|
" gate.ports[64]:setstate(false) " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 97;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "47 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "45 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "43 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "41 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "39 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "37 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "35 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "33 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "31 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "29 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "27 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "25 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "23 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "21 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "19 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "17 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-17 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-19 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-21 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-23 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-25 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-27 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-29 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-31 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-33 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-35 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-37 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-39 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-41 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-43 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-45 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-47 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "47 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "45 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "43 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "41 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "39 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "37 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "35 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "33 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "31 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "29 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "27 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "25 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "23 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "21 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "19 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "17 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "15 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "13 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "11 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "9 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "7 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "5 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "3 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "1 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-1 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-3 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-5 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-7 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-9 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-11 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-13 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-15 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-17 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-19 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-21 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-23 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-25 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-27 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-29 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-31 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-33 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-35 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-37 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-39 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-41 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-43 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-45 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-47 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "47 0 0";
|
||||||
|
logicPortDir[96] = 2;
|
||||||
|
logicPortUIName[96] = "Clock";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
};
|
809
bricks/gen/newcode/Buffer Active Low 64 Bit.cs
Normal file
809
bricks/gen/newcode/Buffer Active Low 64 Bit.cs
Normal file
@ -0,0 +1,809 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_BufferAl64_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 64 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 64 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Buffer Active Low 64 Bit";
|
||||||
|
logicUIName = "Buffer Active Low 64 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[129].state then " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[97]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[98]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[99]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[100]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[101]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[102]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[103]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[104]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[105]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[106]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[107]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[108]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[109]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[110]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[111]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[112]:setstate(gate.ports[48].state) " @
|
||||||
|
" gate.ports[113]:setstate(gate.ports[49].state) " @
|
||||||
|
" gate.ports[114]:setstate(gate.ports[50].state) " @
|
||||||
|
" gate.ports[115]:setstate(gate.ports[51].state) " @
|
||||||
|
" gate.ports[116]:setstate(gate.ports[52].state) " @
|
||||||
|
" gate.ports[117]:setstate(gate.ports[53].state) " @
|
||||||
|
" gate.ports[118]:setstate(gate.ports[54].state) " @
|
||||||
|
" gate.ports[119]:setstate(gate.ports[55].state) " @
|
||||||
|
" gate.ports[120]:setstate(gate.ports[56].state) " @
|
||||||
|
" gate.ports[121]:setstate(gate.ports[57].state) " @
|
||||||
|
" gate.ports[122]:setstate(gate.ports[58].state) " @
|
||||||
|
" gate.ports[123]:setstate(gate.ports[59].state) " @
|
||||||
|
" gate.ports[124]:setstate(gate.ports[60].state) " @
|
||||||
|
" gate.ports[125]:setstate(gate.ports[61].state) " @
|
||||||
|
" gate.ports[126]:setstate(gate.ports[62].state) " @
|
||||||
|
" gate.ports[127]:setstate(gate.ports[63].state) " @
|
||||||
|
" gate.ports[128]:setstate(gate.ports[64].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" gate.ports[97]:setstate(false) " @
|
||||||
|
" gate.ports[98]:setstate(false) " @
|
||||||
|
" gate.ports[99]:setstate(false) " @
|
||||||
|
" gate.ports[100]:setstate(false) " @
|
||||||
|
" gate.ports[101]:setstate(false) " @
|
||||||
|
" gate.ports[102]:setstate(false) " @
|
||||||
|
" gate.ports[103]:setstate(false) " @
|
||||||
|
" gate.ports[104]:setstate(false) " @
|
||||||
|
" gate.ports[105]:setstate(false) " @
|
||||||
|
" gate.ports[106]:setstate(false) " @
|
||||||
|
" gate.ports[107]:setstate(false) " @
|
||||||
|
" gate.ports[108]:setstate(false) " @
|
||||||
|
" gate.ports[109]:setstate(false) " @
|
||||||
|
" gate.ports[110]:setstate(false) " @
|
||||||
|
" gate.ports[111]:setstate(false) " @
|
||||||
|
" gate.ports[112]:setstate(false) " @
|
||||||
|
" gate.ports[113]:setstate(false) " @
|
||||||
|
" gate.ports[114]:setstate(false) " @
|
||||||
|
" gate.ports[115]:setstate(false) " @
|
||||||
|
" gate.ports[116]:setstate(false) " @
|
||||||
|
" gate.ports[117]:setstate(false) " @
|
||||||
|
" gate.ports[118]:setstate(false) " @
|
||||||
|
" gate.ports[119]:setstate(false) " @
|
||||||
|
" gate.ports[120]:setstate(false) " @
|
||||||
|
" gate.ports[121]:setstate(false) " @
|
||||||
|
" gate.ports[122]:setstate(false) " @
|
||||||
|
" gate.ports[123]:setstate(false) " @
|
||||||
|
" gate.ports[124]:setstate(false) " @
|
||||||
|
" gate.ports[125]:setstate(false) " @
|
||||||
|
" gate.ports[126]:setstate(false) " @
|
||||||
|
" gate.ports[127]:setstate(false) " @
|
||||||
|
" gate.ports[128]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 129;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 0 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "In48";
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 0 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "In49";
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 0 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "In50";
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 0 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "In51";
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 0 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "In52";
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 0 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "In53";
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 0 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "In54";
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 0 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "In55";
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 0 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "In56";
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 0 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "In57";
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 0 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "In58";
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 0 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "In59";
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 0 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "In60";
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 0 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "In61";
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 0 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "In62";
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 0 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "In63";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 0 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 0 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 0 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 0 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 0 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 0 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 0 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 0 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 0 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 0 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 0 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 0 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 0 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 0 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 0 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 0 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 0 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "Out48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 0 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "Out49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 0 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "Out50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 0 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "Out51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 0 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "Out52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 0 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "Out53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 0 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "Out54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 0 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "Out55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 0 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "Out56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 0 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "Out57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 0 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "Out58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 0 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "Out59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 0 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "Out60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 0 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "Out61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 0 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "Out62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 0 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "Out63";
|
||||||
|
|
||||||
|
logicPortType[128] = 1;
|
||||||
|
logicPortPos[128] = "63 0 0";
|
||||||
|
logicPortDir[128] = 2;
|
||||||
|
logicPortUIName[128] = "Clock";
|
||||||
|
logicPortCauseUpdate[128] = true;
|
||||||
|
|
||||||
|
};
|
568
bricks/gen/newcode/D FlipFlop 48 Bit.cs
Normal file
568
bricks/gen/newcode/D FlipFlop 48 Bit.cs
Normal file
@ -0,0 +1,568 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_DFlipFlop48_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 48 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 48 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "D FlipFlop 48 Bit";
|
||||||
|
logicUIName = "D FlipFlop 48 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "48 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[97].state then " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[48].state) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 97;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "47 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "45 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "43 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "41 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "39 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "37 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "35 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "33 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "31 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "29 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "27 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "25 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "23 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "21 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "19 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "17 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-17 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-19 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-21 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-23 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-25 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-27 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-29 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-31 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-33 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-35 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-37 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-39 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-41 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-43 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-45 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-47 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "47 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "45 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "43 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "41 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "39 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "37 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "35 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "33 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "31 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "29 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "27 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "25 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "23 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "21 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "19 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "17 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "15 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "13 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "11 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "9 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "7 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "5 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "3 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "1 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-1 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-3 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-5 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-7 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-9 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-11 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-13 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-15 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-17 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-19 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-21 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-23 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-25 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-27 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-29 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-31 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-33 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-35 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-37 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-39 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-41 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-43 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-45 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-47 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "47 0 0";
|
||||||
|
logicPortDir[96] = 2;
|
||||||
|
logicPortUIName[96] = "Clock";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
};
|
744
bricks/gen/newcode/D FlipFlop 64 Bit.cs
Normal file
744
bricks/gen/newcode/D FlipFlop 64 Bit.cs
Normal file
@ -0,0 +1,744 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_DFlipFlop64_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 64 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 64 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "D FlipFlop 64 Bit";
|
||||||
|
logicUIName = "D FlipFlop 64 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[129].state then " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[97]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[98]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[99]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[100]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[101]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[102]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[103]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[104]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[105]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[106]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[107]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[108]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[109]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[110]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[111]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[112]:setstate(gate.ports[48].state) " @
|
||||||
|
" gate.ports[113]:setstate(gate.ports[49].state) " @
|
||||||
|
" gate.ports[114]:setstate(gate.ports[50].state) " @
|
||||||
|
" gate.ports[115]:setstate(gate.ports[51].state) " @
|
||||||
|
" gate.ports[116]:setstate(gate.ports[52].state) " @
|
||||||
|
" gate.ports[117]:setstate(gate.ports[53].state) " @
|
||||||
|
" gate.ports[118]:setstate(gate.ports[54].state) " @
|
||||||
|
" gate.ports[119]:setstate(gate.ports[55].state) " @
|
||||||
|
" gate.ports[120]:setstate(gate.ports[56].state) " @
|
||||||
|
" gate.ports[121]:setstate(gate.ports[57].state) " @
|
||||||
|
" gate.ports[122]:setstate(gate.ports[58].state) " @
|
||||||
|
" gate.ports[123]:setstate(gate.ports[59].state) " @
|
||||||
|
" gate.ports[124]:setstate(gate.ports[60].state) " @
|
||||||
|
" gate.ports[125]:setstate(gate.ports[61].state) " @
|
||||||
|
" gate.ports[126]:setstate(gate.ports[62].state) " @
|
||||||
|
" gate.ports[127]:setstate(gate.ports[63].state) " @
|
||||||
|
" gate.ports[128]:setstate(gate.ports[64].state) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 129;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 0 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "In48";
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 0 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "In49";
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 0 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "In50";
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 0 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "In51";
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 0 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "In52";
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 0 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "In53";
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 0 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "In54";
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 0 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "In55";
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 0 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "In56";
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 0 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "In57";
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 0 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "In58";
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 0 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "In59";
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 0 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "In60";
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 0 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "In61";
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 0 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "In62";
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 0 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "In63";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 0 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 0 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 0 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 0 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 0 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 0 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 0 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 0 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 0 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 0 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 0 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 0 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 0 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 0 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 0 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 0 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 0 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "Out48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 0 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "Out49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 0 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "Out50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 0 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "Out51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 0 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "Out52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 0 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "Out53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 0 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "Out54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 0 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "Out55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 0 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "Out56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 0 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "Out57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 0 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "Out58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 0 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "Out59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 0 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "Out60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 0 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "Out61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 0 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "Out62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 0 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "Out63";
|
||||||
|
|
||||||
|
logicPortType[128] = 1;
|
||||||
|
logicPortPos[128] = "63 0 0";
|
||||||
|
logicPortDir[128] = 2;
|
||||||
|
logicPortUIName[128] = "Clock";
|
||||||
|
logicPortCauseUpdate[128] = true;
|
||||||
|
|
||||||
|
};
|
568
bricks/gen/newcode/D FlipFlop Active Low 48 Bit.cs
Normal file
568
bricks/gen/newcode/D FlipFlop Active Low 48 Bit.cs
Normal file
@ -0,0 +1,568 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_DFlipFlopAl48_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 48 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 48 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "D FlipFlop Active Low 48 Bit";
|
||||||
|
logicUIName = "D FlipFlop Active Low 48 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "48 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[97].state then " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[48].state) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 97;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "47 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "45 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "43 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "41 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "39 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "37 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "35 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "33 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "31 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "29 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "27 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "25 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "23 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "21 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "19 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "17 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-17 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-19 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-21 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-23 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-25 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-27 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-29 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-31 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-33 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-35 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-37 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-39 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-41 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-43 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-45 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-47 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "47 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "45 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "43 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "41 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "39 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "37 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "35 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "33 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "31 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "29 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "27 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "25 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "23 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "21 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "19 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "17 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "15 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "13 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "11 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "9 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "7 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "5 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "3 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "1 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-1 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-3 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-5 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-7 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-9 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-11 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-13 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-15 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-17 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-19 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-21 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-23 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-25 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-27 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-29 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-31 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-33 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-35 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-37 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-39 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-41 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-43 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-45 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-47 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "47 0 0";
|
||||||
|
logicPortDir[96] = 2;
|
||||||
|
logicPortUIName[96] = "Clock";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
};
|
744
bricks/gen/newcode/D FlipFlop Active Low 64 Bit.cs
Normal file
744
bricks/gen/newcode/D FlipFlop Active Low 64 Bit.cs
Normal file
@ -0,0 +1,744 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_DFlipFlopAl64_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 64 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 64 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "D FlipFlop Active Low 64 Bit";
|
||||||
|
logicUIName = "D FlipFlop Active Low 64 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[129].state then " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[97]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[98]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[99]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[100]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[101]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[102]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[103]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[104]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[105]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[106]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[107]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[108]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[109]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[110]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[111]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[112]:setstate(gate.ports[48].state) " @
|
||||||
|
" gate.ports[113]:setstate(gate.ports[49].state) " @
|
||||||
|
" gate.ports[114]:setstate(gate.ports[50].state) " @
|
||||||
|
" gate.ports[115]:setstate(gate.ports[51].state) " @
|
||||||
|
" gate.ports[116]:setstate(gate.ports[52].state) " @
|
||||||
|
" gate.ports[117]:setstate(gate.ports[53].state) " @
|
||||||
|
" gate.ports[118]:setstate(gate.ports[54].state) " @
|
||||||
|
" gate.ports[119]:setstate(gate.ports[55].state) " @
|
||||||
|
" gate.ports[120]:setstate(gate.ports[56].state) " @
|
||||||
|
" gate.ports[121]:setstate(gate.ports[57].state) " @
|
||||||
|
" gate.ports[122]:setstate(gate.ports[58].state) " @
|
||||||
|
" gate.ports[123]:setstate(gate.ports[59].state) " @
|
||||||
|
" gate.ports[124]:setstate(gate.ports[60].state) " @
|
||||||
|
" gate.ports[125]:setstate(gate.ports[61].state) " @
|
||||||
|
" gate.ports[126]:setstate(gate.ports[62].state) " @
|
||||||
|
" gate.ports[127]:setstate(gate.ports[63].state) " @
|
||||||
|
" gate.ports[128]:setstate(gate.ports[64].state) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 129;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 0 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "In48";
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 0 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "In49";
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 0 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "In50";
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 0 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "In51";
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 0 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "In52";
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 0 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "In53";
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 0 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "In54";
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 0 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "In55";
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 0 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "In56";
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 0 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "In57";
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 0 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "In58";
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 0 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "In59";
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 0 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "In60";
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 0 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "In61";
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 0 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "In62";
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 0 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "In63";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 0 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 0 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 0 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 0 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 0 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 0 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 0 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 0 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 0 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 0 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 0 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 0 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 0 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 0 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 0 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 0 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 0 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "Out48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 0 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "Out49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 0 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "Out50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 0 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "Out51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 0 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "Out52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 0 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "Out53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 0 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "Out54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 0 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "Out55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 0 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "Out56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 0 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "Out57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 0 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "Out58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 0 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "Out59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 0 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "Out60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 0 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "Out61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 0 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "Out62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 0 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "Out63";
|
||||||
|
|
||||||
|
logicPortType[128] = 1;
|
||||||
|
logicPortPos[128] = "63 0 0";
|
||||||
|
logicPortDir[128] = 2;
|
||||||
|
logicPortUIName[128] = "Clock";
|
||||||
|
logicPortCauseUpdate[128] = true;
|
||||||
|
|
||||||
|
};
|
54
bricks/gen/newcode/Enabler 1 Bit.cs
Normal file
54
bricks/gen/newcode/Enabler 1 Bit.cs
Normal file
@ -0,0 +1,54 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler1_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 1 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 1 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 1 Bit";
|
||||||
|
logicUIName = "Enabler 1 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "1 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[3].state then " @
|
||||||
|
" gate.ports[2]:setstate(gate.ports[1].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[2]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 3;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "0 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 0;
|
||||||
|
logicPortPos[1] = "0 0 0";
|
||||||
|
logicPortDir[1] = 1;
|
||||||
|
logicPortUIName[1] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "0 0 0";
|
||||||
|
logicPortDir[2] = 2;
|
||||||
|
logicPortUIName[2] = "Clock";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
};
|
171
bricks/gen/newcode/Enabler 10 Bit.cs
Normal file
171
bricks/gen/newcode/Enabler 10 Bit.cs
Normal file
@ -0,0 +1,171 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler10_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 10 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 10 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 10 Bit";
|
||||||
|
logicUIName = "Enabler 10 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "10 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[21].state then " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[10].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 21;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "9 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "7 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "5 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "3 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "1 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-1 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-3 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-5 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-7 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-9 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "9 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "7 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "5 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "3 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "1 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-1 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "-3 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-5 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-7 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-9 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "9 0 0";
|
||||||
|
logicPortDir[20] = 2;
|
||||||
|
logicPortUIName[20] = "Clock";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
};
|
184
bricks/gen/newcode/Enabler 11 Bit.cs
Normal file
184
bricks/gen/newcode/Enabler 11 Bit.cs
Normal file
@ -0,0 +1,184 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler11_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 11 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 11 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 11 Bit";
|
||||||
|
logicUIName = "Enabler 11 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "11 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[23].state then " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[11].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 23;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "10 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "8 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "6 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "4 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "2 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "0 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-2 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-4 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-6 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-8 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-10 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "10 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "8 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "6 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "4 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "2 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "0 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-2 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-4 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-6 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-8 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-10 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "10 0 0";
|
||||||
|
logicPortDir[22] = 2;
|
||||||
|
logicPortUIName[22] = "Clock";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
};
|
197
bricks/gen/newcode/Enabler 12 Bit.cs
Normal file
197
bricks/gen/newcode/Enabler 12 Bit.cs
Normal file
@ -0,0 +1,197 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler12_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 12 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 12 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 12 Bit";
|
||||||
|
logicUIName = "Enabler 12 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "12 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[25].state then " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[12].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 25;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "11 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "9 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "7 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "5 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "3 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "1 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-1 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-3 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-5 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-7 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-9 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-11 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "11 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "9 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "7 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "5 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "3 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "1 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-1 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-3 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-5 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-7 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-9 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-11 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "11 0 0";
|
||||||
|
logicPortDir[24] = 2;
|
||||||
|
logicPortUIName[24] = "Clock";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
};
|
210
bricks/gen/newcode/Enabler 13 Bit.cs
Normal file
210
bricks/gen/newcode/Enabler 13 Bit.cs
Normal file
@ -0,0 +1,210 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler13_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 13 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 13 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 13 Bit";
|
||||||
|
logicUIName = "Enabler 13 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "13 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[27].state then " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[13].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 27;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "12 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "10 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "8 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "6 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "4 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "2 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "0 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-2 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-4 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-6 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-8 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-10 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-12 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "12 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "10 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "8 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "6 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "4 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "2 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "0 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-2 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-4 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-6 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-8 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-10 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-12 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "12 0 0";
|
||||||
|
logicPortDir[26] = 2;
|
||||||
|
logicPortUIName[26] = "Clock";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
};
|
223
bricks/gen/newcode/Enabler 14 Bit.cs
Normal file
223
bricks/gen/newcode/Enabler 14 Bit.cs
Normal file
@ -0,0 +1,223 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler14_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 14 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 14 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 14 Bit";
|
||||||
|
logicUIName = "Enabler 14 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "14 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[29].state then " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[14].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 29;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "13 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "11 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "9 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "7 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "5 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "3 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "1 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-1 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-3 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-5 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-7 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-9 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-11 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-13 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "13 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "11 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "9 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "7 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "5 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "3 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "1 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-1 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-3 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-5 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-7 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-9 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-11 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-13 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "13 0 0";
|
||||||
|
logicPortDir[28] = 2;
|
||||||
|
logicPortUIName[28] = "Clock";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
};
|
236
bricks/gen/newcode/Enabler 15 Bit.cs
Normal file
236
bricks/gen/newcode/Enabler 15 Bit.cs
Normal file
@ -0,0 +1,236 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler15_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 15 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 15 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 15 Bit";
|
||||||
|
logicUIName = "Enabler 15 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "15 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[31].state then " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[29]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[30]:setstate(gate.ports[15].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" gate.ports[29]:setstate(false) " @
|
||||||
|
" gate.ports[30]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 31;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "14 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "12 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "10 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "8 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "6 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "4 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "2 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "0 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-2 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-4 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-6 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-8 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-10 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-12 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-14 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "14 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "12 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "10 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "8 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "6 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "4 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "2 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "0 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-2 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-4 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-6 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-8 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-10 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-12 0 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-14 0 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "14 0 0";
|
||||||
|
logicPortDir[30] = 2;
|
||||||
|
logicPortUIName[30] = "Clock";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
};
|
249
bricks/gen/newcode/Enabler 16 Bit.cs
Normal file
249
bricks/gen/newcode/Enabler 16 Bit.cs
Normal file
@ -0,0 +1,249 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler16_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 16 Bit";
|
||||||
|
logicUIName = "Enabler 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[33].state then " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[29]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[30]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[31]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[32]:setstate(gate.ports[16].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" gate.ports[29]:setstate(false) " @
|
||||||
|
" gate.ports[30]:setstate(false) " @
|
||||||
|
" gate.ports[31]:setstate(false) " @
|
||||||
|
" gate.ports[32]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 33;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-1 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-3 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-5 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-7 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-9 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-11 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-13 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-15 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "15 0 0";
|
||||||
|
logicPortDir[32] = 2;
|
||||||
|
logicPortUIName[32] = "Clock";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
};
|
67
bricks/gen/newcode/Enabler 2 Bit.cs
Normal file
67
bricks/gen/newcode/Enabler 2 Bit.cs
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler2_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 2 Bit";
|
||||||
|
logicUIName = "Enabler 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "2 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[5].state then " @
|
||||||
|
" gate.ports[3]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[4]:setstate(gate.ports[2].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[3]:setstate(false) " @
|
||||||
|
" gate.ports[4]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 5;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "1 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "-1 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 0;
|
||||||
|
logicPortPos[2] = "1 0 0";
|
||||||
|
logicPortDir[2] = 1;
|
||||||
|
logicPortUIName[2] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "-1 0 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "1 0 0";
|
||||||
|
logicPortDir[4] = 2;
|
||||||
|
logicPortUIName[4] = "Clock";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
};
|
353
bricks/gen/newcode/Enabler 24 Bit.cs
Normal file
353
bricks/gen/newcode/Enabler 24 Bit.cs
Normal file
@ -0,0 +1,353 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler24_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 24 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 24 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 24 Bit";
|
||||||
|
logicUIName = "Enabler 24 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "24 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[49].state then " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[29]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[30]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[31]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[32]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[33]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[34]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[35]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[36]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[37]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[38]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[39]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[40]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[41]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[42]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[43]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[44]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[45]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[46]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[47]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[48]:setstate(gate.ports[24].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" gate.ports[29]:setstate(false) " @
|
||||||
|
" gate.ports[30]:setstate(false) " @
|
||||||
|
" gate.ports[31]:setstate(false) " @
|
||||||
|
" gate.ports[32]:setstate(false) " @
|
||||||
|
" gate.ports[33]:setstate(false) " @
|
||||||
|
" gate.ports[34]:setstate(false) " @
|
||||||
|
" gate.ports[35]:setstate(false) " @
|
||||||
|
" gate.ports[36]:setstate(false) " @
|
||||||
|
" gate.ports[37]:setstate(false) " @
|
||||||
|
" gate.ports[38]:setstate(false) " @
|
||||||
|
" gate.ports[39]:setstate(false) " @
|
||||||
|
" gate.ports[40]:setstate(false) " @
|
||||||
|
" gate.ports[41]:setstate(false) " @
|
||||||
|
" gate.ports[42]:setstate(false) " @
|
||||||
|
" gate.ports[43]:setstate(false) " @
|
||||||
|
" gate.ports[44]:setstate(false) " @
|
||||||
|
" gate.ports[45]:setstate(false) " @
|
||||||
|
" gate.ports[46]:setstate(false) " @
|
||||||
|
" gate.ports[47]:setstate(false) " @
|
||||||
|
" gate.ports[48]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 49;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "23 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "21 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "19 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "17 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "15 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "13 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "11 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "9 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "7 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "5 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "3 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "1 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-1 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-3 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-5 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-7 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-9 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-11 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-13 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-15 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-17 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-19 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-21 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-23 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "23 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "21 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "19 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "17 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "15 0 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "13 0 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "11 0 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "9 0 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "7 0 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "5 0 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "3 0 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "1 0 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "-1 0 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "-3 0 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "-5 0 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "-7 0 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "-9 0 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "-11 0 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "-13 0 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "-15 0 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "-17 0 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "-19 0 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "-21 0 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "-23 0 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "23 0 0";
|
||||||
|
logicPortDir[48] = 2;
|
||||||
|
logicPortUIName[48] = "Clock";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
};
|
80
bricks/gen/newcode/Enabler 3 Bit.cs
Normal file
80
bricks/gen/newcode/Enabler 3 Bit.cs
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler3_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 3 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 3 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 3 Bit";
|
||||||
|
logicUIName = "Enabler 3 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "3 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[7].state then " @
|
||||||
|
" gate.ports[4]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[5]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[6]:setstate(gate.ports[3].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[4]:setstate(false) " @
|
||||||
|
" gate.ports[5]:setstate(false) " @
|
||||||
|
" gate.ports[6]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 7;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "2 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "0 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-2 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "2 0 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "0 0 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "-2 0 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "2 0 0";
|
||||||
|
logicPortDir[6] = 2;
|
||||||
|
logicPortUIName[6] = "Clock";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
};
|
457
bricks/gen/newcode/Enabler 32 Bit.cs
Normal file
457
bricks/gen/newcode/Enabler 32 Bit.cs
Normal file
@ -0,0 +1,457 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler32_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 32 Bit";
|
||||||
|
logicUIName = "Enabler 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[65].state then " @
|
||||||
|
" gate.ports[33]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[34]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[35]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[36]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[37]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[38]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[39]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[40]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[41]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[42]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[43]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[44]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[45]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[46]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[47]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[48]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[32].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[33]:setstate(false) " @
|
||||||
|
" gate.ports[34]:setstate(false) " @
|
||||||
|
" gate.ports[35]:setstate(false) " @
|
||||||
|
" gate.ports[36]:setstate(false) " @
|
||||||
|
" gate.ports[37]:setstate(false) " @
|
||||||
|
" gate.ports[38]:setstate(false) " @
|
||||||
|
" gate.ports[39]:setstate(false) " @
|
||||||
|
" gate.ports[40]:setstate(false) " @
|
||||||
|
" gate.ports[41]:setstate(false) " @
|
||||||
|
" gate.ports[42]:setstate(false) " @
|
||||||
|
" gate.ports[43]:setstate(false) " @
|
||||||
|
" gate.ports[44]:setstate(false) " @
|
||||||
|
" gate.ports[45]:setstate(false) " @
|
||||||
|
" gate.ports[46]:setstate(false) " @
|
||||||
|
" gate.ports[47]:setstate(false) " @
|
||||||
|
" gate.ports[48]:setstate(false) " @
|
||||||
|
" gate.ports[49]:setstate(false) " @
|
||||||
|
" gate.ports[50]:setstate(false) " @
|
||||||
|
" gate.ports[51]:setstate(false) " @
|
||||||
|
" gate.ports[52]:setstate(false) " @
|
||||||
|
" gate.ports[53]:setstate(false) " @
|
||||||
|
" gate.ports[54]:setstate(false) " @
|
||||||
|
" gate.ports[55]:setstate(false) " @
|
||||||
|
" gate.ports[56]:setstate(false) " @
|
||||||
|
" gate.ports[57]:setstate(false) " @
|
||||||
|
" gate.ports[58]:setstate(false) " @
|
||||||
|
" gate.ports[59]:setstate(false) " @
|
||||||
|
" gate.ports[60]:setstate(false) " @
|
||||||
|
" gate.ports[61]:setstate(false) " @
|
||||||
|
" gate.ports[62]:setstate(false) " @
|
||||||
|
" gate.ports[63]:setstate(false) " @
|
||||||
|
" gate.ports[64]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 65;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-1 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-3 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-5 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-7 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-9 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-11 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-13 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-15 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-17 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-19 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-21 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-23 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-25 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-27 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-29 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-31 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "31 0 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "29 0 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "27 0 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "25 0 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "23 0 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "21 0 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "19 0 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "17 0 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "15 0 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "13 0 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "11 0 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "9 0 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "7 0 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "5 0 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "3 0 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "1 0 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "-1 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "-3 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "-5 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "-7 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "-9 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "-11 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "-13 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "-15 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "-17 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "-19 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "-21 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "-23 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "-25 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "-27 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "-29 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "-31 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[64] = 1;
|
||||||
|
logicPortPos[64] = "31 0 0";
|
||||||
|
logicPortDir[64] = 2;
|
||||||
|
logicPortUIName[64] = "Clock";
|
||||||
|
logicPortCauseUpdate[64] = true;
|
||||||
|
|
||||||
|
};
|
93
bricks/gen/newcode/Enabler 4 Bit.cs
Normal file
93
bricks/gen/newcode/Enabler 4 Bit.cs
Normal file
@ -0,0 +1,93 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler4_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 4 Bit";
|
||||||
|
logicUIName = "Enabler 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[9].state then " @
|
||||||
|
" gate.ports[5]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[6]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[7]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[4].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[5]:setstate(false) " @
|
||||||
|
" gate.ports[6]:setstate(false) " @
|
||||||
|
" gate.ports[7]:setstate(false) " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 9;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-1 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-3 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "3 0 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "1 0 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "-1 0 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "-3 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "3 0 0";
|
||||||
|
logicPortDir[8] = 2;
|
||||||
|
logicPortUIName[8] = "Clock";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
};
|
665
bricks/gen/newcode/Enabler 48 Bit.cs
Normal file
665
bricks/gen/newcode/Enabler 48 Bit.cs
Normal file
@ -0,0 +1,665 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler48_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 48 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 48 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 48 Bit";
|
||||||
|
logicUIName = "Enabler 48 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "48 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[97].state then " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[48].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[49]:setstate(false) " @
|
||||||
|
" gate.ports[50]:setstate(false) " @
|
||||||
|
" gate.ports[51]:setstate(false) " @
|
||||||
|
" gate.ports[52]:setstate(false) " @
|
||||||
|
" gate.ports[53]:setstate(false) " @
|
||||||
|
" gate.ports[54]:setstate(false) " @
|
||||||
|
" gate.ports[55]:setstate(false) " @
|
||||||
|
" gate.ports[56]:setstate(false) " @
|
||||||
|
" gate.ports[57]:setstate(false) " @
|
||||||
|
" gate.ports[58]:setstate(false) " @
|
||||||
|
" gate.ports[59]:setstate(false) " @
|
||||||
|
" gate.ports[60]:setstate(false) " @
|
||||||
|
" gate.ports[61]:setstate(false) " @
|
||||||
|
" gate.ports[62]:setstate(false) " @
|
||||||
|
" gate.ports[63]:setstate(false) " @
|
||||||
|
" gate.ports[64]:setstate(false) " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 97;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "47 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "45 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "43 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "41 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "39 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "37 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "35 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "33 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "31 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "29 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "27 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "25 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "23 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "21 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "19 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "17 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-17 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-19 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-21 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
logicPortCauseUpdate[34] = true;
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-23 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-25 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
logicPortCauseUpdate[36] = true;
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-27 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
logicPortCauseUpdate[37] = true;
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-29 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
logicPortCauseUpdate[38] = true;
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-31 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
logicPortCauseUpdate[39] = true;
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-33 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
logicPortCauseUpdate[40] = true;
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-35 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
logicPortCauseUpdate[41] = true;
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-37 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
logicPortCauseUpdate[42] = true;
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-39 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
logicPortCauseUpdate[43] = true;
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-41 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
logicPortCauseUpdate[44] = true;
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-43 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
logicPortCauseUpdate[45] = true;
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-45 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
logicPortCauseUpdate[46] = true;
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-47 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
logicPortCauseUpdate[47] = true;
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "47 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "45 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "43 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "41 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "39 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "37 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "35 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "33 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "31 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "29 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "27 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "25 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "23 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "21 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "19 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "17 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "15 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "13 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "11 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "9 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "7 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "5 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "3 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "1 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-1 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-3 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-5 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-7 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-9 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-11 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-13 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-15 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-17 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-19 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-21 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-23 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-25 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-27 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-29 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-31 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-33 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-35 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-37 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-39 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-41 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-43 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-45 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-47 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "47 0 0";
|
||||||
|
logicPortDir[96] = 2;
|
||||||
|
logicPortUIName[96] = "Clock";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
};
|
106
bricks/gen/newcode/Enabler 5 Bit.cs
Normal file
106
bricks/gen/newcode/Enabler 5 Bit.cs
Normal file
@ -0,0 +1,106 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler5_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 5 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 5 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 5 Bit";
|
||||||
|
logicUIName = "Enabler 5 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "5 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[11].state then " @
|
||||||
|
" gate.ports[6]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[7]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[5].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[6]:setstate(false) " @
|
||||||
|
" gate.ports[7]:setstate(false) " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 11;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "4 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "2 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "0 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-2 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-4 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "4 0 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "2 0 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "0 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "-2 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "-4 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "4 0 0";
|
||||||
|
logicPortDir[10] = 2;
|
||||||
|
logicPortUIName[10] = "Clock";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
};
|
119
bricks/gen/newcode/Enabler 6 Bit.cs
Normal file
119
bricks/gen/newcode/Enabler 6 Bit.cs
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler6_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 6 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 6 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 6 Bit";
|
||||||
|
logicUIName = "Enabler 6 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "6 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[13].state then " @
|
||||||
|
" gate.ports[7]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[6].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[7]:setstate(false) " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 13;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "5 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "3 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "1 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-1 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-3 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-5 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "5 0 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "3 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "1 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "-1 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "-3 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "-5 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "5 0 0";
|
||||||
|
logicPortDir[12] = 2;
|
||||||
|
logicPortUIName[12] = "Clock";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
};
|
873
bricks/gen/newcode/Enabler 64 Bit.cs
Normal file
873
bricks/gen/newcode/Enabler 64 Bit.cs
Normal file
@ -0,0 +1,873 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler64_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 64 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 64 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 64 Bit";
|
||||||
|
logicUIName = "Enabler 64 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[129].state then " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[97]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[98]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[99]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[100]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[101]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[102]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[103]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[104]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[105]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[106]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[107]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[108]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[109]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[110]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[111]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[112]:setstate(gate.ports[48].state) " @
|
||||||
|
" gate.ports[113]:setstate(gate.ports[49].state) " @
|
||||||
|
" gate.ports[114]:setstate(gate.ports[50].state) " @
|
||||||
|
" gate.ports[115]:setstate(gate.ports[51].state) " @
|
||||||
|
" gate.ports[116]:setstate(gate.ports[52].state) " @
|
||||||
|
" gate.ports[117]:setstate(gate.ports[53].state) " @
|
||||||
|
" gate.ports[118]:setstate(gate.ports[54].state) " @
|
||||||
|
" gate.ports[119]:setstate(gate.ports[55].state) " @
|
||||||
|
" gate.ports[120]:setstate(gate.ports[56].state) " @
|
||||||
|
" gate.ports[121]:setstate(gate.ports[57].state) " @
|
||||||
|
" gate.ports[122]:setstate(gate.ports[58].state) " @
|
||||||
|
" gate.ports[123]:setstate(gate.ports[59].state) " @
|
||||||
|
" gate.ports[124]:setstate(gate.ports[60].state) " @
|
||||||
|
" gate.ports[125]:setstate(gate.ports[61].state) " @
|
||||||
|
" gate.ports[126]:setstate(gate.ports[62].state) " @
|
||||||
|
" gate.ports[127]:setstate(gate.ports[63].state) " @
|
||||||
|
" gate.ports[128]:setstate(gate.ports[64].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" gate.ports[97]:setstate(false) " @
|
||||||
|
" gate.ports[98]:setstate(false) " @
|
||||||
|
" gate.ports[99]:setstate(false) " @
|
||||||
|
" gate.ports[100]:setstate(false) " @
|
||||||
|
" gate.ports[101]:setstate(false) " @
|
||||||
|
" gate.ports[102]:setstate(false) " @
|
||||||
|
" gate.ports[103]:setstate(false) " @
|
||||||
|
" gate.ports[104]:setstate(false) " @
|
||||||
|
" gate.ports[105]:setstate(false) " @
|
||||||
|
" gate.ports[106]:setstate(false) " @
|
||||||
|
" gate.ports[107]:setstate(false) " @
|
||||||
|
" gate.ports[108]:setstate(false) " @
|
||||||
|
" gate.ports[109]:setstate(false) " @
|
||||||
|
" gate.ports[110]:setstate(false) " @
|
||||||
|
" gate.ports[111]:setstate(false) " @
|
||||||
|
" gate.ports[112]:setstate(false) " @
|
||||||
|
" gate.ports[113]:setstate(false) " @
|
||||||
|
" gate.ports[114]:setstate(false) " @
|
||||||
|
" gate.ports[115]:setstate(false) " @
|
||||||
|
" gate.ports[116]:setstate(false) " @
|
||||||
|
" gate.ports[117]:setstate(false) " @
|
||||||
|
" gate.ports[118]:setstate(false) " @
|
||||||
|
" gate.ports[119]:setstate(false) " @
|
||||||
|
" gate.ports[120]:setstate(false) " @
|
||||||
|
" gate.ports[121]:setstate(false) " @
|
||||||
|
" gate.ports[122]:setstate(false) " @
|
||||||
|
" gate.ports[123]:setstate(false) " @
|
||||||
|
" gate.ports[124]:setstate(false) " @
|
||||||
|
" gate.ports[125]:setstate(false) " @
|
||||||
|
" gate.ports[126]:setstate(false) " @
|
||||||
|
" gate.ports[127]:setstate(false) " @
|
||||||
|
" gate.ports[128]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 129;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
logicPortCauseUpdate[34] = true;
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
logicPortCauseUpdate[36] = true;
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
logicPortCauseUpdate[37] = true;
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
logicPortCauseUpdate[38] = true;
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
logicPortCauseUpdate[39] = true;
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
logicPortCauseUpdate[40] = true;
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
logicPortCauseUpdate[41] = true;
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
logicPortCauseUpdate[42] = true;
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
logicPortCauseUpdate[43] = true;
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
logicPortCauseUpdate[44] = true;
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
logicPortCauseUpdate[45] = true;
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
logicPortCauseUpdate[46] = true;
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
logicPortCauseUpdate[47] = true;
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 0 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "In48";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 0 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "In49";
|
||||||
|
logicPortCauseUpdate[49] = true;
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 0 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "In50";
|
||||||
|
logicPortCauseUpdate[50] = true;
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 0 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "In51";
|
||||||
|
logicPortCauseUpdate[51] = true;
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 0 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "In52";
|
||||||
|
logicPortCauseUpdate[52] = true;
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 0 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "In53";
|
||||||
|
logicPortCauseUpdate[53] = true;
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 0 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "In54";
|
||||||
|
logicPortCauseUpdate[54] = true;
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 0 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "In55";
|
||||||
|
logicPortCauseUpdate[55] = true;
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 0 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "In56";
|
||||||
|
logicPortCauseUpdate[56] = true;
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 0 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "In57";
|
||||||
|
logicPortCauseUpdate[57] = true;
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 0 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "In58";
|
||||||
|
logicPortCauseUpdate[58] = true;
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 0 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "In59";
|
||||||
|
logicPortCauseUpdate[59] = true;
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 0 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "In60";
|
||||||
|
logicPortCauseUpdate[60] = true;
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 0 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "In61";
|
||||||
|
logicPortCauseUpdate[61] = true;
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 0 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "In62";
|
||||||
|
logicPortCauseUpdate[62] = true;
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 0 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "In63";
|
||||||
|
logicPortCauseUpdate[63] = true;
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 0 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 0 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 0 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 0 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 0 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 0 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 0 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 0 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 0 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 0 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 0 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 0 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 0 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 0 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 0 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 0 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 0 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "Out48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 0 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "Out49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 0 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "Out50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 0 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "Out51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 0 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "Out52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 0 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "Out53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 0 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "Out54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 0 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "Out55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 0 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "Out56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 0 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "Out57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 0 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "Out58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 0 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "Out59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 0 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "Out60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 0 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "Out61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 0 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "Out62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 0 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "Out63";
|
||||||
|
|
||||||
|
logicPortType[128] = 1;
|
||||||
|
logicPortPos[128] = "63 0 0";
|
||||||
|
logicPortDir[128] = 2;
|
||||||
|
logicPortUIName[128] = "Clock";
|
||||||
|
logicPortCauseUpdate[128] = true;
|
||||||
|
|
||||||
|
};
|
132
bricks/gen/newcode/Enabler 7 Bit.cs
Normal file
132
bricks/gen/newcode/Enabler 7 Bit.cs
Normal file
@ -0,0 +1,132 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler7_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 7 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 7 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 7 Bit";
|
||||||
|
logicUIName = "Enabler 7 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "7 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[15].state then " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[7].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 15;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "6 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "4 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "2 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "0 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-2 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-4 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-6 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "6 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "4 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "2 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "0 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "-2 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-4 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-6 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "6 0 0";
|
||||||
|
logicPortDir[14] = 2;
|
||||||
|
logicPortUIName[14] = "Clock";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
};
|
145
bricks/gen/newcode/Enabler 8 Bit.cs
Normal file
145
bricks/gen/newcode/Enabler 8 Bit.cs
Normal file
@ -0,0 +1,145 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler8_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 8 Bit";
|
||||||
|
logicUIName = "Enabler 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[17].state then " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[8].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 17;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-1 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-3 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-5 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-7 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "7 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "5 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "3 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "1 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-1 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-3 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-5 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-7 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "7 0 0";
|
||||||
|
logicPortDir[16] = 2;
|
||||||
|
logicPortUIName[16] = "Clock";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
};
|
158
bricks/gen/newcode/Enabler 9 Bit.cs
Normal file
158
bricks/gen/newcode/Enabler 9 Bit.cs
Normal file
@ -0,0 +1,158 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_Enabler9_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler 9 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler 9 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler 9 Bit";
|
||||||
|
logicUIName = "Enabler 9 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "9 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if gate.ports[19].state then " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[9].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 19;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "8 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "6 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "4 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "2 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "0 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-2 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-4 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-6 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-8 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "8 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "6 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "4 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "2 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "0 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-2 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-4 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "-6 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-8 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "8 0 0";
|
||||||
|
logicPortDir[18] = 2;
|
||||||
|
logicPortUIName[18] = "Clock";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
};
|
54
bricks/gen/newcode/Enabler Active Low 1 Bit.cs
Normal file
54
bricks/gen/newcode/Enabler Active Low 1 Bit.cs
Normal file
@ -0,0 +1,54 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl1_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 1 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 1 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 1 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 1 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "1 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[3].state then " @
|
||||||
|
" gate.ports[2]:setstate(gate.ports[1].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[2]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 3;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "0 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 0;
|
||||||
|
logicPortPos[1] = "0 0 0";
|
||||||
|
logicPortDir[1] = 1;
|
||||||
|
logicPortUIName[1] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "0 0 0";
|
||||||
|
logicPortDir[2] = 2;
|
||||||
|
logicPortUIName[2] = "Clock";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
};
|
171
bricks/gen/newcode/Enabler Active Low 10 Bit.cs
Normal file
171
bricks/gen/newcode/Enabler Active Low 10 Bit.cs
Normal file
@ -0,0 +1,171 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl10_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 10 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 10 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 10 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 10 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "10 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[21].state then " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[10].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 21;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "9 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "7 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "5 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "3 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "1 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-1 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-3 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-5 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-7 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-9 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "9 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "7 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "5 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "3 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "1 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-1 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "-3 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-5 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-7 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-9 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "9 0 0";
|
||||||
|
logicPortDir[20] = 2;
|
||||||
|
logicPortUIName[20] = "Clock";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
};
|
184
bricks/gen/newcode/Enabler Active Low 11 Bit.cs
Normal file
184
bricks/gen/newcode/Enabler Active Low 11 Bit.cs
Normal file
@ -0,0 +1,184 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl11_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 11 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 11 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 11 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 11 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "11 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[23].state then " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[11].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 23;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "10 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "8 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "6 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "4 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "2 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "0 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-2 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-4 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-6 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-8 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-10 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "10 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "8 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "6 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "4 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "2 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "0 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-2 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-4 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-6 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-8 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-10 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "10 0 0";
|
||||||
|
logicPortDir[22] = 2;
|
||||||
|
logicPortUIName[22] = "Clock";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
};
|
197
bricks/gen/newcode/Enabler Active Low 12 Bit.cs
Normal file
197
bricks/gen/newcode/Enabler Active Low 12 Bit.cs
Normal file
@ -0,0 +1,197 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl12_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 12 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 12 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 12 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 12 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "12 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[25].state then " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[12].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 25;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "11 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "9 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "7 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "5 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "3 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "1 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-1 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-3 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-5 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-7 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-9 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-11 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "11 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "9 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "7 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "5 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "3 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "1 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "-1 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "-3 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-5 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-7 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-9 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-11 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "11 0 0";
|
||||||
|
logicPortDir[24] = 2;
|
||||||
|
logicPortUIName[24] = "Clock";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
};
|
210
bricks/gen/newcode/Enabler Active Low 13 Bit.cs
Normal file
210
bricks/gen/newcode/Enabler Active Low 13 Bit.cs
Normal file
@ -0,0 +1,210 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl13_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 13 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 13 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 13 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 13 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "13 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[27].state then " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[13].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 27;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "12 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "10 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "8 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "6 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "4 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "2 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "0 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-2 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-4 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-6 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-8 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-10 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-12 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "12 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "10 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "8 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "6 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "4 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "2 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "0 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "-2 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-4 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-6 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-8 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-10 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-12 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "12 0 0";
|
||||||
|
logicPortDir[26] = 2;
|
||||||
|
logicPortUIName[26] = "Clock";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
};
|
223
bricks/gen/newcode/Enabler Active Low 14 Bit.cs
Normal file
223
bricks/gen/newcode/Enabler Active Low 14 Bit.cs
Normal file
@ -0,0 +1,223 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl14_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 14 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 14 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 14 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 14 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "14 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[29].state then " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[14].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 29;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "13 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "11 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "9 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "7 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "5 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "3 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "1 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-1 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-3 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-5 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-7 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-9 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-11 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-13 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "13 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "11 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "9 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "7 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "5 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "3 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "1 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "-1 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "-3 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-5 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-7 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-9 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-11 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-13 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "13 0 0";
|
||||||
|
logicPortDir[28] = 2;
|
||||||
|
logicPortUIName[28] = "Clock";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
};
|
236
bricks/gen/newcode/Enabler Active Low 15 Bit.cs
Normal file
236
bricks/gen/newcode/Enabler Active Low 15 Bit.cs
Normal file
@ -0,0 +1,236 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl15_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 15 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 15 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 15 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 15 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "15 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[31].state then " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[29]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[30]:setstate(gate.ports[15].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" gate.ports[29]:setstate(false) " @
|
||||||
|
" gate.ports[30]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 31;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "14 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "12 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "10 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "8 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "6 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "4 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "2 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "0 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-2 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-4 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-6 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-8 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-10 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-12 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-14 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "14 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "12 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "10 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "8 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "6 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "4 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "2 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "0 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "-2 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-4 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-6 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-8 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-10 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-12 0 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-14 0 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "14 0 0";
|
||||||
|
logicPortDir[30] = 2;
|
||||||
|
logicPortUIName[30] = "Clock";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
};
|
249
bricks/gen/newcode/Enabler Active Low 16 Bit.cs
Normal file
249
bricks/gen/newcode/Enabler Active Low 16 Bit.cs
Normal file
@ -0,0 +1,249 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl16_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 16 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 16 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 16 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 16 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "16 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[33].state then " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[19]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[20]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[21]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[22]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[23]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[24]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[29]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[30]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[31]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[32]:setstate(gate.ports[16].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" gate.ports[19]:setstate(false) " @
|
||||||
|
" gate.ports[20]:setstate(false) " @
|
||||||
|
" gate.ports[21]:setstate(false) " @
|
||||||
|
" gate.ports[22]:setstate(false) " @
|
||||||
|
" gate.ports[23]:setstate(false) " @
|
||||||
|
" gate.ports[24]:setstate(false) " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" gate.ports[29]:setstate(false) " @
|
||||||
|
" gate.ports[30]:setstate(false) " @
|
||||||
|
" gate.ports[31]:setstate(false) " @
|
||||||
|
" gate.ports[32]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 33;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "15 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "13 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "11 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "9 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "7 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "5 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "3 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "1 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-1 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "-3 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "-5 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "-7 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-9 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-11 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-13 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-15 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[18] = 0;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 1;
|
||||||
|
logicPortUIName[18] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[19] = 0;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 1;
|
||||||
|
logicPortUIName[19] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[20] = 0;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 1;
|
||||||
|
logicPortUIName[20] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[21] = 0;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 1;
|
||||||
|
logicPortUIName[21] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[22] = 0;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 1;
|
||||||
|
logicPortUIName[22] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[23] = 0;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 1;
|
||||||
|
logicPortUIName[23] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "15 0 0";
|
||||||
|
logicPortDir[32] = 2;
|
||||||
|
logicPortUIName[32] = "Clock";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
};
|
67
bricks/gen/newcode/Enabler Active Low 2 Bit.cs
Normal file
67
bricks/gen/newcode/Enabler Active Low 2 Bit.cs
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl2_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 2 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 2 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 2 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 2 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "2 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[5].state then " @
|
||||||
|
" gate.ports[3]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[4]:setstate(gate.ports[2].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[3]:setstate(false) " @
|
||||||
|
" gate.ports[4]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 5;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "1 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "-1 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 0;
|
||||||
|
logicPortPos[2] = "1 0 0";
|
||||||
|
logicPortDir[2] = 1;
|
||||||
|
logicPortUIName[2] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "-1 0 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "1 0 0";
|
||||||
|
logicPortDir[4] = 2;
|
||||||
|
logicPortUIName[4] = "Clock";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
};
|
353
bricks/gen/newcode/Enabler Active Low 24 Bit.cs
Normal file
353
bricks/gen/newcode/Enabler Active Low 24 Bit.cs
Normal file
@ -0,0 +1,353 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl24_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 24 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 24 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 24 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 24 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "24 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[49].state then " @
|
||||||
|
" gate.ports[25]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[26]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[27]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[28]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[29]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[30]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[31]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[32]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[33]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[34]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[35]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[36]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[37]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[38]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[39]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[40]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[41]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[42]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[43]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[44]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[45]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[46]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[47]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[48]:setstate(gate.ports[24].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[25]:setstate(false) " @
|
||||||
|
" gate.ports[26]:setstate(false) " @
|
||||||
|
" gate.ports[27]:setstate(false) " @
|
||||||
|
" gate.ports[28]:setstate(false) " @
|
||||||
|
" gate.ports[29]:setstate(false) " @
|
||||||
|
" gate.ports[30]:setstate(false) " @
|
||||||
|
" gate.ports[31]:setstate(false) " @
|
||||||
|
" gate.ports[32]:setstate(false) " @
|
||||||
|
" gate.ports[33]:setstate(false) " @
|
||||||
|
" gate.ports[34]:setstate(false) " @
|
||||||
|
" gate.ports[35]:setstate(false) " @
|
||||||
|
" gate.ports[36]:setstate(false) " @
|
||||||
|
" gate.ports[37]:setstate(false) " @
|
||||||
|
" gate.ports[38]:setstate(false) " @
|
||||||
|
" gate.ports[39]:setstate(false) " @
|
||||||
|
" gate.ports[40]:setstate(false) " @
|
||||||
|
" gate.ports[41]:setstate(false) " @
|
||||||
|
" gate.ports[42]:setstate(false) " @
|
||||||
|
" gate.ports[43]:setstate(false) " @
|
||||||
|
" gate.ports[44]:setstate(false) " @
|
||||||
|
" gate.ports[45]:setstate(false) " @
|
||||||
|
" gate.ports[46]:setstate(false) " @
|
||||||
|
" gate.ports[47]:setstate(false) " @
|
||||||
|
" gate.ports[48]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 49;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "23 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "21 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "19 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "17 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "15 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "13 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "11 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "9 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "7 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "5 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "3 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "1 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "-1 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "-3 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "-5 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "-7 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-9 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-11 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-13 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-15 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-17 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-19 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-21 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-23 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 0;
|
||||||
|
logicPortPos[24] = "23 0 0";
|
||||||
|
logicPortDir[24] = 1;
|
||||||
|
logicPortUIName[24] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[25] = 0;
|
||||||
|
logicPortPos[25] = "21 0 0";
|
||||||
|
logicPortDir[25] = 1;
|
||||||
|
logicPortUIName[25] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[26] = 0;
|
||||||
|
logicPortPos[26] = "19 0 0";
|
||||||
|
logicPortDir[26] = 1;
|
||||||
|
logicPortUIName[26] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[27] = 0;
|
||||||
|
logicPortPos[27] = "17 0 0";
|
||||||
|
logicPortDir[27] = 1;
|
||||||
|
logicPortUIName[27] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[28] = 0;
|
||||||
|
logicPortPos[28] = "15 0 0";
|
||||||
|
logicPortDir[28] = 1;
|
||||||
|
logicPortUIName[28] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[29] = 0;
|
||||||
|
logicPortPos[29] = "13 0 0";
|
||||||
|
logicPortDir[29] = 1;
|
||||||
|
logicPortUIName[29] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[30] = 0;
|
||||||
|
logicPortPos[30] = "11 0 0";
|
||||||
|
logicPortDir[30] = 1;
|
||||||
|
logicPortUIName[30] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[31] = 0;
|
||||||
|
logicPortPos[31] = "9 0 0";
|
||||||
|
logicPortDir[31] = 1;
|
||||||
|
logicPortUIName[31] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "7 0 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "5 0 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "3 0 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "1 0 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "-1 0 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "-3 0 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "-5 0 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "-7 0 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "-9 0 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "-11 0 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "-13 0 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "-15 0 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "-17 0 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "-19 0 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "-21 0 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "-23 0 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "23 0 0";
|
||||||
|
logicPortDir[48] = 2;
|
||||||
|
logicPortUIName[48] = "Clock";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
};
|
80
bricks/gen/newcode/Enabler Active Low 3 Bit.cs
Normal file
80
bricks/gen/newcode/Enabler Active Low 3 Bit.cs
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl3_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 3 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 3 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 3 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 3 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "3 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[7].state then " @
|
||||||
|
" gate.ports[4]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[5]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[6]:setstate(gate.ports[3].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[4]:setstate(false) " @
|
||||||
|
" gate.ports[5]:setstate(false) " @
|
||||||
|
" gate.ports[6]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 7;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "2 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "0 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-2 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 0;
|
||||||
|
logicPortPos[3] = "2 0 0";
|
||||||
|
logicPortDir[3] = 1;
|
||||||
|
logicPortUIName[3] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "0 0 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "-2 0 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "2 0 0";
|
||||||
|
logicPortDir[6] = 2;
|
||||||
|
logicPortUIName[6] = "Clock";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
};
|
457
bricks/gen/newcode/Enabler Active Low 32 Bit.cs
Normal file
457
bricks/gen/newcode/Enabler Active Low 32 Bit.cs
Normal file
@ -0,0 +1,457 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl32_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 32 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 32 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 32 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 32 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "32 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[65].state then " @
|
||||||
|
" gate.ports[33]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[34]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[35]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[36]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[37]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[38]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[39]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[40]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[41]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[42]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[43]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[44]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[45]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[46]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[47]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[48]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[32].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[33]:setstate(false) " @
|
||||||
|
" gate.ports[34]:setstate(false) " @
|
||||||
|
" gate.ports[35]:setstate(false) " @
|
||||||
|
" gate.ports[36]:setstate(false) " @
|
||||||
|
" gate.ports[37]:setstate(false) " @
|
||||||
|
" gate.ports[38]:setstate(false) " @
|
||||||
|
" gate.ports[39]:setstate(false) " @
|
||||||
|
" gate.ports[40]:setstate(false) " @
|
||||||
|
" gate.ports[41]:setstate(false) " @
|
||||||
|
" gate.ports[42]:setstate(false) " @
|
||||||
|
" gate.ports[43]:setstate(false) " @
|
||||||
|
" gate.ports[44]:setstate(false) " @
|
||||||
|
" gate.ports[45]:setstate(false) " @
|
||||||
|
" gate.ports[46]:setstate(false) " @
|
||||||
|
" gate.ports[47]:setstate(false) " @
|
||||||
|
" gate.ports[48]:setstate(false) " @
|
||||||
|
" gate.ports[49]:setstate(false) " @
|
||||||
|
" gate.ports[50]:setstate(false) " @
|
||||||
|
" gate.ports[51]:setstate(false) " @
|
||||||
|
" gate.ports[52]:setstate(false) " @
|
||||||
|
" gate.ports[53]:setstate(false) " @
|
||||||
|
" gate.ports[54]:setstate(false) " @
|
||||||
|
" gate.ports[55]:setstate(false) " @
|
||||||
|
" gate.ports[56]:setstate(false) " @
|
||||||
|
" gate.ports[57]:setstate(false) " @
|
||||||
|
" gate.ports[58]:setstate(false) " @
|
||||||
|
" gate.ports[59]:setstate(false) " @
|
||||||
|
" gate.ports[60]:setstate(false) " @
|
||||||
|
" gate.ports[61]:setstate(false) " @
|
||||||
|
" gate.ports[62]:setstate(false) " @
|
||||||
|
" gate.ports[63]:setstate(false) " @
|
||||||
|
" gate.ports[64]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 65;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "31 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "29 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "27 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "25 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "23 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "21 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "19 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "17 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "15 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "13 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "11 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "9 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "7 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "5 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "3 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "1 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "-1 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "-3 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "-5 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "-7 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "-9 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "-11 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "-13 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "-15 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-17 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-19 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-21 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-23 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-25 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-27 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-29 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-31 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 0;
|
||||||
|
logicPortPos[32] = "31 0 0";
|
||||||
|
logicPortDir[32] = 1;
|
||||||
|
logicPortUIName[32] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[33] = 0;
|
||||||
|
logicPortPos[33] = "29 0 0";
|
||||||
|
logicPortDir[33] = 1;
|
||||||
|
logicPortUIName[33] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[34] = 0;
|
||||||
|
logicPortPos[34] = "27 0 0";
|
||||||
|
logicPortDir[34] = 1;
|
||||||
|
logicPortUIName[34] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[35] = 0;
|
||||||
|
logicPortPos[35] = "25 0 0";
|
||||||
|
logicPortDir[35] = 1;
|
||||||
|
logicPortUIName[35] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[36] = 0;
|
||||||
|
logicPortPos[36] = "23 0 0";
|
||||||
|
logicPortDir[36] = 1;
|
||||||
|
logicPortUIName[36] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[37] = 0;
|
||||||
|
logicPortPos[37] = "21 0 0";
|
||||||
|
logicPortDir[37] = 1;
|
||||||
|
logicPortUIName[37] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[38] = 0;
|
||||||
|
logicPortPos[38] = "19 0 0";
|
||||||
|
logicPortDir[38] = 1;
|
||||||
|
logicPortUIName[38] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[39] = 0;
|
||||||
|
logicPortPos[39] = "17 0 0";
|
||||||
|
logicPortDir[39] = 1;
|
||||||
|
logicPortUIName[39] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[40] = 0;
|
||||||
|
logicPortPos[40] = "15 0 0";
|
||||||
|
logicPortDir[40] = 1;
|
||||||
|
logicPortUIName[40] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[41] = 0;
|
||||||
|
logicPortPos[41] = "13 0 0";
|
||||||
|
logicPortDir[41] = 1;
|
||||||
|
logicPortUIName[41] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[42] = 0;
|
||||||
|
logicPortPos[42] = "11 0 0";
|
||||||
|
logicPortDir[42] = 1;
|
||||||
|
logicPortUIName[42] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[43] = 0;
|
||||||
|
logicPortPos[43] = "9 0 0";
|
||||||
|
logicPortDir[43] = 1;
|
||||||
|
logicPortUIName[43] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[44] = 0;
|
||||||
|
logicPortPos[44] = "7 0 0";
|
||||||
|
logicPortDir[44] = 1;
|
||||||
|
logicPortUIName[44] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[45] = 0;
|
||||||
|
logicPortPos[45] = "5 0 0";
|
||||||
|
logicPortDir[45] = 1;
|
||||||
|
logicPortUIName[45] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[46] = 0;
|
||||||
|
logicPortPos[46] = "3 0 0";
|
||||||
|
logicPortDir[46] = 1;
|
||||||
|
logicPortUIName[46] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[47] = 0;
|
||||||
|
logicPortPos[47] = "1 0 0";
|
||||||
|
logicPortDir[47] = 1;
|
||||||
|
logicPortUIName[47] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "-1 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "-3 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "-5 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "-7 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "-9 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "-11 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "-13 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "-15 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "-17 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "-19 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "-21 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "-23 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "-25 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "-27 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "-29 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "-31 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[64] = 1;
|
||||||
|
logicPortPos[64] = "31 0 0";
|
||||||
|
logicPortDir[64] = 2;
|
||||||
|
logicPortUIName[64] = "Clock";
|
||||||
|
logicPortCauseUpdate[64] = true;
|
||||||
|
|
||||||
|
};
|
93
bricks/gen/newcode/Enabler Active Low 4 Bit.cs
Normal file
93
bricks/gen/newcode/Enabler Active Low 4 Bit.cs
Normal file
@ -0,0 +1,93 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl4_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 4 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 4 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 4 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 4 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "4 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[9].state then " @
|
||||||
|
" gate.ports[5]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[6]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[7]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[4].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[5]:setstate(false) " @
|
||||||
|
" gate.ports[6]:setstate(false) " @
|
||||||
|
" gate.ports[7]:setstate(false) " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 9;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "3 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "1 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "-1 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-3 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 0;
|
||||||
|
logicPortPos[4] = "3 0 0";
|
||||||
|
logicPortDir[4] = 1;
|
||||||
|
logicPortUIName[4] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "1 0 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "-1 0 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "-3 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "3 0 0";
|
||||||
|
logicPortDir[8] = 2;
|
||||||
|
logicPortUIName[8] = "Clock";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
};
|
665
bricks/gen/newcode/Enabler Active Low 48 Bit.cs
Normal file
665
bricks/gen/newcode/Enabler Active Low 48 Bit.cs
Normal file
@ -0,0 +1,665 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl48_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 48 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 48 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 48 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 48 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "48 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[97].state then " @
|
||||||
|
" gate.ports[49]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[50]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[51]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[52]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[53]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[54]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[55]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[56]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[57]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[58]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[59]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[60]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[61]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[62]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[63]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[64]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[48].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[49]:setstate(false) " @
|
||||||
|
" gate.ports[50]:setstate(false) " @
|
||||||
|
" gate.ports[51]:setstate(false) " @
|
||||||
|
" gate.ports[52]:setstate(false) " @
|
||||||
|
" gate.ports[53]:setstate(false) " @
|
||||||
|
" gate.ports[54]:setstate(false) " @
|
||||||
|
" gate.ports[55]:setstate(false) " @
|
||||||
|
" gate.ports[56]:setstate(false) " @
|
||||||
|
" gate.ports[57]:setstate(false) " @
|
||||||
|
" gate.ports[58]:setstate(false) " @
|
||||||
|
" gate.ports[59]:setstate(false) " @
|
||||||
|
" gate.ports[60]:setstate(false) " @
|
||||||
|
" gate.ports[61]:setstate(false) " @
|
||||||
|
" gate.ports[62]:setstate(false) " @
|
||||||
|
" gate.ports[63]:setstate(false) " @
|
||||||
|
" gate.ports[64]:setstate(false) " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 97;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "47 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "45 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "43 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "41 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "39 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "37 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "35 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "33 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "31 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "29 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "27 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "25 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "23 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "21 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "19 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "17 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "15 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "13 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "11 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "9 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "7 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "5 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "3 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "1 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "-1 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "-3 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "-5 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "-7 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "-9 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "-11 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "-13 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "-15 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-17 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-19 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-21 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
logicPortCauseUpdate[34] = true;
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-23 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-25 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
logicPortCauseUpdate[36] = true;
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-27 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
logicPortCauseUpdate[37] = true;
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-29 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
logicPortCauseUpdate[38] = true;
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-31 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
logicPortCauseUpdate[39] = true;
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-33 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
logicPortCauseUpdate[40] = true;
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-35 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
logicPortCauseUpdate[41] = true;
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-37 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
logicPortCauseUpdate[42] = true;
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-39 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
logicPortCauseUpdate[43] = true;
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-41 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
logicPortCauseUpdate[44] = true;
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-43 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
logicPortCauseUpdate[45] = true;
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-45 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
logicPortCauseUpdate[46] = true;
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-47 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
logicPortCauseUpdate[47] = true;
|
||||||
|
|
||||||
|
logicPortType[48] = 0;
|
||||||
|
logicPortPos[48] = "47 0 0";
|
||||||
|
logicPortDir[48] = 1;
|
||||||
|
logicPortUIName[48] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[49] = 0;
|
||||||
|
logicPortPos[49] = "45 0 0";
|
||||||
|
logicPortDir[49] = 1;
|
||||||
|
logicPortUIName[49] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[50] = 0;
|
||||||
|
logicPortPos[50] = "43 0 0";
|
||||||
|
logicPortDir[50] = 1;
|
||||||
|
logicPortUIName[50] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[51] = 0;
|
||||||
|
logicPortPos[51] = "41 0 0";
|
||||||
|
logicPortDir[51] = 1;
|
||||||
|
logicPortUIName[51] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[52] = 0;
|
||||||
|
logicPortPos[52] = "39 0 0";
|
||||||
|
logicPortDir[52] = 1;
|
||||||
|
logicPortUIName[52] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[53] = 0;
|
||||||
|
logicPortPos[53] = "37 0 0";
|
||||||
|
logicPortDir[53] = 1;
|
||||||
|
logicPortUIName[53] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[54] = 0;
|
||||||
|
logicPortPos[54] = "35 0 0";
|
||||||
|
logicPortDir[54] = 1;
|
||||||
|
logicPortUIName[54] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[55] = 0;
|
||||||
|
logicPortPos[55] = "33 0 0";
|
||||||
|
logicPortDir[55] = 1;
|
||||||
|
logicPortUIName[55] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[56] = 0;
|
||||||
|
logicPortPos[56] = "31 0 0";
|
||||||
|
logicPortDir[56] = 1;
|
||||||
|
logicPortUIName[56] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[57] = 0;
|
||||||
|
logicPortPos[57] = "29 0 0";
|
||||||
|
logicPortDir[57] = 1;
|
||||||
|
logicPortUIName[57] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[58] = 0;
|
||||||
|
logicPortPos[58] = "27 0 0";
|
||||||
|
logicPortDir[58] = 1;
|
||||||
|
logicPortUIName[58] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[59] = 0;
|
||||||
|
logicPortPos[59] = "25 0 0";
|
||||||
|
logicPortDir[59] = 1;
|
||||||
|
logicPortUIName[59] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[60] = 0;
|
||||||
|
logicPortPos[60] = "23 0 0";
|
||||||
|
logicPortDir[60] = 1;
|
||||||
|
logicPortUIName[60] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[61] = 0;
|
||||||
|
logicPortPos[61] = "21 0 0";
|
||||||
|
logicPortDir[61] = 1;
|
||||||
|
logicPortUIName[61] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[62] = 0;
|
||||||
|
logicPortPos[62] = "19 0 0";
|
||||||
|
logicPortDir[62] = 1;
|
||||||
|
logicPortUIName[62] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[63] = 0;
|
||||||
|
logicPortPos[63] = "17 0 0";
|
||||||
|
logicPortDir[63] = 1;
|
||||||
|
logicPortUIName[63] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "15 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "13 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "11 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "9 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "7 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "5 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "3 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "1 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "-1 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "-3 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "-5 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "-7 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "-9 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "-11 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "-13 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "-15 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "-17 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "-19 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "-21 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "-23 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "-25 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "-27 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "-29 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "-31 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "-33 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "-35 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "-37 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "-39 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "-41 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "-43 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "-45 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "-47 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[96] = 1;
|
||||||
|
logicPortPos[96] = "47 0 0";
|
||||||
|
logicPortDir[96] = 2;
|
||||||
|
logicPortUIName[96] = "Clock";
|
||||||
|
logicPortCauseUpdate[96] = true;
|
||||||
|
|
||||||
|
};
|
106
bricks/gen/newcode/Enabler Active Low 5 Bit.cs
Normal file
106
bricks/gen/newcode/Enabler Active Low 5 Bit.cs
Normal file
@ -0,0 +1,106 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl5_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 5 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 5 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 5 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 5 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "5 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[11].state then " @
|
||||||
|
" gate.ports[6]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[7]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[5].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[6]:setstate(false) " @
|
||||||
|
" gate.ports[7]:setstate(false) " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 11;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "4 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "2 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "0 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-2 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-4 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 0;
|
||||||
|
logicPortPos[5] = "4 0 0";
|
||||||
|
logicPortDir[5] = 1;
|
||||||
|
logicPortUIName[5] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "2 0 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "0 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "-2 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "-4 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "4 0 0";
|
||||||
|
logicPortDir[10] = 2;
|
||||||
|
logicPortUIName[10] = "Clock";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
};
|
119
bricks/gen/newcode/Enabler Active Low 6 Bit.cs
Normal file
119
bricks/gen/newcode/Enabler Active Low 6 Bit.cs
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl6_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 6 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 6 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 6 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 6 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "6 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[13].state then " @
|
||||||
|
" gate.ports[7]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[6].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[7]:setstate(false) " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 13;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "5 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "3 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "1 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "-1 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-3 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-5 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 0;
|
||||||
|
logicPortPos[6] = "5 0 0";
|
||||||
|
logicPortDir[6] = 1;
|
||||||
|
logicPortUIName[6] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "3 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "1 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "-1 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "-3 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "-5 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "5 0 0";
|
||||||
|
logicPortDir[12] = 2;
|
||||||
|
logicPortUIName[12] = "Clock";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
};
|
873
bricks/gen/newcode/Enabler Active Low 64 Bit.cs
Normal file
873
bricks/gen/newcode/Enabler Active Low 64 Bit.cs
Normal file
@ -0,0 +1,873 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl64_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 64 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 64 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 64 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 64 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "64 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[129].state then " @
|
||||||
|
" gate.ports[65]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[66]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[67]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[68]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[69]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[70]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[71]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[72]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[73]:setstate(gate.ports[9].state) " @
|
||||||
|
" gate.ports[74]:setstate(gate.ports[10].state) " @
|
||||||
|
" gate.ports[75]:setstate(gate.ports[11].state) " @
|
||||||
|
" gate.ports[76]:setstate(gate.ports[12].state) " @
|
||||||
|
" gate.ports[77]:setstate(gate.ports[13].state) " @
|
||||||
|
" gate.ports[78]:setstate(gate.ports[14].state) " @
|
||||||
|
" gate.ports[79]:setstate(gate.ports[15].state) " @
|
||||||
|
" gate.ports[80]:setstate(gate.ports[16].state) " @
|
||||||
|
" gate.ports[81]:setstate(gate.ports[17].state) " @
|
||||||
|
" gate.ports[82]:setstate(gate.ports[18].state) " @
|
||||||
|
" gate.ports[83]:setstate(gate.ports[19].state) " @
|
||||||
|
" gate.ports[84]:setstate(gate.ports[20].state) " @
|
||||||
|
" gate.ports[85]:setstate(gate.ports[21].state) " @
|
||||||
|
" gate.ports[86]:setstate(gate.ports[22].state) " @
|
||||||
|
" gate.ports[87]:setstate(gate.ports[23].state) " @
|
||||||
|
" gate.ports[88]:setstate(gate.ports[24].state) " @
|
||||||
|
" gate.ports[89]:setstate(gate.ports[25].state) " @
|
||||||
|
" gate.ports[90]:setstate(gate.ports[26].state) " @
|
||||||
|
" gate.ports[91]:setstate(gate.ports[27].state) " @
|
||||||
|
" gate.ports[92]:setstate(gate.ports[28].state) " @
|
||||||
|
" gate.ports[93]:setstate(gate.ports[29].state) " @
|
||||||
|
" gate.ports[94]:setstate(gate.ports[30].state) " @
|
||||||
|
" gate.ports[95]:setstate(gate.ports[31].state) " @
|
||||||
|
" gate.ports[96]:setstate(gate.ports[32].state) " @
|
||||||
|
" gate.ports[97]:setstate(gate.ports[33].state) " @
|
||||||
|
" gate.ports[98]:setstate(gate.ports[34].state) " @
|
||||||
|
" gate.ports[99]:setstate(gate.ports[35].state) " @
|
||||||
|
" gate.ports[100]:setstate(gate.ports[36].state) " @
|
||||||
|
" gate.ports[101]:setstate(gate.ports[37].state) " @
|
||||||
|
" gate.ports[102]:setstate(gate.ports[38].state) " @
|
||||||
|
" gate.ports[103]:setstate(gate.ports[39].state) " @
|
||||||
|
" gate.ports[104]:setstate(gate.ports[40].state) " @
|
||||||
|
" gate.ports[105]:setstate(gate.ports[41].state) " @
|
||||||
|
" gate.ports[106]:setstate(gate.ports[42].state) " @
|
||||||
|
" gate.ports[107]:setstate(gate.ports[43].state) " @
|
||||||
|
" gate.ports[108]:setstate(gate.ports[44].state) " @
|
||||||
|
" gate.ports[109]:setstate(gate.ports[45].state) " @
|
||||||
|
" gate.ports[110]:setstate(gate.ports[46].state) " @
|
||||||
|
" gate.ports[111]:setstate(gate.ports[47].state) " @
|
||||||
|
" gate.ports[112]:setstate(gate.ports[48].state) " @
|
||||||
|
" gate.ports[113]:setstate(gate.ports[49].state) " @
|
||||||
|
" gate.ports[114]:setstate(gate.ports[50].state) " @
|
||||||
|
" gate.ports[115]:setstate(gate.ports[51].state) " @
|
||||||
|
" gate.ports[116]:setstate(gate.ports[52].state) " @
|
||||||
|
" gate.ports[117]:setstate(gate.ports[53].state) " @
|
||||||
|
" gate.ports[118]:setstate(gate.ports[54].state) " @
|
||||||
|
" gate.ports[119]:setstate(gate.ports[55].state) " @
|
||||||
|
" gate.ports[120]:setstate(gate.ports[56].state) " @
|
||||||
|
" gate.ports[121]:setstate(gate.ports[57].state) " @
|
||||||
|
" gate.ports[122]:setstate(gate.ports[58].state) " @
|
||||||
|
" gate.ports[123]:setstate(gate.ports[59].state) " @
|
||||||
|
" gate.ports[124]:setstate(gate.ports[60].state) " @
|
||||||
|
" gate.ports[125]:setstate(gate.ports[61].state) " @
|
||||||
|
" gate.ports[126]:setstate(gate.ports[62].state) " @
|
||||||
|
" gate.ports[127]:setstate(gate.ports[63].state) " @
|
||||||
|
" gate.ports[128]:setstate(gate.ports[64].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[65]:setstate(false) " @
|
||||||
|
" gate.ports[66]:setstate(false) " @
|
||||||
|
" gate.ports[67]:setstate(false) " @
|
||||||
|
" gate.ports[68]:setstate(false) " @
|
||||||
|
" gate.ports[69]:setstate(false) " @
|
||||||
|
" gate.ports[70]:setstate(false) " @
|
||||||
|
" gate.ports[71]:setstate(false) " @
|
||||||
|
" gate.ports[72]:setstate(false) " @
|
||||||
|
" gate.ports[73]:setstate(false) " @
|
||||||
|
" gate.ports[74]:setstate(false) " @
|
||||||
|
" gate.ports[75]:setstate(false) " @
|
||||||
|
" gate.ports[76]:setstate(false) " @
|
||||||
|
" gate.ports[77]:setstate(false) " @
|
||||||
|
" gate.ports[78]:setstate(false) " @
|
||||||
|
" gate.ports[79]:setstate(false) " @
|
||||||
|
" gate.ports[80]:setstate(false) " @
|
||||||
|
" gate.ports[81]:setstate(false) " @
|
||||||
|
" gate.ports[82]:setstate(false) " @
|
||||||
|
" gate.ports[83]:setstate(false) " @
|
||||||
|
" gate.ports[84]:setstate(false) " @
|
||||||
|
" gate.ports[85]:setstate(false) " @
|
||||||
|
" gate.ports[86]:setstate(false) " @
|
||||||
|
" gate.ports[87]:setstate(false) " @
|
||||||
|
" gate.ports[88]:setstate(false) " @
|
||||||
|
" gate.ports[89]:setstate(false) " @
|
||||||
|
" gate.ports[90]:setstate(false) " @
|
||||||
|
" gate.ports[91]:setstate(false) " @
|
||||||
|
" gate.ports[92]:setstate(false) " @
|
||||||
|
" gate.ports[93]:setstate(false) " @
|
||||||
|
" gate.ports[94]:setstate(false) " @
|
||||||
|
" gate.ports[95]:setstate(false) " @
|
||||||
|
" gate.ports[96]:setstate(false) " @
|
||||||
|
" gate.ports[97]:setstate(false) " @
|
||||||
|
" gate.ports[98]:setstate(false) " @
|
||||||
|
" gate.ports[99]:setstate(false) " @
|
||||||
|
" gate.ports[100]:setstate(false) " @
|
||||||
|
" gate.ports[101]:setstate(false) " @
|
||||||
|
" gate.ports[102]:setstate(false) " @
|
||||||
|
" gate.ports[103]:setstate(false) " @
|
||||||
|
" gate.ports[104]:setstate(false) " @
|
||||||
|
" gate.ports[105]:setstate(false) " @
|
||||||
|
" gate.ports[106]:setstate(false) " @
|
||||||
|
" gate.ports[107]:setstate(false) " @
|
||||||
|
" gate.ports[108]:setstate(false) " @
|
||||||
|
" gate.ports[109]:setstate(false) " @
|
||||||
|
" gate.ports[110]:setstate(false) " @
|
||||||
|
" gate.ports[111]:setstate(false) " @
|
||||||
|
" gate.ports[112]:setstate(false) " @
|
||||||
|
" gate.ports[113]:setstate(false) " @
|
||||||
|
" gate.ports[114]:setstate(false) " @
|
||||||
|
" gate.ports[115]:setstate(false) " @
|
||||||
|
" gate.ports[116]:setstate(false) " @
|
||||||
|
" gate.ports[117]:setstate(false) " @
|
||||||
|
" gate.ports[118]:setstate(false) " @
|
||||||
|
" gate.ports[119]:setstate(false) " @
|
||||||
|
" gate.ports[120]:setstate(false) " @
|
||||||
|
" gate.ports[121]:setstate(false) " @
|
||||||
|
" gate.ports[122]:setstate(false) " @
|
||||||
|
" gate.ports[123]:setstate(false) " @
|
||||||
|
" gate.ports[124]:setstate(false) " @
|
||||||
|
" gate.ports[125]:setstate(false) " @
|
||||||
|
" gate.ports[126]:setstate(false) " @
|
||||||
|
" gate.ports[127]:setstate(false) " @
|
||||||
|
" gate.ports[128]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 129;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "63 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "61 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "59 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "57 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "55 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "53 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "51 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "49 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "47 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 1;
|
||||||
|
logicPortPos[9] = "45 0 0";
|
||||||
|
logicPortDir[9] = 3;
|
||||||
|
logicPortUIName[9] = "In9";
|
||||||
|
logicPortCauseUpdate[9] = true;
|
||||||
|
|
||||||
|
logicPortType[10] = 1;
|
||||||
|
logicPortPos[10] = "43 0 0";
|
||||||
|
logicPortDir[10] = 3;
|
||||||
|
logicPortUIName[10] = "In10";
|
||||||
|
logicPortCauseUpdate[10] = true;
|
||||||
|
|
||||||
|
logicPortType[11] = 1;
|
||||||
|
logicPortPos[11] = "41 0 0";
|
||||||
|
logicPortDir[11] = 3;
|
||||||
|
logicPortUIName[11] = "In11";
|
||||||
|
logicPortCauseUpdate[11] = true;
|
||||||
|
|
||||||
|
logicPortType[12] = 1;
|
||||||
|
logicPortPos[12] = "39 0 0";
|
||||||
|
logicPortDir[12] = 3;
|
||||||
|
logicPortUIName[12] = "In12";
|
||||||
|
logicPortCauseUpdate[12] = true;
|
||||||
|
|
||||||
|
logicPortType[13] = 1;
|
||||||
|
logicPortPos[13] = "37 0 0";
|
||||||
|
logicPortDir[13] = 3;
|
||||||
|
logicPortUIName[13] = "In13";
|
||||||
|
logicPortCauseUpdate[13] = true;
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "35 0 0";
|
||||||
|
logicPortDir[14] = 3;
|
||||||
|
logicPortUIName[14] = "In14";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
logicPortType[15] = 1;
|
||||||
|
logicPortPos[15] = "33 0 0";
|
||||||
|
logicPortDir[15] = 3;
|
||||||
|
logicPortUIName[15] = "In15";
|
||||||
|
logicPortCauseUpdate[15] = true;
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "31 0 0";
|
||||||
|
logicPortDir[16] = 3;
|
||||||
|
logicPortUIName[16] = "In16";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
logicPortType[17] = 1;
|
||||||
|
logicPortPos[17] = "29 0 0";
|
||||||
|
logicPortDir[17] = 3;
|
||||||
|
logicPortUIName[17] = "In17";
|
||||||
|
logicPortCauseUpdate[17] = true;
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "27 0 0";
|
||||||
|
logicPortDir[18] = 3;
|
||||||
|
logicPortUIName[18] = "In18";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
logicPortType[19] = 1;
|
||||||
|
logicPortPos[19] = "25 0 0";
|
||||||
|
logicPortDir[19] = 3;
|
||||||
|
logicPortUIName[19] = "In19";
|
||||||
|
logicPortCauseUpdate[19] = true;
|
||||||
|
|
||||||
|
logicPortType[20] = 1;
|
||||||
|
logicPortPos[20] = "23 0 0";
|
||||||
|
logicPortDir[20] = 3;
|
||||||
|
logicPortUIName[20] = "In20";
|
||||||
|
logicPortCauseUpdate[20] = true;
|
||||||
|
|
||||||
|
logicPortType[21] = 1;
|
||||||
|
logicPortPos[21] = "21 0 0";
|
||||||
|
logicPortDir[21] = 3;
|
||||||
|
logicPortUIName[21] = "In21";
|
||||||
|
logicPortCauseUpdate[21] = true;
|
||||||
|
|
||||||
|
logicPortType[22] = 1;
|
||||||
|
logicPortPos[22] = "19 0 0";
|
||||||
|
logicPortDir[22] = 3;
|
||||||
|
logicPortUIName[22] = "In22";
|
||||||
|
logicPortCauseUpdate[22] = true;
|
||||||
|
|
||||||
|
logicPortType[23] = 1;
|
||||||
|
logicPortPos[23] = "17 0 0";
|
||||||
|
logicPortDir[23] = 3;
|
||||||
|
logicPortUIName[23] = "In23";
|
||||||
|
logicPortCauseUpdate[23] = true;
|
||||||
|
|
||||||
|
logicPortType[24] = 1;
|
||||||
|
logicPortPos[24] = "15 0 0";
|
||||||
|
logicPortDir[24] = 3;
|
||||||
|
logicPortUIName[24] = "In24";
|
||||||
|
logicPortCauseUpdate[24] = true;
|
||||||
|
|
||||||
|
logicPortType[25] = 1;
|
||||||
|
logicPortPos[25] = "13 0 0";
|
||||||
|
logicPortDir[25] = 3;
|
||||||
|
logicPortUIName[25] = "In25";
|
||||||
|
logicPortCauseUpdate[25] = true;
|
||||||
|
|
||||||
|
logicPortType[26] = 1;
|
||||||
|
logicPortPos[26] = "11 0 0";
|
||||||
|
logicPortDir[26] = 3;
|
||||||
|
logicPortUIName[26] = "In26";
|
||||||
|
logicPortCauseUpdate[26] = true;
|
||||||
|
|
||||||
|
logicPortType[27] = 1;
|
||||||
|
logicPortPos[27] = "9 0 0";
|
||||||
|
logicPortDir[27] = 3;
|
||||||
|
logicPortUIName[27] = "In27";
|
||||||
|
logicPortCauseUpdate[27] = true;
|
||||||
|
|
||||||
|
logicPortType[28] = 1;
|
||||||
|
logicPortPos[28] = "7 0 0";
|
||||||
|
logicPortDir[28] = 3;
|
||||||
|
logicPortUIName[28] = "In28";
|
||||||
|
logicPortCauseUpdate[28] = true;
|
||||||
|
|
||||||
|
logicPortType[29] = 1;
|
||||||
|
logicPortPos[29] = "5 0 0";
|
||||||
|
logicPortDir[29] = 3;
|
||||||
|
logicPortUIName[29] = "In29";
|
||||||
|
logicPortCauseUpdate[29] = true;
|
||||||
|
|
||||||
|
logicPortType[30] = 1;
|
||||||
|
logicPortPos[30] = "3 0 0";
|
||||||
|
logicPortDir[30] = 3;
|
||||||
|
logicPortUIName[30] = "In30";
|
||||||
|
logicPortCauseUpdate[30] = true;
|
||||||
|
|
||||||
|
logicPortType[31] = 1;
|
||||||
|
logicPortPos[31] = "1 0 0";
|
||||||
|
logicPortDir[31] = 3;
|
||||||
|
logicPortUIName[31] = "In31";
|
||||||
|
logicPortCauseUpdate[31] = true;
|
||||||
|
|
||||||
|
logicPortType[32] = 1;
|
||||||
|
logicPortPos[32] = "-1 0 0";
|
||||||
|
logicPortDir[32] = 3;
|
||||||
|
logicPortUIName[32] = "In32";
|
||||||
|
logicPortCauseUpdate[32] = true;
|
||||||
|
|
||||||
|
logicPortType[33] = 1;
|
||||||
|
logicPortPos[33] = "-3 0 0";
|
||||||
|
logicPortDir[33] = 3;
|
||||||
|
logicPortUIName[33] = "In33";
|
||||||
|
logicPortCauseUpdate[33] = true;
|
||||||
|
|
||||||
|
logicPortType[34] = 1;
|
||||||
|
logicPortPos[34] = "-5 0 0";
|
||||||
|
logicPortDir[34] = 3;
|
||||||
|
logicPortUIName[34] = "In34";
|
||||||
|
logicPortCauseUpdate[34] = true;
|
||||||
|
|
||||||
|
logicPortType[35] = 1;
|
||||||
|
logicPortPos[35] = "-7 0 0";
|
||||||
|
logicPortDir[35] = 3;
|
||||||
|
logicPortUIName[35] = "In35";
|
||||||
|
logicPortCauseUpdate[35] = true;
|
||||||
|
|
||||||
|
logicPortType[36] = 1;
|
||||||
|
logicPortPos[36] = "-9 0 0";
|
||||||
|
logicPortDir[36] = 3;
|
||||||
|
logicPortUIName[36] = "In36";
|
||||||
|
logicPortCauseUpdate[36] = true;
|
||||||
|
|
||||||
|
logicPortType[37] = 1;
|
||||||
|
logicPortPos[37] = "-11 0 0";
|
||||||
|
logicPortDir[37] = 3;
|
||||||
|
logicPortUIName[37] = "In37";
|
||||||
|
logicPortCauseUpdate[37] = true;
|
||||||
|
|
||||||
|
logicPortType[38] = 1;
|
||||||
|
logicPortPos[38] = "-13 0 0";
|
||||||
|
logicPortDir[38] = 3;
|
||||||
|
logicPortUIName[38] = "In38";
|
||||||
|
logicPortCauseUpdate[38] = true;
|
||||||
|
|
||||||
|
logicPortType[39] = 1;
|
||||||
|
logicPortPos[39] = "-15 0 0";
|
||||||
|
logicPortDir[39] = 3;
|
||||||
|
logicPortUIName[39] = "In39";
|
||||||
|
logicPortCauseUpdate[39] = true;
|
||||||
|
|
||||||
|
logicPortType[40] = 1;
|
||||||
|
logicPortPos[40] = "-17 0 0";
|
||||||
|
logicPortDir[40] = 3;
|
||||||
|
logicPortUIName[40] = "In40";
|
||||||
|
logicPortCauseUpdate[40] = true;
|
||||||
|
|
||||||
|
logicPortType[41] = 1;
|
||||||
|
logicPortPos[41] = "-19 0 0";
|
||||||
|
logicPortDir[41] = 3;
|
||||||
|
logicPortUIName[41] = "In41";
|
||||||
|
logicPortCauseUpdate[41] = true;
|
||||||
|
|
||||||
|
logicPortType[42] = 1;
|
||||||
|
logicPortPos[42] = "-21 0 0";
|
||||||
|
logicPortDir[42] = 3;
|
||||||
|
logicPortUIName[42] = "In42";
|
||||||
|
logicPortCauseUpdate[42] = true;
|
||||||
|
|
||||||
|
logicPortType[43] = 1;
|
||||||
|
logicPortPos[43] = "-23 0 0";
|
||||||
|
logicPortDir[43] = 3;
|
||||||
|
logicPortUIName[43] = "In43";
|
||||||
|
logicPortCauseUpdate[43] = true;
|
||||||
|
|
||||||
|
logicPortType[44] = 1;
|
||||||
|
logicPortPos[44] = "-25 0 0";
|
||||||
|
logicPortDir[44] = 3;
|
||||||
|
logicPortUIName[44] = "In44";
|
||||||
|
logicPortCauseUpdate[44] = true;
|
||||||
|
|
||||||
|
logicPortType[45] = 1;
|
||||||
|
logicPortPos[45] = "-27 0 0";
|
||||||
|
logicPortDir[45] = 3;
|
||||||
|
logicPortUIName[45] = "In45";
|
||||||
|
logicPortCauseUpdate[45] = true;
|
||||||
|
|
||||||
|
logicPortType[46] = 1;
|
||||||
|
logicPortPos[46] = "-29 0 0";
|
||||||
|
logicPortDir[46] = 3;
|
||||||
|
logicPortUIName[46] = "In46";
|
||||||
|
logicPortCauseUpdate[46] = true;
|
||||||
|
|
||||||
|
logicPortType[47] = 1;
|
||||||
|
logicPortPos[47] = "-31 0 0";
|
||||||
|
logicPortDir[47] = 3;
|
||||||
|
logicPortUIName[47] = "In47";
|
||||||
|
logicPortCauseUpdate[47] = true;
|
||||||
|
|
||||||
|
logicPortType[48] = 1;
|
||||||
|
logicPortPos[48] = "-33 0 0";
|
||||||
|
logicPortDir[48] = 3;
|
||||||
|
logicPortUIName[48] = "In48";
|
||||||
|
logicPortCauseUpdate[48] = true;
|
||||||
|
|
||||||
|
logicPortType[49] = 1;
|
||||||
|
logicPortPos[49] = "-35 0 0";
|
||||||
|
logicPortDir[49] = 3;
|
||||||
|
logicPortUIName[49] = "In49";
|
||||||
|
logicPortCauseUpdate[49] = true;
|
||||||
|
|
||||||
|
logicPortType[50] = 1;
|
||||||
|
logicPortPos[50] = "-37 0 0";
|
||||||
|
logicPortDir[50] = 3;
|
||||||
|
logicPortUIName[50] = "In50";
|
||||||
|
logicPortCauseUpdate[50] = true;
|
||||||
|
|
||||||
|
logicPortType[51] = 1;
|
||||||
|
logicPortPos[51] = "-39 0 0";
|
||||||
|
logicPortDir[51] = 3;
|
||||||
|
logicPortUIName[51] = "In51";
|
||||||
|
logicPortCauseUpdate[51] = true;
|
||||||
|
|
||||||
|
logicPortType[52] = 1;
|
||||||
|
logicPortPos[52] = "-41 0 0";
|
||||||
|
logicPortDir[52] = 3;
|
||||||
|
logicPortUIName[52] = "In52";
|
||||||
|
logicPortCauseUpdate[52] = true;
|
||||||
|
|
||||||
|
logicPortType[53] = 1;
|
||||||
|
logicPortPos[53] = "-43 0 0";
|
||||||
|
logicPortDir[53] = 3;
|
||||||
|
logicPortUIName[53] = "In53";
|
||||||
|
logicPortCauseUpdate[53] = true;
|
||||||
|
|
||||||
|
logicPortType[54] = 1;
|
||||||
|
logicPortPos[54] = "-45 0 0";
|
||||||
|
logicPortDir[54] = 3;
|
||||||
|
logicPortUIName[54] = "In54";
|
||||||
|
logicPortCauseUpdate[54] = true;
|
||||||
|
|
||||||
|
logicPortType[55] = 1;
|
||||||
|
logicPortPos[55] = "-47 0 0";
|
||||||
|
logicPortDir[55] = 3;
|
||||||
|
logicPortUIName[55] = "In55";
|
||||||
|
logicPortCauseUpdate[55] = true;
|
||||||
|
|
||||||
|
logicPortType[56] = 1;
|
||||||
|
logicPortPos[56] = "-49 0 0";
|
||||||
|
logicPortDir[56] = 3;
|
||||||
|
logicPortUIName[56] = "In56";
|
||||||
|
logicPortCauseUpdate[56] = true;
|
||||||
|
|
||||||
|
logicPortType[57] = 1;
|
||||||
|
logicPortPos[57] = "-51 0 0";
|
||||||
|
logicPortDir[57] = 3;
|
||||||
|
logicPortUIName[57] = "In57";
|
||||||
|
logicPortCauseUpdate[57] = true;
|
||||||
|
|
||||||
|
logicPortType[58] = 1;
|
||||||
|
logicPortPos[58] = "-53 0 0";
|
||||||
|
logicPortDir[58] = 3;
|
||||||
|
logicPortUIName[58] = "In58";
|
||||||
|
logicPortCauseUpdate[58] = true;
|
||||||
|
|
||||||
|
logicPortType[59] = 1;
|
||||||
|
logicPortPos[59] = "-55 0 0";
|
||||||
|
logicPortDir[59] = 3;
|
||||||
|
logicPortUIName[59] = "In59";
|
||||||
|
logicPortCauseUpdate[59] = true;
|
||||||
|
|
||||||
|
logicPortType[60] = 1;
|
||||||
|
logicPortPos[60] = "-57 0 0";
|
||||||
|
logicPortDir[60] = 3;
|
||||||
|
logicPortUIName[60] = "In60";
|
||||||
|
logicPortCauseUpdate[60] = true;
|
||||||
|
|
||||||
|
logicPortType[61] = 1;
|
||||||
|
logicPortPos[61] = "-59 0 0";
|
||||||
|
logicPortDir[61] = 3;
|
||||||
|
logicPortUIName[61] = "In61";
|
||||||
|
logicPortCauseUpdate[61] = true;
|
||||||
|
|
||||||
|
logicPortType[62] = 1;
|
||||||
|
logicPortPos[62] = "-61 0 0";
|
||||||
|
logicPortDir[62] = 3;
|
||||||
|
logicPortUIName[62] = "In62";
|
||||||
|
logicPortCauseUpdate[62] = true;
|
||||||
|
|
||||||
|
logicPortType[63] = 1;
|
||||||
|
logicPortPos[63] = "-63 0 0";
|
||||||
|
logicPortDir[63] = 3;
|
||||||
|
logicPortUIName[63] = "In63";
|
||||||
|
logicPortCauseUpdate[63] = true;
|
||||||
|
|
||||||
|
logicPortType[64] = 0;
|
||||||
|
logicPortPos[64] = "63 0 0";
|
||||||
|
logicPortDir[64] = 1;
|
||||||
|
logicPortUIName[64] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[65] = 0;
|
||||||
|
logicPortPos[65] = "61 0 0";
|
||||||
|
logicPortDir[65] = 1;
|
||||||
|
logicPortUIName[65] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[66] = 0;
|
||||||
|
logicPortPos[66] = "59 0 0";
|
||||||
|
logicPortDir[66] = 1;
|
||||||
|
logicPortUIName[66] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[67] = 0;
|
||||||
|
logicPortPos[67] = "57 0 0";
|
||||||
|
logicPortDir[67] = 1;
|
||||||
|
logicPortUIName[67] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[68] = 0;
|
||||||
|
logicPortPos[68] = "55 0 0";
|
||||||
|
logicPortDir[68] = 1;
|
||||||
|
logicPortUIName[68] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[69] = 0;
|
||||||
|
logicPortPos[69] = "53 0 0";
|
||||||
|
logicPortDir[69] = 1;
|
||||||
|
logicPortUIName[69] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[70] = 0;
|
||||||
|
logicPortPos[70] = "51 0 0";
|
||||||
|
logicPortDir[70] = 1;
|
||||||
|
logicPortUIName[70] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[71] = 0;
|
||||||
|
logicPortPos[71] = "49 0 0";
|
||||||
|
logicPortDir[71] = 1;
|
||||||
|
logicPortUIName[71] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[72] = 0;
|
||||||
|
logicPortPos[72] = "47 0 0";
|
||||||
|
logicPortDir[72] = 1;
|
||||||
|
logicPortUIName[72] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[73] = 0;
|
||||||
|
logicPortPos[73] = "45 0 0";
|
||||||
|
logicPortDir[73] = 1;
|
||||||
|
logicPortUIName[73] = "Out9";
|
||||||
|
|
||||||
|
logicPortType[74] = 0;
|
||||||
|
logicPortPos[74] = "43 0 0";
|
||||||
|
logicPortDir[74] = 1;
|
||||||
|
logicPortUIName[74] = "Out10";
|
||||||
|
|
||||||
|
logicPortType[75] = 0;
|
||||||
|
logicPortPos[75] = "41 0 0";
|
||||||
|
logicPortDir[75] = 1;
|
||||||
|
logicPortUIName[75] = "Out11";
|
||||||
|
|
||||||
|
logicPortType[76] = 0;
|
||||||
|
logicPortPos[76] = "39 0 0";
|
||||||
|
logicPortDir[76] = 1;
|
||||||
|
logicPortUIName[76] = "Out12";
|
||||||
|
|
||||||
|
logicPortType[77] = 0;
|
||||||
|
logicPortPos[77] = "37 0 0";
|
||||||
|
logicPortDir[77] = 1;
|
||||||
|
logicPortUIName[77] = "Out13";
|
||||||
|
|
||||||
|
logicPortType[78] = 0;
|
||||||
|
logicPortPos[78] = "35 0 0";
|
||||||
|
logicPortDir[78] = 1;
|
||||||
|
logicPortUIName[78] = "Out14";
|
||||||
|
|
||||||
|
logicPortType[79] = 0;
|
||||||
|
logicPortPos[79] = "33 0 0";
|
||||||
|
logicPortDir[79] = 1;
|
||||||
|
logicPortUIName[79] = "Out15";
|
||||||
|
|
||||||
|
logicPortType[80] = 0;
|
||||||
|
logicPortPos[80] = "31 0 0";
|
||||||
|
logicPortDir[80] = 1;
|
||||||
|
logicPortUIName[80] = "Out16";
|
||||||
|
|
||||||
|
logicPortType[81] = 0;
|
||||||
|
logicPortPos[81] = "29 0 0";
|
||||||
|
logicPortDir[81] = 1;
|
||||||
|
logicPortUIName[81] = "Out17";
|
||||||
|
|
||||||
|
logicPortType[82] = 0;
|
||||||
|
logicPortPos[82] = "27 0 0";
|
||||||
|
logicPortDir[82] = 1;
|
||||||
|
logicPortUIName[82] = "Out18";
|
||||||
|
|
||||||
|
logicPortType[83] = 0;
|
||||||
|
logicPortPos[83] = "25 0 0";
|
||||||
|
logicPortDir[83] = 1;
|
||||||
|
logicPortUIName[83] = "Out19";
|
||||||
|
|
||||||
|
logicPortType[84] = 0;
|
||||||
|
logicPortPos[84] = "23 0 0";
|
||||||
|
logicPortDir[84] = 1;
|
||||||
|
logicPortUIName[84] = "Out20";
|
||||||
|
|
||||||
|
logicPortType[85] = 0;
|
||||||
|
logicPortPos[85] = "21 0 0";
|
||||||
|
logicPortDir[85] = 1;
|
||||||
|
logicPortUIName[85] = "Out21";
|
||||||
|
|
||||||
|
logicPortType[86] = 0;
|
||||||
|
logicPortPos[86] = "19 0 0";
|
||||||
|
logicPortDir[86] = 1;
|
||||||
|
logicPortUIName[86] = "Out22";
|
||||||
|
|
||||||
|
logicPortType[87] = 0;
|
||||||
|
logicPortPos[87] = "17 0 0";
|
||||||
|
logicPortDir[87] = 1;
|
||||||
|
logicPortUIName[87] = "Out23";
|
||||||
|
|
||||||
|
logicPortType[88] = 0;
|
||||||
|
logicPortPos[88] = "15 0 0";
|
||||||
|
logicPortDir[88] = 1;
|
||||||
|
logicPortUIName[88] = "Out24";
|
||||||
|
|
||||||
|
logicPortType[89] = 0;
|
||||||
|
logicPortPos[89] = "13 0 0";
|
||||||
|
logicPortDir[89] = 1;
|
||||||
|
logicPortUIName[89] = "Out25";
|
||||||
|
|
||||||
|
logicPortType[90] = 0;
|
||||||
|
logicPortPos[90] = "11 0 0";
|
||||||
|
logicPortDir[90] = 1;
|
||||||
|
logicPortUIName[90] = "Out26";
|
||||||
|
|
||||||
|
logicPortType[91] = 0;
|
||||||
|
logicPortPos[91] = "9 0 0";
|
||||||
|
logicPortDir[91] = 1;
|
||||||
|
logicPortUIName[91] = "Out27";
|
||||||
|
|
||||||
|
logicPortType[92] = 0;
|
||||||
|
logicPortPos[92] = "7 0 0";
|
||||||
|
logicPortDir[92] = 1;
|
||||||
|
logicPortUIName[92] = "Out28";
|
||||||
|
|
||||||
|
logicPortType[93] = 0;
|
||||||
|
logicPortPos[93] = "5 0 0";
|
||||||
|
logicPortDir[93] = 1;
|
||||||
|
logicPortUIName[93] = "Out29";
|
||||||
|
|
||||||
|
logicPortType[94] = 0;
|
||||||
|
logicPortPos[94] = "3 0 0";
|
||||||
|
logicPortDir[94] = 1;
|
||||||
|
logicPortUIName[94] = "Out30";
|
||||||
|
|
||||||
|
logicPortType[95] = 0;
|
||||||
|
logicPortPos[95] = "1 0 0";
|
||||||
|
logicPortDir[95] = 1;
|
||||||
|
logicPortUIName[95] = "Out31";
|
||||||
|
|
||||||
|
logicPortType[96] = 0;
|
||||||
|
logicPortPos[96] = "-1 0 0";
|
||||||
|
logicPortDir[96] = 1;
|
||||||
|
logicPortUIName[96] = "Out32";
|
||||||
|
|
||||||
|
logicPortType[97] = 0;
|
||||||
|
logicPortPos[97] = "-3 0 0";
|
||||||
|
logicPortDir[97] = 1;
|
||||||
|
logicPortUIName[97] = "Out33";
|
||||||
|
|
||||||
|
logicPortType[98] = 0;
|
||||||
|
logicPortPos[98] = "-5 0 0";
|
||||||
|
logicPortDir[98] = 1;
|
||||||
|
logicPortUIName[98] = "Out34";
|
||||||
|
|
||||||
|
logicPortType[99] = 0;
|
||||||
|
logicPortPos[99] = "-7 0 0";
|
||||||
|
logicPortDir[99] = 1;
|
||||||
|
logicPortUIName[99] = "Out35";
|
||||||
|
|
||||||
|
logicPortType[100] = 0;
|
||||||
|
logicPortPos[100] = "-9 0 0";
|
||||||
|
logicPortDir[100] = 1;
|
||||||
|
logicPortUIName[100] = "Out36";
|
||||||
|
|
||||||
|
logicPortType[101] = 0;
|
||||||
|
logicPortPos[101] = "-11 0 0";
|
||||||
|
logicPortDir[101] = 1;
|
||||||
|
logicPortUIName[101] = "Out37";
|
||||||
|
|
||||||
|
logicPortType[102] = 0;
|
||||||
|
logicPortPos[102] = "-13 0 0";
|
||||||
|
logicPortDir[102] = 1;
|
||||||
|
logicPortUIName[102] = "Out38";
|
||||||
|
|
||||||
|
logicPortType[103] = 0;
|
||||||
|
logicPortPos[103] = "-15 0 0";
|
||||||
|
logicPortDir[103] = 1;
|
||||||
|
logicPortUIName[103] = "Out39";
|
||||||
|
|
||||||
|
logicPortType[104] = 0;
|
||||||
|
logicPortPos[104] = "-17 0 0";
|
||||||
|
logicPortDir[104] = 1;
|
||||||
|
logicPortUIName[104] = "Out40";
|
||||||
|
|
||||||
|
logicPortType[105] = 0;
|
||||||
|
logicPortPos[105] = "-19 0 0";
|
||||||
|
logicPortDir[105] = 1;
|
||||||
|
logicPortUIName[105] = "Out41";
|
||||||
|
|
||||||
|
logicPortType[106] = 0;
|
||||||
|
logicPortPos[106] = "-21 0 0";
|
||||||
|
logicPortDir[106] = 1;
|
||||||
|
logicPortUIName[106] = "Out42";
|
||||||
|
|
||||||
|
logicPortType[107] = 0;
|
||||||
|
logicPortPos[107] = "-23 0 0";
|
||||||
|
logicPortDir[107] = 1;
|
||||||
|
logicPortUIName[107] = "Out43";
|
||||||
|
|
||||||
|
logicPortType[108] = 0;
|
||||||
|
logicPortPos[108] = "-25 0 0";
|
||||||
|
logicPortDir[108] = 1;
|
||||||
|
logicPortUIName[108] = "Out44";
|
||||||
|
|
||||||
|
logicPortType[109] = 0;
|
||||||
|
logicPortPos[109] = "-27 0 0";
|
||||||
|
logicPortDir[109] = 1;
|
||||||
|
logicPortUIName[109] = "Out45";
|
||||||
|
|
||||||
|
logicPortType[110] = 0;
|
||||||
|
logicPortPos[110] = "-29 0 0";
|
||||||
|
logicPortDir[110] = 1;
|
||||||
|
logicPortUIName[110] = "Out46";
|
||||||
|
|
||||||
|
logicPortType[111] = 0;
|
||||||
|
logicPortPos[111] = "-31 0 0";
|
||||||
|
logicPortDir[111] = 1;
|
||||||
|
logicPortUIName[111] = "Out47";
|
||||||
|
|
||||||
|
logicPortType[112] = 0;
|
||||||
|
logicPortPos[112] = "-33 0 0";
|
||||||
|
logicPortDir[112] = 1;
|
||||||
|
logicPortUIName[112] = "Out48";
|
||||||
|
|
||||||
|
logicPortType[113] = 0;
|
||||||
|
logicPortPos[113] = "-35 0 0";
|
||||||
|
logicPortDir[113] = 1;
|
||||||
|
logicPortUIName[113] = "Out49";
|
||||||
|
|
||||||
|
logicPortType[114] = 0;
|
||||||
|
logicPortPos[114] = "-37 0 0";
|
||||||
|
logicPortDir[114] = 1;
|
||||||
|
logicPortUIName[114] = "Out50";
|
||||||
|
|
||||||
|
logicPortType[115] = 0;
|
||||||
|
logicPortPos[115] = "-39 0 0";
|
||||||
|
logicPortDir[115] = 1;
|
||||||
|
logicPortUIName[115] = "Out51";
|
||||||
|
|
||||||
|
logicPortType[116] = 0;
|
||||||
|
logicPortPos[116] = "-41 0 0";
|
||||||
|
logicPortDir[116] = 1;
|
||||||
|
logicPortUIName[116] = "Out52";
|
||||||
|
|
||||||
|
logicPortType[117] = 0;
|
||||||
|
logicPortPos[117] = "-43 0 0";
|
||||||
|
logicPortDir[117] = 1;
|
||||||
|
logicPortUIName[117] = "Out53";
|
||||||
|
|
||||||
|
logicPortType[118] = 0;
|
||||||
|
logicPortPos[118] = "-45 0 0";
|
||||||
|
logicPortDir[118] = 1;
|
||||||
|
logicPortUIName[118] = "Out54";
|
||||||
|
|
||||||
|
logicPortType[119] = 0;
|
||||||
|
logicPortPos[119] = "-47 0 0";
|
||||||
|
logicPortDir[119] = 1;
|
||||||
|
logicPortUIName[119] = "Out55";
|
||||||
|
|
||||||
|
logicPortType[120] = 0;
|
||||||
|
logicPortPos[120] = "-49 0 0";
|
||||||
|
logicPortDir[120] = 1;
|
||||||
|
logicPortUIName[120] = "Out56";
|
||||||
|
|
||||||
|
logicPortType[121] = 0;
|
||||||
|
logicPortPos[121] = "-51 0 0";
|
||||||
|
logicPortDir[121] = 1;
|
||||||
|
logicPortUIName[121] = "Out57";
|
||||||
|
|
||||||
|
logicPortType[122] = 0;
|
||||||
|
logicPortPos[122] = "-53 0 0";
|
||||||
|
logicPortDir[122] = 1;
|
||||||
|
logicPortUIName[122] = "Out58";
|
||||||
|
|
||||||
|
logicPortType[123] = 0;
|
||||||
|
logicPortPos[123] = "-55 0 0";
|
||||||
|
logicPortDir[123] = 1;
|
||||||
|
logicPortUIName[123] = "Out59";
|
||||||
|
|
||||||
|
logicPortType[124] = 0;
|
||||||
|
logicPortPos[124] = "-57 0 0";
|
||||||
|
logicPortDir[124] = 1;
|
||||||
|
logicPortUIName[124] = "Out60";
|
||||||
|
|
||||||
|
logicPortType[125] = 0;
|
||||||
|
logicPortPos[125] = "-59 0 0";
|
||||||
|
logicPortDir[125] = 1;
|
||||||
|
logicPortUIName[125] = "Out61";
|
||||||
|
|
||||||
|
logicPortType[126] = 0;
|
||||||
|
logicPortPos[126] = "-61 0 0";
|
||||||
|
logicPortDir[126] = 1;
|
||||||
|
logicPortUIName[126] = "Out62";
|
||||||
|
|
||||||
|
logicPortType[127] = 0;
|
||||||
|
logicPortPos[127] = "-63 0 0";
|
||||||
|
logicPortDir[127] = 1;
|
||||||
|
logicPortUIName[127] = "Out63";
|
||||||
|
|
||||||
|
logicPortType[128] = 1;
|
||||||
|
logicPortPos[128] = "63 0 0";
|
||||||
|
logicPortDir[128] = 2;
|
||||||
|
logicPortUIName[128] = "Clock";
|
||||||
|
logicPortCauseUpdate[128] = true;
|
||||||
|
|
||||||
|
};
|
132
bricks/gen/newcode/Enabler Active Low 7 Bit.cs
Normal file
132
bricks/gen/newcode/Enabler Active Low 7 Bit.cs
Normal file
@ -0,0 +1,132 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl7_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 7 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 7 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 7 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 7 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "7 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[15].state then " @
|
||||||
|
" gate.ports[8]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[7].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[8]:setstate(false) " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 15;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "6 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "4 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "2 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "0 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-2 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-4 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-6 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 0;
|
||||||
|
logicPortPos[7] = "6 0 0";
|
||||||
|
logicPortDir[7] = 1;
|
||||||
|
logicPortUIName[7] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "4 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "2 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "0 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "-2 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-4 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-6 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[14] = 1;
|
||||||
|
logicPortPos[14] = "6 0 0";
|
||||||
|
logicPortDir[14] = 2;
|
||||||
|
logicPortUIName[14] = "Clock";
|
||||||
|
logicPortCauseUpdate[14] = true;
|
||||||
|
|
||||||
|
};
|
145
bricks/gen/newcode/Enabler Active Low 8 Bit.cs
Normal file
145
bricks/gen/newcode/Enabler Active Low 8 Bit.cs
Normal file
@ -0,0 +1,145 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl8_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 8 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 8 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 8 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 8 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "8 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[17].state then " @
|
||||||
|
" gate.ports[9]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[8].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[9]:setstate(false) " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 17;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "7 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "5 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "3 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "1 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "-1 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-3 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-5 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-7 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 0;
|
||||||
|
logicPortPos[8] = "7 0 0";
|
||||||
|
logicPortDir[8] = 1;
|
||||||
|
logicPortUIName[8] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "5 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "3 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "1 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "-1 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "-3 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-5 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-7 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[16] = 1;
|
||||||
|
logicPortPos[16] = "7 0 0";
|
||||||
|
logicPortDir[16] = 2;
|
||||||
|
logicPortUIName[16] = "Clock";
|
||||||
|
logicPortCauseUpdate[16] = true;
|
||||||
|
|
||||||
|
};
|
158
bricks/gen/newcode/Enabler Active Low 9 Bit.cs
Normal file
158
bricks/gen/newcode/Enabler Active Low 9 Bit.cs
Normal file
@ -0,0 +1,158 @@
|
|||||||
|
|
||||||
|
datablock fxDtsBrickData(LogicGate_EnablerAl9_Data){
|
||||||
|
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Enabler Active Low 9 Bit.blb";
|
||||||
|
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Enabler Active Low 9 Bit";
|
||||||
|
|
||||||
|
category = "Logic Bricks";
|
||||||
|
subCategory = "Bus";
|
||||||
|
uiName = "Enabler Active Low 9 Bit";
|
||||||
|
logicUIName = "Enabler Active Low 9 Bit";
|
||||||
|
logicUIDesc = "";
|
||||||
|
|
||||||
|
hasPrint = 1;
|
||||||
|
printAspectRatio = "Logic";
|
||||||
|
|
||||||
|
logicBrickSize = "9 1 1";
|
||||||
|
orientationFix = 3;
|
||||||
|
|
||||||
|
isLogic = true;
|
||||||
|
isLogicGate = true;
|
||||||
|
isLogicInput = false;
|
||||||
|
|
||||||
|
logicInit = "";
|
||||||
|
logicInput = "";
|
||||||
|
logicUpdate =
|
||||||
|
"return function(gate) " @
|
||||||
|
" if not gate.ports[19].state then " @
|
||||||
|
" gate.ports[10]:setstate(gate.ports[1].state) " @
|
||||||
|
" gate.ports[11]:setstate(gate.ports[2].state) " @
|
||||||
|
" gate.ports[12]:setstate(gate.ports[3].state) " @
|
||||||
|
" gate.ports[13]:setstate(gate.ports[4].state) " @
|
||||||
|
" gate.ports[14]:setstate(gate.ports[5].state) " @
|
||||||
|
" gate.ports[15]:setstate(gate.ports[6].state) " @
|
||||||
|
" gate.ports[16]:setstate(gate.ports[7].state) " @
|
||||||
|
" gate.ports[17]:setstate(gate.ports[8].state) " @
|
||||||
|
" gate.ports[18]:setstate(gate.ports[9].state) " @
|
||||||
|
" else " @
|
||||||
|
" gate.ports[10]:setstate(false) " @
|
||||||
|
" gate.ports[11]:setstate(false) " @
|
||||||
|
" gate.ports[12]:setstate(false) " @
|
||||||
|
" gate.ports[13]:setstate(false) " @
|
||||||
|
" gate.ports[14]:setstate(false) " @
|
||||||
|
" gate.ports[15]:setstate(false) " @
|
||||||
|
" gate.ports[16]:setstate(false) " @
|
||||||
|
" gate.ports[17]:setstate(false) " @
|
||||||
|
" gate.ports[18]:setstate(false) " @
|
||||||
|
" end " @
|
||||||
|
"end"
|
||||||
|
;
|
||||||
|
logicGlobal = "";
|
||||||
|
|
||||||
|
numLogicPorts = 19;
|
||||||
|
|
||||||
|
logicPortType[0] = 1;
|
||||||
|
logicPortPos[0] = "8 0 0";
|
||||||
|
logicPortDir[0] = 3;
|
||||||
|
logicPortUIName[0] = "In0";
|
||||||
|
logicPortCauseUpdate[0] = true;
|
||||||
|
|
||||||
|
logicPortType[1] = 1;
|
||||||
|
logicPortPos[1] = "6 0 0";
|
||||||
|
logicPortDir[1] = 3;
|
||||||
|
logicPortUIName[1] = "In1";
|
||||||
|
logicPortCauseUpdate[1] = true;
|
||||||
|
|
||||||
|
logicPortType[2] = 1;
|
||||||
|
logicPortPos[2] = "4 0 0";
|
||||||
|
logicPortDir[2] = 3;
|
||||||
|
logicPortUIName[2] = "In2";
|
||||||
|
logicPortCauseUpdate[2] = true;
|
||||||
|
|
||||||
|
logicPortType[3] = 1;
|
||||||
|
logicPortPos[3] = "2 0 0";
|
||||||
|
logicPortDir[3] = 3;
|
||||||
|
logicPortUIName[3] = "In3";
|
||||||
|
logicPortCauseUpdate[3] = true;
|
||||||
|
|
||||||
|
logicPortType[4] = 1;
|
||||||
|
logicPortPos[4] = "0 0 0";
|
||||||
|
logicPortDir[4] = 3;
|
||||||
|
logicPortUIName[4] = "In4";
|
||||||
|
logicPortCauseUpdate[4] = true;
|
||||||
|
|
||||||
|
logicPortType[5] = 1;
|
||||||
|
logicPortPos[5] = "-2 0 0";
|
||||||
|
logicPortDir[5] = 3;
|
||||||
|
logicPortUIName[5] = "In5";
|
||||||
|
logicPortCauseUpdate[5] = true;
|
||||||
|
|
||||||
|
logicPortType[6] = 1;
|
||||||
|
logicPortPos[6] = "-4 0 0";
|
||||||
|
logicPortDir[6] = 3;
|
||||||
|
logicPortUIName[6] = "In6";
|
||||||
|
logicPortCauseUpdate[6] = true;
|
||||||
|
|
||||||
|
logicPortType[7] = 1;
|
||||||
|
logicPortPos[7] = "-6 0 0";
|
||||||
|
logicPortDir[7] = 3;
|
||||||
|
logicPortUIName[7] = "In7";
|
||||||
|
logicPortCauseUpdate[7] = true;
|
||||||
|
|
||||||
|
logicPortType[8] = 1;
|
||||||
|
logicPortPos[8] = "-8 0 0";
|
||||||
|
logicPortDir[8] = 3;
|
||||||
|
logicPortUIName[8] = "In8";
|
||||||
|
logicPortCauseUpdate[8] = true;
|
||||||
|
|
||||||
|
logicPortType[9] = 0;
|
||||||
|
logicPortPos[9] = "8 0 0";
|
||||||
|
logicPortDir[9] = 1;
|
||||||
|
logicPortUIName[9] = "Out0";
|
||||||
|
|
||||||
|
logicPortType[10] = 0;
|
||||||
|
logicPortPos[10] = "6 0 0";
|
||||||
|
logicPortDir[10] = 1;
|
||||||
|
logicPortUIName[10] = "Out1";
|
||||||
|
|
||||||
|
logicPortType[11] = 0;
|
||||||
|
logicPortPos[11] = "4 0 0";
|
||||||
|
logicPortDir[11] = 1;
|
||||||
|
logicPortUIName[11] = "Out2";
|
||||||
|
|
||||||
|
logicPortType[12] = 0;
|
||||||
|
logicPortPos[12] = "2 0 0";
|
||||||
|
logicPortDir[12] = 1;
|
||||||
|
logicPortUIName[12] = "Out3";
|
||||||
|
|
||||||
|
logicPortType[13] = 0;
|
||||||
|
logicPortPos[13] = "0 0 0";
|
||||||
|
logicPortDir[13] = 1;
|
||||||
|
logicPortUIName[13] = "Out4";
|
||||||
|
|
||||||
|
logicPortType[14] = 0;
|
||||||
|
logicPortPos[14] = "-2 0 0";
|
||||||
|
logicPortDir[14] = 1;
|
||||||
|
logicPortUIName[14] = "Out5";
|
||||||
|
|
||||||
|
logicPortType[15] = 0;
|
||||||
|
logicPortPos[15] = "-4 0 0";
|
||||||
|
logicPortDir[15] = 1;
|
||||||
|
logicPortUIName[15] = "Out6";
|
||||||
|
|
||||||
|
logicPortType[16] = 0;
|
||||||
|
logicPortPos[16] = "-6 0 0";
|
||||||
|
logicPortDir[16] = 1;
|
||||||
|
logicPortUIName[16] = "Out7";
|
||||||
|
|
||||||
|
logicPortType[17] = 0;
|
||||||
|
logicPortPos[17] = "-8 0 0";
|
||||||
|
logicPortDir[17] = 1;
|
||||||
|
logicPortUIName[17] = "Out8";
|
||||||
|
|
||||||
|
logicPortType[18] = 1;
|
||||||
|
logicPortPos[18] = "8 0 0";
|
||||||
|
logicPortDir[18] = 2;
|
||||||
|
logicPortUIName[18] = "Clock";
|
||||||
|
logicPortCauseUpdate[18] = true;
|
||||||
|
|
||||||
|
};
|
BIN
bricks/gen/newicons/Buffer 48 Bit.png
Normal file
BIN
bricks/gen/newicons/Buffer 48 Bit.png
Normal file
Binary file not shown.
After Width: | Height: | Size: 714 B |
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user