replaced a lot ofbricks with generated ones
This commit is contained in:
Redo
53
bricks/gen/newcode/AND 2 Bit.cs
Normal file
53
bricks/gen/newcode/AND 2 Bit.cs
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@@ -0,0 +1,53 @@
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datablock fxDtsBrickData(LogicGate_GateAnd2_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 2 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 2 Bit";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 2 Bit";
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logicUIName = "AND 2 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "2 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" gate.ports[3]:setstate(( " @
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" gate.ports[1].state and " @
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" gate.ports[2].state " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 3;
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logicPortType[0] = 1;
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logicPortPos[0] = "1 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "-1 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 0;
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logicPortPos[2] = "1 0 0";
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logicPortDir[2] = 1;
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logicPortUIName[2] = "Out";
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};
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60
bricks/gen/newcode/AND 3 Bit.cs
Normal file
60
bricks/gen/newcode/AND 3 Bit.cs
Normal file
@@ -0,0 +1,60 @@
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datablock fxDtsBrickData(LogicGate_GateAnd3_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 3 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 3 Bit";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 3 Bit";
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logicUIName = "AND 3 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "3 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" gate.ports[4]:setstate(( " @
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" gate.ports[1].state and " @
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" gate.ports[2].state and " @
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" gate.ports[3].state " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 4;
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logicPortType[0] = 1;
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logicPortPos[0] = "2 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "-2 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 0;
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logicPortPos[3] = "2 0 0";
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logicPortDir[3] = 1;
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logicPortUIName[3] = "Out";
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};
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67
bricks/gen/newcode/AND 4 Bit.cs
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67
bricks/gen/newcode/AND 4 Bit.cs
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@@ -0,0 +1,67 @@
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datablock fxDtsBrickData(LogicGate_GateAnd4_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 4 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 4 Bit";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 4 Bit";
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logicUIName = "AND 4 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "4 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" gate.ports[5]:setstate(( " @
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" gate.ports[1].state and " @
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" gate.ports[2].state and " @
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" gate.ports[3].state and " @
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" gate.ports[4].state " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 5;
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logicPortType[0] = 1;
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logicPortPos[0] = "3 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "1 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "-1 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "-3 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 0;
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logicPortPos[4] = "3 0 0";
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logicPortDir[4] = 1;
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logicPortUIName[4] = "Out";
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};
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74
bricks/gen/newcode/AND 5 Bit.cs
Normal file
74
bricks/gen/newcode/AND 5 Bit.cs
Normal file
@@ -0,0 +1,74 @@
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datablock fxDtsBrickData(LogicGate_GateAnd5_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 5 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 5 Bit";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 5 Bit";
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logicUIName = "AND 5 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "5 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" gate.ports[6]:setstate(( " @
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" gate.ports[1].state and " @
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" gate.ports[2].state and " @
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" gate.ports[3].state and " @
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" gate.ports[4].state and " @
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" gate.ports[5].state " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 6;
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logicPortType[0] = 1;
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logicPortPos[0] = "4 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "2 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "-2 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "-4 0 0";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 0;
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logicPortPos[5] = "4 0 0";
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logicPortDir[5] = 1;
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logicPortUIName[5] = "Out";
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};
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81
bricks/gen/newcode/AND 6 Bit.cs
Normal file
81
bricks/gen/newcode/AND 6 Bit.cs
Normal file
@@ -0,0 +1,81 @@
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datablock fxDtsBrickData(LogicGate_GateAnd6_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 6 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 6 Bit";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 6 Bit";
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logicUIName = "AND 6 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "6 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" gate.ports[7]:setstate(( " @
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" gate.ports[1].state and " @
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" gate.ports[2].state and " @
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" gate.ports[3].state and " @
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" gate.ports[4].state and " @
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" gate.ports[5].state and " @
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" gate.ports[6].state " @
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" )) " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 7;
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logicPortType[0] = 1;
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logicPortPos[0] = "5 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "3 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "1 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "-1 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "-3 0 0";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 1;
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logicPortPos[5] = "-5 0 0";
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logicPortDir[5] = 3;
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logicPortUIName[5] = "In5";
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logicPortCauseUpdate[5] = true;
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logicPortType[6] = 0;
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logicPortPos[6] = "5 0 0";
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logicPortDir[6] = 1;
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logicPortUIName[6] = "Out";
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};
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88
bricks/gen/newcode/AND 7 Bit.cs
Normal file
88
bricks/gen/newcode/AND 7 Bit.cs
Normal file
@@ -0,0 +1,88 @@
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datablock fxDtsBrickData(LogicGate_GateAnd7_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 7 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 7 Bit";
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category = "Logic Bricks";
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subCategory = "Gates";
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uiName = "AND 7 Bit";
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logicUIName = "AND 7 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "7 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" gate.ports[8]:setstate(( " @
|
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" gate.ports[1].state and " @
|
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" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state and " @
|
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" gate.ports[5].state and " @
|
||||
" gate.ports[6].state and " @
|
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" gate.ports[7].state " @
|
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" )) " @
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"end"
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||||
;
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logicGlobal = "";
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numLogicPorts = 8;
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logicPortType[0] = 1;
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logicPortPos[0] = "6 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "4 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "2 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "0 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "-2 0 0";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortCauseUpdate[4] = true;
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|
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logicPortType[5] = 1;
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logicPortPos[5] = "-4 0 0";
|
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logicPortDir[5] = 3;
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logicPortUIName[5] = "In5";
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logicPortCauseUpdate[5] = true;
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logicPortType[6] = 1;
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logicPortPos[6] = "-6 0 0";
|
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logicPortDir[6] = 3;
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logicPortUIName[6] = "In6";
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logicPortCauseUpdate[6] = true;
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logicPortType[7] = 0;
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logicPortPos[7] = "6 0 0";
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logicPortDir[7] = 1;
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logicPortUIName[7] = "Out";
|
||||
|
||||
};
|
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95
bricks/gen/newcode/AND 8 Bit.cs
Normal file
95
bricks/gen/newcode/AND 8 Bit.cs
Normal file
@@ -0,0 +1,95 @@
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datablock fxDtsBrickData(LogicGate_GateAnd8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "AND 8 Bit";
|
||||
logicUIName = "AND 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
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isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[9]:setstate(( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state and " @
|
||||
" gate.ports[5].state and " @
|
||||
" gate.ports[6].state and " @
|
||||
" gate.ports[7].state and " @
|
||||
" gate.ports[8].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out";
|
||||
|
||||
};
|
||||
53
bricks/gen/newcode/Buffer 1 Bit.cs
Normal file
53
bricks/gen/newcode/Buffer 1 Bit.cs
Normal file
@@ -0,0 +1,53 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 1 Bit";
|
||||
logicUIName = "Buffer 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[3].state then " @
|
||||
" gate.ports[2]:setstate(gate.ports[1].state) " @
|
||||
" else " @
|
||||
" gate.ports[2]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
161
bricks/gen/newcode/Buffer 10 Bit.cs
Normal file
161
bricks/gen/newcode/Buffer 10 Bit.cs
Normal file
@@ -0,0 +1,161 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer10_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 10 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 10 Bit";
|
||||
logicUIName = "Buffer 10 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[21].state then " @
|
||||
" gate.ports[11]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[10].state) " @
|
||||
" else " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
173
bricks/gen/newcode/Buffer 11 Bit.cs
Normal file
173
bricks/gen/newcode/Buffer 11 Bit.cs
Normal file
@@ -0,0 +1,173 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer11_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 11 Bit";
|
||||
logicUIName = "Buffer 11 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[23].state then " @
|
||||
" gate.ports[12]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[11].state) " @
|
||||
" else " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
185
bricks/gen/newcode/Buffer 12 Bit.cs
Normal file
185
bricks/gen/newcode/Buffer 12 Bit.cs
Normal file
@@ -0,0 +1,185 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer12_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 12 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 12 Bit";
|
||||
logicUIName = "Buffer 12 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[25].state then " @
|
||||
" gate.ports[13]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[12].state) " @
|
||||
" else " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
197
bricks/gen/newcode/Buffer 13 Bit.cs
Normal file
197
bricks/gen/newcode/Buffer 13 Bit.cs
Normal file
@@ -0,0 +1,197 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer13_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 13 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 13 Bit";
|
||||
logicUIName = "Buffer 13 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[27].state then " @
|
||||
" gate.ports[14]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[13].state) " @
|
||||
" else " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
209
bricks/gen/newcode/Buffer 14 Bit.cs
Normal file
209
bricks/gen/newcode/Buffer 14 Bit.cs
Normal file
@@ -0,0 +1,209 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer14_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 14 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 14 Bit";
|
||||
logicUIName = "Buffer 14 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[29].state then " @
|
||||
" gate.ports[15]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[14].state) " @
|
||||
" else " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
221
bricks/gen/newcode/Buffer 15 Bit.cs
Normal file
221
bricks/gen/newcode/Buffer 15 Bit.cs
Normal file
@@ -0,0 +1,221 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer15_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 15 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 15 Bit";
|
||||
logicUIName = "Buffer 15 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[31].state then " @
|
||||
" gate.ports[16]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[15].state) " @
|
||||
" else " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" gate.ports[29]:setstate(false) " @
|
||||
" gate.ports[30]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
233
bricks/gen/newcode/Buffer 16 Bit.cs
Normal file
233
bricks/gen/newcode/Buffer 16 Bit.cs
Normal file
@@ -0,0 +1,233 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 16 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 16 Bit";
|
||||
logicUIName = "Buffer 16 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[33].state then " @
|
||||
" gate.ports[17]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[16].state) " @
|
||||
" else " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" gate.ports[29]:setstate(false) " @
|
||||
" gate.ports[30]:setstate(false) " @
|
||||
" gate.ports[31]:setstate(false) " @
|
||||
" gate.ports[32]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
65
bricks/gen/newcode/Buffer 2 Bit.cs
Normal file
65
bricks/gen/newcode/Buffer 2 Bit.cs
Normal file
@@ -0,0 +1,65 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 2 Bit";
|
||||
logicUIName = "Buffer 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[5].state then " @
|
||||
" gate.ports[3]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[4]:setstate(gate.ports[2].state) " @
|
||||
" else " @
|
||||
" gate.ports[3]:setstate(false) " @
|
||||
" gate.ports[4]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
329
bricks/gen/newcode/Buffer 24 Bit.cs
Normal file
329
bricks/gen/newcode/Buffer 24 Bit.cs
Normal file
@@ -0,0 +1,329 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer24_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 24 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 24 Bit";
|
||||
logicUIName = "Buffer 24 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[49].state then " @
|
||||
" gate.ports[25]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[33]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[24].state) " @
|
||||
" else " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" gate.ports[29]:setstate(false) " @
|
||||
" gate.ports[30]:setstate(false) " @
|
||||
" gate.ports[31]:setstate(false) " @
|
||||
" gate.ports[32]:setstate(false) " @
|
||||
" gate.ports[33]:setstate(false) " @
|
||||
" gate.ports[34]:setstate(false) " @
|
||||
" gate.ports[35]:setstate(false) " @
|
||||
" gate.ports[36]:setstate(false) " @
|
||||
" gate.ports[37]:setstate(false) " @
|
||||
" gate.ports[38]:setstate(false) " @
|
||||
" gate.ports[39]:setstate(false) " @
|
||||
" gate.ports[40]:setstate(false) " @
|
||||
" gate.ports[41]:setstate(false) " @
|
||||
" gate.ports[42]:setstate(false) " @
|
||||
" gate.ports[43]:setstate(false) " @
|
||||
" gate.ports[44]:setstate(false) " @
|
||||
" gate.ports[45]:setstate(false) " @
|
||||
" gate.ports[46]:setstate(false) " @
|
||||
" gate.ports[47]:setstate(false) " @
|
||||
" gate.ports[48]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
77
bricks/gen/newcode/Buffer 3 Bit.cs
Normal file
77
bricks/gen/newcode/Buffer 3 Bit.cs
Normal file
@@ -0,0 +1,77 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 3 Bit";
|
||||
logicUIName = "Buffer 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[7].state then " @
|
||||
" gate.ports[4]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[5]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[3].state) " @
|
||||
" else " @
|
||||
" gate.ports[4]:setstate(false) " @
|
||||
" gate.ports[5]:setstate(false) " @
|
||||
" gate.ports[6]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
425
bricks/gen/newcode/Buffer 32 Bit.cs
Normal file
425
bricks/gen/newcode/Buffer 32 Bit.cs
Normal file
@@ -0,0 +1,425 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 32 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 32 Bit";
|
||||
logicUIName = "Buffer 32 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[65].state then " @
|
||||
" gate.ports[33]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[49]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[50]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[51]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[52]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[53]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[54]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[55]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[56]:setstate(gate.ports[24].state) " @
|
||||
" gate.ports[57]:setstate(gate.ports[25].state) " @
|
||||
" gate.ports[58]:setstate(gate.ports[26].state) " @
|
||||
" gate.ports[59]:setstate(gate.ports[27].state) " @
|
||||
" gate.ports[60]:setstate(gate.ports[28].state) " @
|
||||
" gate.ports[61]:setstate(gate.ports[29].state) " @
|
||||
" gate.ports[62]:setstate(gate.ports[30].state) " @
|
||||
" gate.ports[63]:setstate(gate.ports[31].state) " @
|
||||
" gate.ports[64]:setstate(gate.ports[32].state) " @
|
||||
" else " @
|
||||
" gate.ports[33]:setstate(false) " @
|
||||
" gate.ports[34]:setstate(false) " @
|
||||
" gate.ports[35]:setstate(false) " @
|
||||
" gate.ports[36]:setstate(false) " @
|
||||
" gate.ports[37]:setstate(false) " @
|
||||
" gate.ports[38]:setstate(false) " @
|
||||
" gate.ports[39]:setstate(false) " @
|
||||
" gate.ports[40]:setstate(false) " @
|
||||
" gate.ports[41]:setstate(false) " @
|
||||
" gate.ports[42]:setstate(false) " @
|
||||
" gate.ports[43]:setstate(false) " @
|
||||
" gate.ports[44]:setstate(false) " @
|
||||
" gate.ports[45]:setstate(false) " @
|
||||
" gate.ports[46]:setstate(false) " @
|
||||
" gate.ports[47]:setstate(false) " @
|
||||
" gate.ports[48]:setstate(false) " @
|
||||
" gate.ports[49]:setstate(false) " @
|
||||
" gate.ports[50]:setstate(false) " @
|
||||
" gate.ports[51]:setstate(false) " @
|
||||
" gate.ports[52]:setstate(false) " @
|
||||
" gate.ports[53]:setstate(false) " @
|
||||
" gate.ports[54]:setstate(false) " @
|
||||
" gate.ports[55]:setstate(false) " @
|
||||
" gate.ports[56]:setstate(false) " @
|
||||
" gate.ports[57]:setstate(false) " @
|
||||
" gate.ports[58]:setstate(false) " @
|
||||
" gate.ports[59]:setstate(false) " @
|
||||
" gate.ports[60]:setstate(false) " @
|
||||
" gate.ports[61]:setstate(false) " @
|
||||
" gate.ports[62]:setstate(false) " @
|
||||
" gate.ports[63]:setstate(false) " @
|
||||
" gate.ports[64]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 0 0";
|
||||
logicPortDir[24] = 3;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 0 0";
|
||||
logicPortDir[25] = 3;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 0 0";
|
||||
logicPortDir[26] = 3;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 0 0";
|
||||
logicPortDir[27] = 3;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 0 0";
|
||||
logicPortDir[28] = 3;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 0 0";
|
||||
logicPortDir[29] = 3;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 0 0";
|
||||
logicPortDir[30] = 3;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 0 0";
|
||||
logicPortDir[31] = 3;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out15";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-1 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out16";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-3 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out17";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-5 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out18";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-7 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out19";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-9 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out20";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-11 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out21";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-13 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out22";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-15 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out23";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-17 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out24";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-19 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out25";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-21 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out26";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-23 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out27";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-25 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out28";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-27 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out29";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-29 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out30";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-31 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out31";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "31 0 0";
|
||||
logicPortDir[64] = 2;
|
||||
logicPortUIName[64] = "Clock";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
};
|
||||
89
bricks/gen/newcode/Buffer 4 Bit.cs
Normal file
89
bricks/gen/newcode/Buffer 4 Bit.cs
Normal file
@@ -0,0 +1,89 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 4 Bit";
|
||||
logicUIName = "Buffer 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[9].state then " @
|
||||
" gate.ports[5]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[4].state) " @
|
||||
" else " @
|
||||
" gate.ports[5]:setstate(false) " @
|
||||
" gate.ports[6]:setstate(false) " @
|
||||
" gate.ports[7]:setstate(false) " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 0 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
101
bricks/gen/newcode/Buffer 5 Bit.cs
Normal file
101
bricks/gen/newcode/Buffer 5 Bit.cs
Normal file
@@ -0,0 +1,101 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 5 Bit";
|
||||
logicUIName = "Buffer 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[11].state then " @
|
||||
" gate.ports[6]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[5].state) " @
|
||||
" else " @
|
||||
" gate.ports[6]:setstate(false) " @
|
||||
" gate.ports[7]:setstate(false) " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "4 0 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
113
bricks/gen/newcode/Buffer 6 Bit.cs
Normal file
113
bricks/gen/newcode/Buffer 6 Bit.cs
Normal file
@@ -0,0 +1,113 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 6 Bit";
|
||||
logicUIName = "Buffer 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[13].state then " @
|
||||
" gate.ports[7]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[6].state) " @
|
||||
" else " @
|
||||
" gate.ports[7]:setstate(false) " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "1 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-1 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-5 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
||||
125
bricks/gen/newcode/Buffer 7 Bit.cs
Normal file
125
bricks/gen/newcode/Buffer 7 Bit.cs
Normal file
@@ -0,0 +1,125 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 7 Bit";
|
||||
logicUIName = "Buffer 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[15].state then " @
|
||||
" gate.ports[8]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[7].state) " @
|
||||
" else " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "4 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "2 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-2 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-4 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "6 0 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
||||
137
bricks/gen/newcode/Buffer 8 Bit.cs
Normal file
137
bricks/gen/newcode/Buffer 8 Bit.cs
Normal file
@@ -0,0 +1,137 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 8 Bit";
|
||||
logicUIName = "Buffer 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[17].state then " @
|
||||
" gate.ports[9]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[8].state) " @
|
||||
" else " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "7 0 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
||||
149
bricks/gen/newcode/Buffer 9 Bit.cs
Normal file
149
bricks/gen/newcode/Buffer 9 Bit.cs
Normal file
@@ -0,0 +1,149 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Buffer9_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 9 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 9 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer 9 Bit";
|
||||
logicUIName = "Buffer 9 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "9 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[19].state then " @
|
||||
" gate.ports[10]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[9].state) " @
|
||||
" else " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "6 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "4 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-4 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-6 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-8 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "8 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out0";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "6 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out1";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "4 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out2";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "2 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out3";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out4";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-2 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out5";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-4 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out6";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out7";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-8 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out8";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
53
bricks/gen/newcode/Buffer Active Low 1 Bit.cs
Normal file
53
bricks/gen/newcode/Buffer Active Low 1 Bit.cs
Normal file
@@ -0,0 +1,53 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 1 Bit";
|
||||
logicUIName = "Buffer Active Low 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[3].state then " @
|
||||
" gate.ports[2]:setstate(gate.ports[1].state) " @
|
||||
" else " @
|
||||
" gate.ports[2]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
161
bricks/gen/newcode/Buffer Active Low 10 Bit.cs
Normal file
161
bricks/gen/newcode/Buffer Active Low 10 Bit.cs
Normal file
@@ -0,0 +1,161 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl10_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 10 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 10 Bit";
|
||||
logicUIName = "Buffer Active Low 10 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[21].state then " @
|
||||
" gate.ports[11]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[10].state) " @
|
||||
" else " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
173
bricks/gen/newcode/Buffer Active Low 11 Bit.cs
Normal file
173
bricks/gen/newcode/Buffer Active Low 11 Bit.cs
Normal file
@@ -0,0 +1,173 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl11_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 11 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 11 Bit";
|
||||
logicUIName = "Buffer Active Low 11 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[23].state then " @
|
||||
" gate.ports[12]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[11].state) " @
|
||||
" else " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
185
bricks/gen/newcode/Buffer Active Low 12 Bit.cs
Normal file
185
bricks/gen/newcode/Buffer Active Low 12 Bit.cs
Normal file
@@ -0,0 +1,185 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl12_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 12 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 12 Bit";
|
||||
logicUIName = "Buffer Active Low 12 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[25].state then " @
|
||||
" gate.ports[13]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[12].state) " @
|
||||
" else " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
197
bricks/gen/newcode/Buffer Active Low 13 Bit.cs
Normal file
197
bricks/gen/newcode/Buffer Active Low 13 Bit.cs
Normal file
@@ -0,0 +1,197 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl13_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 13 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 13 Bit";
|
||||
logicUIName = "Buffer Active Low 13 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[27].state then " @
|
||||
" gate.ports[14]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[13].state) " @
|
||||
" else " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
209
bricks/gen/newcode/Buffer Active Low 14 Bit.cs
Normal file
209
bricks/gen/newcode/Buffer Active Low 14 Bit.cs
Normal file
@@ -0,0 +1,209 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl14_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 14 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 14 Bit";
|
||||
logicUIName = "Buffer Active Low 14 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[29].state then " @
|
||||
" gate.ports[15]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[14].state) " @
|
||||
" else " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
221
bricks/gen/newcode/Buffer Active Low 15 Bit.cs
Normal file
221
bricks/gen/newcode/Buffer Active Low 15 Bit.cs
Normal file
@@ -0,0 +1,221 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl15_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 15 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 15 Bit";
|
||||
logicUIName = "Buffer Active Low 15 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[31].state then " @
|
||||
" gate.ports[16]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[15].state) " @
|
||||
" else " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" gate.ports[29]:setstate(false) " @
|
||||
" gate.ports[30]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
233
bricks/gen/newcode/Buffer Active Low 16 Bit.cs
Normal file
233
bricks/gen/newcode/Buffer Active Low 16 Bit.cs
Normal file
@@ -0,0 +1,233 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 16 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 16 Bit";
|
||||
logicUIName = "Buffer Active Low 16 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[33].state then " @
|
||||
" gate.ports[17]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[16].state) " @
|
||||
" else " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" gate.ports[19]:setstate(false) " @
|
||||
" gate.ports[20]:setstate(false) " @
|
||||
" gate.ports[21]:setstate(false) " @
|
||||
" gate.ports[22]:setstate(false) " @
|
||||
" gate.ports[23]:setstate(false) " @
|
||||
" gate.ports[24]:setstate(false) " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" gate.ports[29]:setstate(false) " @
|
||||
" gate.ports[30]:setstate(false) " @
|
||||
" gate.ports[31]:setstate(false) " @
|
||||
" gate.ports[32]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
65
bricks/gen/newcode/Buffer Active Low 2 Bit.cs
Normal file
65
bricks/gen/newcode/Buffer Active Low 2 Bit.cs
Normal file
@@ -0,0 +1,65 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 2 Bit";
|
||||
logicUIName = "Buffer Active Low 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[5].state then " @
|
||||
" gate.ports[3]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[4]:setstate(gate.ports[2].state) " @
|
||||
" else " @
|
||||
" gate.ports[3]:setstate(false) " @
|
||||
" gate.ports[4]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
329
bricks/gen/newcode/Buffer Active Low 24 Bit.cs
Normal file
329
bricks/gen/newcode/Buffer Active Low 24 Bit.cs
Normal file
@@ -0,0 +1,329 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl24_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 24 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 24 Bit";
|
||||
logicUIName = "Buffer Active Low 24 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[49].state then " @
|
||||
" gate.ports[25]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[33]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[24].state) " @
|
||||
" else " @
|
||||
" gate.ports[25]:setstate(false) " @
|
||||
" gate.ports[26]:setstate(false) " @
|
||||
" gate.ports[27]:setstate(false) " @
|
||||
" gate.ports[28]:setstate(false) " @
|
||||
" gate.ports[29]:setstate(false) " @
|
||||
" gate.ports[30]:setstate(false) " @
|
||||
" gate.ports[31]:setstate(false) " @
|
||||
" gate.ports[32]:setstate(false) " @
|
||||
" gate.ports[33]:setstate(false) " @
|
||||
" gate.ports[34]:setstate(false) " @
|
||||
" gate.ports[35]:setstate(false) " @
|
||||
" gate.ports[36]:setstate(false) " @
|
||||
" gate.ports[37]:setstate(false) " @
|
||||
" gate.ports[38]:setstate(false) " @
|
||||
" gate.ports[39]:setstate(false) " @
|
||||
" gate.ports[40]:setstate(false) " @
|
||||
" gate.ports[41]:setstate(false) " @
|
||||
" gate.ports[42]:setstate(false) " @
|
||||
" gate.ports[43]:setstate(false) " @
|
||||
" gate.ports[44]:setstate(false) " @
|
||||
" gate.ports[45]:setstate(false) " @
|
||||
" gate.ports[46]:setstate(false) " @
|
||||
" gate.ports[47]:setstate(false) " @
|
||||
" gate.ports[48]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
77
bricks/gen/newcode/Buffer Active Low 3 Bit.cs
Normal file
77
bricks/gen/newcode/Buffer Active Low 3 Bit.cs
Normal file
@@ -0,0 +1,77 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 3 Bit";
|
||||
logicUIName = "Buffer Active Low 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[7].state then " @
|
||||
" gate.ports[4]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[5]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[3].state) " @
|
||||
" else " @
|
||||
" gate.ports[4]:setstate(false) " @
|
||||
" gate.ports[5]:setstate(false) " @
|
||||
" gate.ports[6]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
425
bricks/gen/newcode/Buffer Active Low 32 Bit.cs
Normal file
425
bricks/gen/newcode/Buffer Active Low 32 Bit.cs
Normal file
@@ -0,0 +1,425 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 32 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 32 Bit";
|
||||
logicUIName = "Buffer Active Low 32 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[65].state then " @
|
||||
" gate.ports[33]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[49]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[50]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[51]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[52]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[53]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[54]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[55]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[56]:setstate(gate.ports[24].state) " @
|
||||
" gate.ports[57]:setstate(gate.ports[25].state) " @
|
||||
" gate.ports[58]:setstate(gate.ports[26].state) " @
|
||||
" gate.ports[59]:setstate(gate.ports[27].state) " @
|
||||
" gate.ports[60]:setstate(gate.ports[28].state) " @
|
||||
" gate.ports[61]:setstate(gate.ports[29].state) " @
|
||||
" gate.ports[62]:setstate(gate.ports[30].state) " @
|
||||
" gate.ports[63]:setstate(gate.ports[31].state) " @
|
||||
" gate.ports[64]:setstate(gate.ports[32].state) " @
|
||||
" else " @
|
||||
" gate.ports[33]:setstate(false) " @
|
||||
" gate.ports[34]:setstate(false) " @
|
||||
" gate.ports[35]:setstate(false) " @
|
||||
" gate.ports[36]:setstate(false) " @
|
||||
" gate.ports[37]:setstate(false) " @
|
||||
" gate.ports[38]:setstate(false) " @
|
||||
" gate.ports[39]:setstate(false) " @
|
||||
" gate.ports[40]:setstate(false) " @
|
||||
" gate.ports[41]:setstate(false) " @
|
||||
" gate.ports[42]:setstate(false) " @
|
||||
" gate.ports[43]:setstate(false) " @
|
||||
" gate.ports[44]:setstate(false) " @
|
||||
" gate.ports[45]:setstate(false) " @
|
||||
" gate.ports[46]:setstate(false) " @
|
||||
" gate.ports[47]:setstate(false) " @
|
||||
" gate.ports[48]:setstate(false) " @
|
||||
" gate.ports[49]:setstate(false) " @
|
||||
" gate.ports[50]:setstate(false) " @
|
||||
" gate.ports[51]:setstate(false) " @
|
||||
" gate.ports[52]:setstate(false) " @
|
||||
" gate.ports[53]:setstate(false) " @
|
||||
" gate.ports[54]:setstate(false) " @
|
||||
" gate.ports[55]:setstate(false) " @
|
||||
" gate.ports[56]:setstate(false) " @
|
||||
" gate.ports[57]:setstate(false) " @
|
||||
" gate.ports[58]:setstate(false) " @
|
||||
" gate.ports[59]:setstate(false) " @
|
||||
" gate.ports[60]:setstate(false) " @
|
||||
" gate.ports[61]:setstate(false) " @
|
||||
" gate.ports[62]:setstate(false) " @
|
||||
" gate.ports[63]:setstate(false) " @
|
||||
" gate.ports[64]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 0 0";
|
||||
logicPortDir[24] = 3;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 0 0";
|
||||
logicPortDir[25] = 3;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 0 0";
|
||||
logicPortDir[26] = 3;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 0 0";
|
||||
logicPortDir[27] = 3;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 0 0";
|
||||
logicPortDir[28] = 3;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 0 0";
|
||||
logicPortDir[29] = 3;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 0 0";
|
||||
logicPortDir[30] = 3;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 0 0";
|
||||
logicPortDir[31] = 3;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out15";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-1 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out16";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-3 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out17";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-5 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out18";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-7 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out19";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-9 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out20";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-11 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out21";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-13 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out22";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-15 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out23";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-17 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out24";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-19 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out25";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-21 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out26";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-23 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out27";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-25 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out28";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-27 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out29";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-29 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out30";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-31 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out31";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "31 0 0";
|
||||
logicPortDir[64] = 2;
|
||||
logicPortUIName[64] = "Clock";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
};
|
||||
89
bricks/gen/newcode/Buffer Active Low 4 Bit.cs
Normal file
89
bricks/gen/newcode/Buffer Active Low 4 Bit.cs
Normal file
@@ -0,0 +1,89 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 4 Bit";
|
||||
logicUIName = "Buffer Active Low 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[9].state then " @
|
||||
" gate.ports[5]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[4].state) " @
|
||||
" else " @
|
||||
" gate.ports[5]:setstate(false) " @
|
||||
" gate.ports[6]:setstate(false) " @
|
||||
" gate.ports[7]:setstate(false) " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 0 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
101
bricks/gen/newcode/Buffer Active Low 5 Bit.cs
Normal file
101
bricks/gen/newcode/Buffer Active Low 5 Bit.cs
Normal file
@@ -0,0 +1,101 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 5 Bit";
|
||||
logicUIName = "Buffer Active Low 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[11].state then " @
|
||||
" gate.ports[6]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[5].state) " @
|
||||
" else " @
|
||||
" gate.ports[6]:setstate(false) " @
|
||||
" gate.ports[7]:setstate(false) " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "4 0 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
113
bricks/gen/newcode/Buffer Active Low 6 Bit.cs
Normal file
113
bricks/gen/newcode/Buffer Active Low 6 Bit.cs
Normal file
@@ -0,0 +1,113 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 6 Bit";
|
||||
logicUIName = "Buffer Active Low 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[13].state then " @
|
||||
" gate.ports[7]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[6].state) " @
|
||||
" else " @
|
||||
" gate.ports[7]:setstate(false) " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "1 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-1 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-5 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
||||
125
bricks/gen/newcode/Buffer Active Low 7 Bit.cs
Normal file
125
bricks/gen/newcode/Buffer Active Low 7 Bit.cs
Normal file
@@ -0,0 +1,125 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 7 Bit";
|
||||
logicUIName = "Buffer Active Low 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[15].state then " @
|
||||
" gate.ports[8]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[7].state) " @
|
||||
" else " @
|
||||
" gate.ports[8]:setstate(false) " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "4 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "2 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-2 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-4 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "6 0 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
||||
137
bricks/gen/newcode/Buffer Active Low 8 Bit.cs
Normal file
137
bricks/gen/newcode/Buffer Active Low 8 Bit.cs
Normal file
@@ -0,0 +1,137 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 8 Bit";
|
||||
logicUIName = "Buffer Active Low 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[17].state then " @
|
||||
" gate.ports[9]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[8].state) " @
|
||||
" else " @
|
||||
" gate.ports[9]:setstate(false) " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "7 0 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
||||
149
bricks/gen/newcode/Buffer Active Low 9 Bit.cs
Normal file
149
bricks/gen/newcode/Buffer Active Low 9 Bit.cs
Normal file
@@ -0,0 +1,149 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_BufferAl9_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer Active Low 9 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer Active Low 9 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "Buffer Active Low 9 Bit";
|
||||
logicUIName = "Buffer Active Low 9 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "9 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[19].state then " @
|
||||
" gate.ports[10]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[9].state) " @
|
||||
" else " @
|
||||
" gate.ports[10]:setstate(false) " @
|
||||
" gate.ports[11]:setstate(false) " @
|
||||
" gate.ports[12]:setstate(false) " @
|
||||
" gate.ports[13]:setstate(false) " @
|
||||
" gate.ports[14]:setstate(false) " @
|
||||
" gate.ports[15]:setstate(false) " @
|
||||
" gate.ports[16]:setstate(false) " @
|
||||
" gate.ports[17]:setstate(false) " @
|
||||
" gate.ports[18]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "6 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "4 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-4 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-6 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-8 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "8 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out0";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "6 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out1";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "4 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out2";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "2 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out3";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out4";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-2 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out5";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-4 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out6";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out7";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-8 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out8";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
51
bricks/gen/newcode/D FlipFlop 1 Bit.cs
Normal file
51
bricks/gen/newcode/D FlipFlop 1 Bit.cs
Normal file
@@ -0,0 +1,51 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 1 Bit";
|
||||
logicUIName = "D FlipFlop 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[3].state then " @
|
||||
" gate.ports[2]:setstate(gate.ports[1].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
150
bricks/gen/newcode/D FlipFlop 10 Bit.cs
Normal file
150
bricks/gen/newcode/D FlipFlop 10 Bit.cs
Normal file
@@ -0,0 +1,150 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop10_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 10 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 10 Bit";
|
||||
logicUIName = "D FlipFlop 10 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[21].state then " @
|
||||
" gate.ports[11]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[10].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
161
bricks/gen/newcode/D FlipFlop 11 Bit.cs
Normal file
161
bricks/gen/newcode/D FlipFlop 11 Bit.cs
Normal file
@@ -0,0 +1,161 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop11_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 11 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 11 Bit";
|
||||
logicUIName = "D FlipFlop 11 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[23].state then " @
|
||||
" gate.ports[12]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[11].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
172
bricks/gen/newcode/D FlipFlop 12 Bit.cs
Normal file
172
bricks/gen/newcode/D FlipFlop 12 Bit.cs
Normal file
@@ -0,0 +1,172 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop12_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 12 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 12 Bit";
|
||||
logicUIName = "D FlipFlop 12 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[25].state then " @
|
||||
" gate.ports[13]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[12].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
183
bricks/gen/newcode/D FlipFlop 13 Bit.cs
Normal file
183
bricks/gen/newcode/D FlipFlop 13 Bit.cs
Normal file
@@ -0,0 +1,183 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop13_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 13 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 13 Bit";
|
||||
logicUIName = "D FlipFlop 13 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[27].state then " @
|
||||
" gate.ports[14]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[13].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
194
bricks/gen/newcode/D FlipFlop 14 Bit.cs
Normal file
194
bricks/gen/newcode/D FlipFlop 14 Bit.cs
Normal file
@@ -0,0 +1,194 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop14_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 14 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 14 Bit";
|
||||
logicUIName = "D FlipFlop 14 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[29].state then " @
|
||||
" gate.ports[15]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[14].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
205
bricks/gen/newcode/D FlipFlop 15 Bit.cs
Normal file
205
bricks/gen/newcode/D FlipFlop 15 Bit.cs
Normal file
@@ -0,0 +1,205 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop15_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 15 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 15 Bit";
|
||||
logicUIName = "D FlipFlop 15 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[31].state then " @
|
||||
" gate.ports[16]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[15].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
216
bricks/gen/newcode/D FlipFlop 16 Bit.cs
Normal file
216
bricks/gen/newcode/D FlipFlop 16 Bit.cs
Normal file
@@ -0,0 +1,216 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 16 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 16 Bit";
|
||||
logicUIName = "D FlipFlop 16 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[33].state then " @
|
||||
" gate.ports[17]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[16].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
62
bricks/gen/newcode/D FlipFlop 2 Bit.cs
Normal file
62
bricks/gen/newcode/D FlipFlop 2 Bit.cs
Normal file
@@ -0,0 +1,62 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 2 Bit";
|
||||
logicUIName = "D FlipFlop 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[5].state then " @
|
||||
" gate.ports[3]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[4]:setstate(gate.ports[2].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
304
bricks/gen/newcode/D FlipFlop 24 Bit.cs
Normal file
304
bricks/gen/newcode/D FlipFlop 24 Bit.cs
Normal file
@@ -0,0 +1,304 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop24_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 24 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 24 Bit";
|
||||
logicUIName = "D FlipFlop 24 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[49].state then " @
|
||||
" gate.ports[25]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[33]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[24].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
73
bricks/gen/newcode/D FlipFlop 3 Bit.cs
Normal file
73
bricks/gen/newcode/D FlipFlop 3 Bit.cs
Normal file
@@ -0,0 +1,73 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 3 Bit";
|
||||
logicUIName = "D FlipFlop 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[7].state then " @
|
||||
" gate.ports[4]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[5]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[3].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
392
bricks/gen/newcode/D FlipFlop 32 Bit.cs
Normal file
392
bricks/gen/newcode/D FlipFlop 32 Bit.cs
Normal file
@@ -0,0 +1,392 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 32 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 32 Bit";
|
||||
logicUIName = "D FlipFlop 32 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[65].state then " @
|
||||
" gate.ports[33]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[49]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[50]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[51]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[52]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[53]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[54]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[55]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[56]:setstate(gate.ports[24].state) " @
|
||||
" gate.ports[57]:setstate(gate.ports[25].state) " @
|
||||
" gate.ports[58]:setstate(gate.ports[26].state) " @
|
||||
" gate.ports[59]:setstate(gate.ports[27].state) " @
|
||||
" gate.ports[60]:setstate(gate.ports[28].state) " @
|
||||
" gate.ports[61]:setstate(gate.ports[29].state) " @
|
||||
" gate.ports[62]:setstate(gate.ports[30].state) " @
|
||||
" gate.ports[63]:setstate(gate.ports[31].state) " @
|
||||
" gate.ports[64]:setstate(gate.ports[32].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 0 0";
|
||||
logicPortDir[24] = 3;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 0 0";
|
||||
logicPortDir[25] = 3;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 0 0";
|
||||
logicPortDir[26] = 3;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 0 0";
|
||||
logicPortDir[27] = 3;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 0 0";
|
||||
logicPortDir[28] = 3;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 0 0";
|
||||
logicPortDir[29] = 3;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 0 0";
|
||||
logicPortDir[30] = 3;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 0 0";
|
||||
logicPortDir[31] = 3;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out15";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-1 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out16";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-3 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out17";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-5 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out18";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-7 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out19";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-9 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out20";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-11 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out21";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-13 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out22";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-15 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out23";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-17 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out24";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-19 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out25";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-21 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out26";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-23 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out27";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-25 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out28";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-27 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out29";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-29 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out30";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-31 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out31";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "31 0 0";
|
||||
logicPortDir[64] = 2;
|
||||
logicPortUIName[64] = "Clock";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
};
|
||||
84
bricks/gen/newcode/D FlipFlop 4 Bit.cs
Normal file
84
bricks/gen/newcode/D FlipFlop 4 Bit.cs
Normal file
@@ -0,0 +1,84 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 4 Bit";
|
||||
logicUIName = "D FlipFlop 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[9].state then " @
|
||||
" gate.ports[5]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[4].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 0 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
95
bricks/gen/newcode/D FlipFlop 5 Bit.cs
Normal file
95
bricks/gen/newcode/D FlipFlop 5 Bit.cs
Normal file
@@ -0,0 +1,95 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 5 Bit";
|
||||
logicUIName = "D FlipFlop 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[11].state then " @
|
||||
" gate.ports[6]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[5].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "4 0 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
106
bricks/gen/newcode/D FlipFlop 6 Bit.cs
Normal file
106
bricks/gen/newcode/D FlipFlop 6 Bit.cs
Normal file
@@ -0,0 +1,106 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 6 Bit";
|
||||
logicUIName = "D FlipFlop 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[13].state then " @
|
||||
" gate.ports[7]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[6].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "1 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-1 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-5 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
||||
117
bricks/gen/newcode/D FlipFlop 7 Bit.cs
Normal file
117
bricks/gen/newcode/D FlipFlop 7 Bit.cs
Normal file
@@ -0,0 +1,117 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 7 Bit";
|
||||
logicUIName = "D FlipFlop 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[15].state then " @
|
||||
" gate.ports[8]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[7].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "4 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "2 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-2 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-4 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "6 0 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
||||
128
bricks/gen/newcode/D FlipFlop 8 Bit.cs
Normal file
128
bricks/gen/newcode/D FlipFlop 8 Bit.cs
Normal file
@@ -0,0 +1,128 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 8 Bit";
|
||||
logicUIName = "D FlipFlop 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[17].state then " @
|
||||
" gate.ports[9]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[8].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "7 0 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
||||
139
bricks/gen/newcode/D FlipFlop 9 Bit.cs
Normal file
139
bricks/gen/newcode/D FlipFlop 9 Bit.cs
Normal file
@@ -0,0 +1,139 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlop9_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop 9 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop 9 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop 9 Bit";
|
||||
logicUIName = "D FlipFlop 9 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "9 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[19].state then " @
|
||||
" gate.ports[10]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[9].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "6 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "4 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-4 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-6 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-8 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "8 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out0";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "6 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out1";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "4 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out2";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "2 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out3";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out4";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-2 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out5";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-4 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out6";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out7";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-8 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out8";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
51
bricks/gen/newcode/D FlipFlop Active Low 1 Bit.cs
Normal file
51
bricks/gen/newcode/D FlipFlop Active Low 1 Bit.cs
Normal file
@@ -0,0 +1,51 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 1 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[3].state then " @
|
||||
" gate.ports[2]:setstate(gate.ports[1].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 2;
|
||||
logicPortUIName[2] = "Clock";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
};
|
||||
150
bricks/gen/newcode/D FlipFlop Active Low 10 Bit.cs
Normal file
150
bricks/gen/newcode/D FlipFlop Active Low 10 Bit.cs
Normal file
@@ -0,0 +1,150 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl10_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 10 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 10 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 10 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 10 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "10 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[21].state then " @
|
||||
" gate.ports[11]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[10].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "9 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "7 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "5 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-5 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-9 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "9 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "1 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-1 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-5 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-7 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out9";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "9 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
161
bricks/gen/newcode/D FlipFlop Active Low 11 Bit.cs
Normal file
161
bricks/gen/newcode/D FlipFlop Active Low 11 Bit.cs
Normal file
@@ -0,0 +1,161 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl11_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 11 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 11 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 11 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 11 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "11 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[23].state then " @
|
||||
" gate.ports[12]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[11].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "10 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "8 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "6 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "4 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-4 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-6 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-8 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-10 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "10 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out0";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "8 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out1";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out2";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "4 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out3";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "2 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out4";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out5";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-2 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out6";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-4 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out7";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out8";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-8 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out9";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-10 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out10";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "10 0 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
||||
172
bricks/gen/newcode/D FlipFlop Active Low 12 Bit.cs
Normal file
172
bricks/gen/newcode/D FlipFlop Active Low 12 Bit.cs
Normal file
@@ -0,0 +1,172 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl12_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 12 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 12 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 12 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 12 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "12 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[25].state then " @
|
||||
" gate.ports[13]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[12].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "11 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "9 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "7 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "5 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-5 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-7 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-9 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-11 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "11 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "9 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "7 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "5 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "3 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "1 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-1 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-5 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-7 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-9 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-11 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out11";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "11 0 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
||||
183
bricks/gen/newcode/D FlipFlop Active Low 13 Bit.cs
Normal file
183
bricks/gen/newcode/D FlipFlop Active Low 13 Bit.cs
Normal file
@@ -0,0 +1,183 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl13_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 13 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 13 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 13 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 13 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "13 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[27].state then " @
|
||||
" gate.ports[14]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[13].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "12 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "10 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "8 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "6 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-2 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-4 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-6 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-8 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-10 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-12 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "12 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out0";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "10 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out1";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "8 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out2";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out3";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "4 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out4";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "2 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out5";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out6";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-2 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out7";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-4 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out8";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-6 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out9";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-8 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out10";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-10 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out11";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-12 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out12";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "12 0 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
||||
194
bricks/gen/newcode/D FlipFlop Active Low 14 Bit.cs
Normal file
194
bricks/gen/newcode/D FlipFlop Active Low 14 Bit.cs
Normal file
@@ -0,0 +1,194 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl14_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 14 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 14 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 14 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 14 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "14 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[29].state then " @
|
||||
" gate.ports[15]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[14].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "13 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "11 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "9 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-11 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-13 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out0";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out1";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out2";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out3";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out4";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out5";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out6";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out7";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out8";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out9";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out10";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out11";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out12";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out13";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "13 0 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
||||
205
bricks/gen/newcode/D FlipFlop Active Low 15 Bit.cs
Normal file
205
bricks/gen/newcode/D FlipFlop Active Low 15 Bit.cs
Normal file
@@ -0,0 +1,205 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl15_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 15 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 15 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 15 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 15 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "15 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[31].state then " @
|
||||
" gate.ports[16]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[15].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 31;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "14 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "12 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "10 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "8 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "6 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-6 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-8 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-10 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-12 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-14 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "14 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out0";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "12 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out1";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "10 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out2";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out3";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "6 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out4";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "4 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out5";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "2 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out6";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out7";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-2 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out8";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-4 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out9";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-6 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out10";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-8 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out11";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-10 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out12";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-12 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out13";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-14 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out14";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "14 0 0";
|
||||
logicPortDir[30] = 2;
|
||||
logicPortUIName[30] = "Clock";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
};
|
||||
216
bricks/gen/newcode/D FlipFlop Active Low 16 Bit.cs
Normal file
216
bricks/gen/newcode/D FlipFlop Active Low 16 Bit.cs
Normal file
@@ -0,0 +1,216 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 16 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 16 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 16 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[33].state then " @
|
||||
" gate.ports[17]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[19]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[20]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[21]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[22]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[23]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[24]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[25]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[16].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 33;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out7";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out8";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out9";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out10";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out11";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out12";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out13";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out14";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out15";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "15 0 0";
|
||||
logicPortDir[32] = 2;
|
||||
logicPortUIName[32] = "Clock";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
};
|
||||
62
bricks/gen/newcode/D FlipFlop Active Low 2 Bit.cs
Normal file
62
bricks/gen/newcode/D FlipFlop Active Low 2 Bit.cs
Normal file
@@ -0,0 +1,62 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 2 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[5].state then " @
|
||||
" gate.ports[3]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[4]:setstate(gate.ports[2].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "1 0 0";
|
||||
logicPortDir[4] = 2;
|
||||
logicPortUIName[4] = "Clock";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
||||
304
bricks/gen/newcode/D FlipFlop Active Low 24 Bit.cs
Normal file
304
bricks/gen/newcode/D FlipFlop Active Low 24 Bit.cs
Normal file
@@ -0,0 +1,304 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl24_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 24 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 24 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 24 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 24 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "24 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[49].state then " @
|
||||
" gate.ports[25]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[26]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[27]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[28]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[29]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[30]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[31]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[32]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[33]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[24].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 49;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "23 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "21 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "19 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "17 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-17 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-19 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-21 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-23 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "23 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out0";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "21 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out1";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "19 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out2";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "17 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out3";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out4";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "13 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out5";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "11 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out6";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "9 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out7";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "7 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out8";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "5 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out9";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "3 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out10";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "1 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out11";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-1 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out12";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-3 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out13";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-5 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out14";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-7 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out15";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-9 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out16";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-11 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out17";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-13 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out18";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-15 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out19";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-17 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out20";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-19 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out21";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-21 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out22";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-23 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out23";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "23 0 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "Clock";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
};
|
||||
73
bricks/gen/newcode/D FlipFlop Active Low 3 Bit.cs
Normal file
73
bricks/gen/newcode/D FlipFlop Active Low 3 Bit.cs
Normal file
@@ -0,0 +1,73 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 3 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[7].state then " @
|
||||
" gate.ports[4]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[5]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[3].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "Clock";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
392
bricks/gen/newcode/D FlipFlop Active Low 32 Bit.cs
Normal file
392
bricks/gen/newcode/D FlipFlop Active Low 32 Bit.cs
Normal file
@@ -0,0 +1,392 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 32 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 32 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 32 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[65].state then " @
|
||||
" gate.ports[33]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[34]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[35]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[36]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[37]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[38]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[39]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[40]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[41]:setstate(gate.ports[9].state) " @
|
||||
" gate.ports[42]:setstate(gate.ports[10].state) " @
|
||||
" gate.ports[43]:setstate(gate.ports[11].state) " @
|
||||
" gate.ports[44]:setstate(gate.ports[12].state) " @
|
||||
" gate.ports[45]:setstate(gate.ports[13].state) " @
|
||||
" gate.ports[46]:setstate(gate.ports[14].state) " @
|
||||
" gate.ports[47]:setstate(gate.ports[15].state) " @
|
||||
" gate.ports[48]:setstate(gate.ports[16].state) " @
|
||||
" gate.ports[49]:setstate(gate.ports[17].state) " @
|
||||
" gate.ports[50]:setstate(gate.ports[18].state) " @
|
||||
" gate.ports[51]:setstate(gate.ports[19].state) " @
|
||||
" gate.ports[52]:setstate(gate.ports[20].state) " @
|
||||
" gate.ports[53]:setstate(gate.ports[21].state) " @
|
||||
" gate.ports[54]:setstate(gate.ports[22].state) " @
|
||||
" gate.ports[55]:setstate(gate.ports[23].state) " @
|
||||
" gate.ports[56]:setstate(gate.ports[24].state) " @
|
||||
" gate.ports[57]:setstate(gate.ports[25].state) " @
|
||||
" gate.ports[58]:setstate(gate.ports[26].state) " @
|
||||
" gate.ports[59]:setstate(gate.ports[27].state) " @
|
||||
" gate.ports[60]:setstate(gate.ports[28].state) " @
|
||||
" gate.ports[61]:setstate(gate.ports[29].state) " @
|
||||
" gate.ports[62]:setstate(gate.ports[30].state) " @
|
||||
" gate.ports[63]:setstate(gate.ports[31].state) " @
|
||||
" gate.ports[64]:setstate(gate.ports[32].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 65;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 0 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "In9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 0 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "In10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 0 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "In11";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 0 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "In12";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 0 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "In13";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 0 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "In14";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 0 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "In15";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 0 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "In16";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 0 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "In17";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 0 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "In18";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 0 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "In19";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 0 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "In20";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 0 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "In21";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 0 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "In22";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 0 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "In23";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 0 0";
|
||||
logicPortDir[24] = 3;
|
||||
logicPortUIName[24] = "In24";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 0 0";
|
||||
logicPortDir[25] = 3;
|
||||
logicPortUIName[25] = "In25";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 0 0";
|
||||
logicPortDir[26] = 3;
|
||||
logicPortUIName[26] = "In26";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 0 0";
|
||||
logicPortDir[27] = 3;
|
||||
logicPortUIName[27] = "In27";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 0 0";
|
||||
logicPortDir[28] = 3;
|
||||
logicPortUIName[28] = "In28";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 0 0";
|
||||
logicPortDir[29] = 3;
|
||||
logicPortUIName[29] = "In29";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 0 0";
|
||||
logicPortDir[30] = 3;
|
||||
logicPortUIName[30] = "In30";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 0 0";
|
||||
logicPortDir[31] = 3;
|
||||
logicPortUIName[31] = "In31";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out15";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-1 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out16";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-3 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out17";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-5 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out18";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-7 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out19";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-9 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out20";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-11 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out21";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-13 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out22";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-15 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out23";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-17 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out24";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-19 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out25";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-21 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out26";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-23 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out27";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-25 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out28";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-27 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out29";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-29 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out30";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-31 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out31";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "31 0 0";
|
||||
logicPortDir[64] = 2;
|
||||
logicPortUIName[64] = "Clock";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
};
|
||||
84
bricks/gen/newcode/D FlipFlop Active Low 4 Bit.cs
Normal file
84
bricks/gen/newcode/D FlipFlop Active Low 4 Bit.cs
Normal file
@@ -0,0 +1,84 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 4 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[9].state then " @
|
||||
" gate.ports[5]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[6]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[4].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 0 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
95
bricks/gen/newcode/D FlipFlop Active Low 5 Bit.cs
Normal file
95
bricks/gen/newcode/D FlipFlop Active Low 5 Bit.cs
Normal file
@@ -0,0 +1,95 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 5 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[11].state then " @
|
||||
" gate.ports[6]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[7]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[5].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "2 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-2 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-4 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "4 0 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
106
bricks/gen/newcode/D FlipFlop Active Low 6 Bit.cs
Normal file
106
bricks/gen/newcode/D FlipFlop Active Low 6 Bit.cs
Normal file
@@ -0,0 +1,106 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 6 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[13].state then " @
|
||||
" gate.ports[7]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[8]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[6].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "3 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "1 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-1 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-5 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "5 0 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
||||
117
bricks/gen/newcode/D FlipFlop Active Low 7 Bit.cs
Normal file
117
bricks/gen/newcode/D FlipFlop Active Low 7 Bit.cs
Normal file
@@ -0,0 +1,117 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 7 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[15].state then " @
|
||||
" gate.ports[8]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[9]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[7].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "4 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "2 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-2 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-4 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-6 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "6 0 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
||||
128
bricks/gen/newcode/D FlipFlop Active Low 8 Bit.cs
Normal file
128
bricks/gen/newcode/D FlipFlop Active Low 8 Bit.cs
Normal file
@@ -0,0 +1,128 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 8 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[17].state then " @
|
||||
" gate.ports[9]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[10]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[8].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "7 0 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
||||
139
bricks/gen/newcode/D FlipFlop Active Low 9 Bit.cs
Normal file
139
bricks/gen/newcode/D FlipFlop Active Low 9 Bit.cs
Normal file
@@ -0,0 +1,139 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_DFlipFlopAl9_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/D FlipFlop Active Low 9 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/D FlipFlop Active Low 9 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Bus";
|
||||
uiName = "D FlipFlop Active Low 9 Bit";
|
||||
logicUIName = "D FlipFlop Active Low 9 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "9 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if not gate.ports[19].state then " @
|
||||
" gate.ports[10]:setstate(gate.ports[1].state) " @
|
||||
" gate.ports[11]:setstate(gate.ports[2].state) " @
|
||||
" gate.ports[12]:setstate(gate.ports[3].state) " @
|
||||
" gate.ports[13]:setstate(gate.ports[4].state) " @
|
||||
" gate.ports[14]:setstate(gate.ports[5].state) " @
|
||||
" gate.ports[15]:setstate(gate.ports[6].state) " @
|
||||
" gate.ports[16]:setstate(gate.ports[7].state) " @
|
||||
" gate.ports[17]:setstate(gate.ports[8].state) " @
|
||||
" gate.ports[18]:setstate(gate.ports[9].state) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 19;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "8 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "6 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "4 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-2 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-4 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-6 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-8 0 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "In8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "8 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out0";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "6 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out1";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "4 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out2";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "2 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out3";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out4";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-2 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out5";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-4 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out6";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-6 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out7";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-8 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out8";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "8 0 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
69
bricks/gen/newcode/Demux 1 Bit.cs
Normal file
69
bricks/gen/newcode/Demux 1 Bit.cs
Normal file
@@ -0,0 +1,69 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 1 Bit";
|
||||
logicUIName = "Demux 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 2 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[4].state then " @
|
||||
" local idx = 2 + " @
|
||||
" (gate.ports[1].state and 1 or 0) " @
|
||||
" gate.ports[idx]:setstate(true) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "Out0";
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out1";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 2;
|
||||
logicPortUIName[3] = "In";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
};
|
||||
86
bricks/gen/newcode/Demux 2 Bit.cs
Normal file
86
bricks/gen/newcode/Demux 2 Bit.cs
Normal file
@@ -0,0 +1,86 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 2 Bit";
|
||||
logicUIName = "Demux 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 3 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[7].state then " @
|
||||
" local idx = 3 + " @
|
||||
" (gate.ports[1].state and 1 or 0) + " @
|
||||
" (gate.ports[2].state and 2 or 0) " @
|
||||
" gate.ports[idx]:setstate(true) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out0";
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out1";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out2";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out3";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "In";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
113
bricks/gen/newcode/Demux 3 Bit.cs
Normal file
113
bricks/gen/newcode/Demux 3 Bit.cs
Normal file
@@ -0,0 +1,113 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 3 Bit";
|
||||
logicUIName = "Demux 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 4 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[12].state then " @
|
||||
" local idx = 4 + " @
|
||||
" (gate.ports[1].state and 1 or 0) + " @
|
||||
" (gate.ports[2].state and 2 or 0) + " @
|
||||
" (gate.ports[3].state and 4 or 0) " @
|
||||
" gate.ports[idx]:setstate(true) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 12;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out0";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out1";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out2";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out3";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out4";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out5";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out6";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out7";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
logicPortDir[11] = 2;
|
||||
logicPortUIName[11] = "In";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
};
|
||||
160
bricks/gen/newcode/Demux 4 Bit.cs
Normal file
160
bricks/gen/newcode/Demux 4 Bit.cs
Normal file
@@ -0,0 +1,160 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 4 Bit";
|
||||
logicUIName = "Demux 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 5 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[21].state then " @
|
||||
" local idx = 5 + " @
|
||||
" (gate.ports[1].state and 1 or 0) + " @
|
||||
" (gate.ports[2].state and 2 or 0) + " @
|
||||
" (gate.ports[3].state and 4 or 0) + " @
|
||||
" (gate.ports[4].state and 8 or 0) " @
|
||||
" gate.ports[idx]:setstate(true) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out3";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out4";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out5";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out6";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out7";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out8";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out9";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out10";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out11";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out12";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out13";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out14";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out15";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "15 0 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "In";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
||||
247
bricks/gen/newcode/Demux 5 Bit.cs
Normal file
247
bricks/gen/newcode/Demux 5 Bit.cs
Normal file
@@ -0,0 +1,247 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 5 Bit";
|
||||
logicUIName = "Demux 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 6 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[38].state then " @
|
||||
" local idx = 6 + " @
|
||||
" (gate.ports[1].state and 1 or 0) + " @
|
||||
" (gate.ports[2].state and 2 or 0) + " @
|
||||
" (gate.ports[3].state and 4 or 0) + " @
|
||||
" (gate.ports[4].state and 8 or 0) + " @
|
||||
" (gate.ports[5].state and 16 or 0) " @
|
||||
" gate.ports[idx]:setstate(true) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 38;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "31 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out0";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "29 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out1";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "27 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out2";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "25 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out3";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "23 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out4";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "21 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out5";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "19 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out6";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "17 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out7";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "15 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out8";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out9";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out10";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out11";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out12";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out13";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out14";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out15";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out16";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out17";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out18";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out19";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out20";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out21";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out22";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out23";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-17 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out24";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-19 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out25";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-21 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out26";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "-23 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out27";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "-25 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out28";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "-27 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out29";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "-29 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out30";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-31 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out31";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "31 0 0";
|
||||
logicPortDir[37] = 2;
|
||||
logicPortUIName[37] = "In";
|
||||
logicPortCauseUpdate[37] = true;
|
||||
|
||||
};
|
||||
414
bricks/gen/newcode/Demux 6 Bit.cs
Normal file
414
bricks/gen/newcode/Demux 6 Bit.cs
Normal file
@@ -0,0 +1,414 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 6 Bit";
|
||||
logicUIName = "Demux 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 7 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if gate.ports[71].state then " @
|
||||
" local idx = 7 + " @
|
||||
" (gate.ports[1].state and 1 or 0) + " @
|
||||
" (gate.ports[2].state and 2 or 0) + " @
|
||||
" (gate.ports[3].state and 4 or 0) + " @
|
||||
" (gate.ports[4].state and 8 or 0) + " @
|
||||
" (gate.ports[5].state and 16 or 0) + " @
|
||||
" (gate.ports[6].state and 32 or 0) " @
|
||||
" gate.ports[idx]:setstate(true) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" gate.ports[gate.laston]:setstate(false) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 71;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "63 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "61 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "59 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "57 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "55 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "53 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out5";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "51 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out6";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "49 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out7";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "47 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out8";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "45 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out9";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "43 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out10";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "41 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out11";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "39 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out12";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "37 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out13";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "35 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out14";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "33 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out15";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "31 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out16";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "29 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out17";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "27 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out18";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "25 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out19";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "23 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out20";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "21 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out21";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "19 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out22";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "17 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out23";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "15 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out24";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "13 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out25";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "11 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out26";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "9 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out27";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "7 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out28";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "5 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out29";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "3 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out30";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "1 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out31";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-1 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out32";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-3 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out33";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-5 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out34";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-7 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out35";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-9 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out36";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-11 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out37";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-13 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out38";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-15 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out39";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-17 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out40";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-19 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out41";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-21 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out42";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-23 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out43";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-25 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out44";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-27 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out45";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-29 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out46";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-31 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out47";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-33 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out48";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-35 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out49";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-37 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out50";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-39 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out51";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-41 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out52";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-43 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out53";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-45 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out54";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-47 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out55";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-49 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out56";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-51 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out57";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "-53 0 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "Out58";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "-55 0 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "Out59";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "-57 0 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "Out60";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "-59 0 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "Out61";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "-61 0 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "Out62";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "-63 0 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "Out63";
|
||||
|
||||
logicPortType[70] = 1;
|
||||
logicPortPos[70] = "63 0 0";
|
||||
logicPortDir[70] = 2;
|
||||
logicPortUIName[70] = "In";
|
||||
logicPortCauseUpdate[70] = true;
|
||||
|
||||
};
|
||||
53
bricks/gen/newcode/NAND 2 Bit.cs
Normal file
53
bricks/gen/newcode/NAND 2 Bit.cs
Normal file
@@ -0,0 +1,53 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 2 Bit";
|
||||
logicUIName = "NAND 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[3]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out";
|
||||
|
||||
};
|
||||
60
bricks/gen/newcode/NAND 3 Bit.cs
Normal file
60
bricks/gen/newcode/NAND 3 Bit.cs
Normal file
@@ -0,0 +1,60 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 3 Bit";
|
||||
logicUIName = "NAND 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[4]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out";
|
||||
|
||||
};
|
||||
67
bricks/gen/newcode/NAND 4 Bit.cs
Normal file
67
bricks/gen/newcode/NAND 4 Bit.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 4 Bit";
|
||||
logicUIName = "NAND 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[5]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out";
|
||||
|
||||
};
|
||||
74
bricks/gen/newcode/NAND 5 Bit.cs
Normal file
74
bricks/gen/newcode/NAND 5 Bit.cs
Normal file
@@ -0,0 +1,74 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 5 Bit";
|
||||
logicUIName = "NAND 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[6]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state and " @
|
||||
" gate.ports[5].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 6;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out";
|
||||
|
||||
};
|
||||
81
bricks/gen/newcode/NAND 6 Bit.cs
Normal file
81
bricks/gen/newcode/NAND 6 Bit.cs
Normal file
@@ -0,0 +1,81 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 6 Bit";
|
||||
logicUIName = "NAND 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[7]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state and " @
|
||||
" gate.ports[5].state and " @
|
||||
" gate.ports[6].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out";
|
||||
|
||||
};
|
||||
88
bricks/gen/newcode/NAND 7 Bit.cs
Normal file
88
bricks/gen/newcode/NAND 7 Bit.cs
Normal file
@@ -0,0 +1,88 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 7 Bit";
|
||||
logicUIName = "NAND 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[8]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state and " @
|
||||
" gate.ports[5].state and " @
|
||||
" gate.ports[6].state and " @
|
||||
" gate.ports[7].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out";
|
||||
|
||||
};
|
||||
95
bricks/gen/newcode/NAND 8 Bit.cs
Normal file
95
bricks/gen/newcode/NAND 8 Bit.cs
Normal file
@@ -0,0 +1,95 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNand8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NAND 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NAND 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NAND 8 Bit";
|
||||
logicUIName = "NAND 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[9]:setstate(not ( " @
|
||||
" gate.ports[1].state and " @
|
||||
" gate.ports[2].state and " @
|
||||
" gate.ports[3].state and " @
|
||||
" gate.ports[4].state and " @
|
||||
" gate.ports[5].state and " @
|
||||
" gate.ports[6].state and " @
|
||||
" gate.ports[7].state and " @
|
||||
" gate.ports[8].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out";
|
||||
|
||||
};
|
||||
53
bricks/gen/newcode/NOR 2 Bit.cs
Normal file
53
bricks/gen/newcode/NOR 2 Bit.cs
Normal file
@@ -0,0 +1,53 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 2 Bit";
|
||||
logicUIName = "NOR 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[3]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out";
|
||||
|
||||
};
|
||||
60
bricks/gen/newcode/NOR 3 Bit.cs
Normal file
60
bricks/gen/newcode/NOR 3 Bit.cs
Normal file
@@ -0,0 +1,60 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor3_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 3 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 3 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 3 Bit";
|
||||
logicUIName = "NOR 3 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "3 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[4]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state or " @
|
||||
" gate.ports[3].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "2 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "2 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "Out";
|
||||
|
||||
};
|
||||
67
bricks/gen/newcode/NOR 4 Bit.cs
Normal file
67
bricks/gen/newcode/NOR 4 Bit.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 4 Bit";
|
||||
logicUIName = "NOR 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[5]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state or " @
|
||||
" gate.ports[3].state or " @
|
||||
" gate.ports[4].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out";
|
||||
|
||||
};
|
||||
74
bricks/gen/newcode/NOR 5 Bit.cs
Normal file
74
bricks/gen/newcode/NOR 5 Bit.cs
Normal file
@@ -0,0 +1,74 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor5_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 5 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 5 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 5 Bit";
|
||||
logicUIName = "NOR 5 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "5 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[6]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state or " @
|
||||
" gate.ports[3].state or " @
|
||||
" gate.ports[4].state or " @
|
||||
" gate.ports[5].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 6;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "4 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "2 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-2 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-4 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "4 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out";
|
||||
|
||||
};
|
||||
81
bricks/gen/newcode/NOR 6 Bit.cs
Normal file
81
bricks/gen/newcode/NOR 6 Bit.cs
Normal file
@@ -0,0 +1,81 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor6_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 6 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 6 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 6 Bit";
|
||||
logicUIName = "NOR 6 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "6 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[7]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state or " @
|
||||
" gate.ports[3].state or " @
|
||||
" gate.ports[4].state or " @
|
||||
" gate.ports[5].state or " @
|
||||
" gate.ports[6].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "5 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "3 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-3 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-5 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "5 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out";
|
||||
|
||||
};
|
||||
88
bricks/gen/newcode/NOR 7 Bit.cs
Normal file
88
bricks/gen/newcode/NOR 7 Bit.cs
Normal file
@@ -0,0 +1,88 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 7 Bit";
|
||||
logicUIName = "NOR 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "7 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[8]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state or " @
|
||||
" gate.ports[3].state or " @
|
||||
" gate.ports[4].state or " @
|
||||
" gate.ports[5].state or " @
|
||||
" gate.ports[6].state or " @
|
||||
" gate.ports[7].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "6 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "4 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "2 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-2 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-4 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-6 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "6 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out";
|
||||
|
||||
};
|
||||
95
bricks/gen/newcode/NOR 8 Bit.cs
Normal file
95
bricks/gen/newcode/NOR 8 Bit.cs
Normal file
@@ -0,0 +1,95 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateNor8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/NOR 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/NOR 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "NOR 8 Bit";
|
||||
logicUIName = "NOR 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[9]:setstate(not ( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state or " @
|
||||
" gate.ports[3].state or " @
|
||||
" gate.ports[4].state or " @
|
||||
" gate.ports[5].state or " @
|
||||
" gate.ports[6].state or " @
|
||||
" gate.ports[7].state or " @
|
||||
" gate.ports[8].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "In2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "In3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "In4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "In5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "In6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 0 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "In7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out";
|
||||
|
||||
};
|
||||
53
bricks/gen/newcode/OR 2 Bit.cs
Normal file
53
bricks/gen/newcode/OR 2 Bit.cs
Normal file
@@ -0,0 +1,53 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_GateOr2_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/OR 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/OR 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Gates";
|
||||
uiName = "OR 2 Bit";
|
||||
logicUIName = "OR 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" gate.ports[3]:setstate(( " @
|
||||
" gate.ports[1].state or " @
|
||||
" gate.ports[2].state " @
|
||||
" )) " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 3;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "In0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "In1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "Out";
|
||||
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user