add rom brick

2021-05-12 21:20:24 -05:00
parent 7bd5fe696d
commit de586ff608
7 changed files with 1491 additions and 1 deletions
--- a/bricks/gen/newcode/ROM
+++ b/bricks/gen/newcode/ROM
@ -0,0 +1,118 @@
+
+datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
+	brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16.blb";
+	iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16";
+	
+	category = "Logic Bricks";
+	subCategory = "Special I/O";
+	uiName = "ROM 16x16";
+	logicUIName = "ROM 16x16";
+	logicUIDesc = "";
+	
+	hasPrint = 1;
+	printAspectRatio = "Logic";
+	
+	logicBrickSize = "16 16 1";
+	orientationFix = 3;
+	
+	isLogic = true;
+	isLogicGate = true;
+	isLogicInput = false;
+	
+	logicInit = 
+		"return function(gate) " @
+		"	gate.romdata = {} " @
+		"	for i = 0, 255 do " @
+		"		gate.romdata[i] = false " @
+		"	end " @
+		"end"
+	;
+	logicInput = 
+		"return function(gate, args) " @
+		"	local data = args[1] " @
+		"	for i = 1, #data do " @
+		"		local c = data:sub(i, i) " @
+		"		gate.romdata[i-1] = (c==\"1\") " @
+		"	end " @
+		"	Gate.queue(gate, 0) " @
+		"end"
+	;
+	logicUpdate = 
+		"return function(gate) " @
+		"	local addr = (Gate.getportstate(gate, 1) and 1 or 0) " @
+		"		+ (Gate.getportstate(gate, 2) and 2 or 0) " @
+		"		+ (Gate.getportstate(gate, 3) and 4 or 0) " @
+		"		+ (Gate.getportstate(gate, 4) and 8 or 0) " @
+		"		+ (Gate.getportstate(gate, 5) and 16 or 0) " @
+		"		+ (Gate.getportstate(gate, 6) and 32 or 0) " @
+		"		+ (Gate.getportstate(gate, 7) and 64 or 0) " @
+		"		+ (Gate.getportstate(gate, 8) and 128 or 0) " @
+		"	Gate.setportstate(gate, 9, gate.romdata[addr]) " @
+		"end"
+	;
+	logicGlobal = "";
+	
+	numLogicPorts = 9;
+	
+	isLogicRom = true;
+	logicRomY = 16;
+	logicRomX = 16;
+	
+	logicPortType[0] = 1;
+	logicPortPos[0] = "15 -15 0";
+	logicPortDir[0] = 3;
+	logicPortUIName[0] = "Addr0";
+	logicPortCauseUpdate[0] = true;
+	
+	logicPortType[1] = 1;
+	logicPortPos[1] = "13 -15 0";
+	logicPortDir[1] = 3;
+	logicPortUIName[1] = "Addr1";
+	logicPortCauseUpdate[1] = true;
+	
+	logicPortType[2] = 1;
+	logicPortPos[2] = "11 -15 0";
+	logicPortDir[2] = 3;
+	logicPortUIName[2] = "Addr2";
+	logicPortCauseUpdate[2] = true;
+	
+	logicPortType[3] = 1;
+	logicPortPos[3] = "9 -15 0";
+	logicPortDir[3] = 3;
+	logicPortUIName[3] = "Addr3";
+	logicPortCauseUpdate[3] = true;
+	
+	logicPortType[4] = 1;
+	logicPortPos[4] = "7 -15 0";
+	logicPortDir[4] = 3;
+	logicPortUIName[4] = "Addr4";
+	logicPortCauseUpdate[4] = true;
+	
+	logicPortType[5] = 1;
+	logicPortPos[5] = "5 -15 0";
+	logicPortDir[5] = 3;
+	logicPortUIName[5] = "Addr5";
+	logicPortCauseUpdate[5] = true;
+	
+	logicPortType[6] = 1;
+	logicPortPos[6] = "3 -15 0";
+	logicPortDir[6] = 3;
+	logicPortUIName[6] = "Addr6";
+	logicPortCauseUpdate[6] = true;
+	
+	logicPortType[7] = 1;
+	logicPortPos[7] = "1 -15 0";
+	logicPortDir[7] = 3;
+	logicPortUIName[7] = "Addr7";
+	logicPortCauseUpdate[7] = true;
+	
+	logicPortType[8] = 0;
+	logicPortPos[8] = "15 15 0";
+	logicPortDir[8] = 1;
+	logicPortUIName[8] = "Out";
+	
+};
+
+function LogicGate_Rom16x16_Data::Logic_onAdd(%data, %brick) {
+	lualogic_rom_updatedata(%brick);
+}