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more wires, fix rom

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This commit is contained in:
Redo0 2021-07-24 15:32:14 -05:00
parent 4501eea02e
commit 519a887dca
30 changed files with 171 additions and 80 deletions
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1
bricks/execall.cs
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@ -7,6 +7,7 @@ exec("./gates/diode.cs");
exec("./gates/NOT.cs");
exec("./gates/verticalDiode.cs");
exec("./gates/verticalNOT.cs");
exec("./gates/srlatch.cs");
exec("./inputs/switch.cs");
exec("./inputs/button.cs");

52
bricks/gates/srlatch.cs Normal file
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@ -0,0 +1,52 @@
datablock fxDtsBrickData(LogicGate_GateSRLatch_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/AND 2 Bit.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/AND 2 Bit";
category = "Logic Bricks";
subCategory = "Gates";
uiName = "SR Latch";
logicUIName = "SR Latch";
logicUIDesc = "";
hasPrint = 1;
printAspectRatio = "Logic";
logicBrickSize = "2 1 1";
orientationFix = 3;
isLogic = true;
isLogicGate = true;
isLogicInput = false;
logicInit = "";
logicInput = "";
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 1)~=0 then Gate.setportstate(gate, 3, 0) " @
" elseif Gate.getportstate(gate, 2)~=0 then Gate.setportstate(gate, 3, 1) " @
" end " @
"end"
;
logicGlobal = "";
numLogicPorts = 3;
logicPortType[0] = 1;
logicPortPos[0] = "1 0 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "R";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "-1 0 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "S";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 0;
logicPortPos[2] = "1 0 0";
logicPortDir[2] = 1;
logicPortUIName[2] = "Out";
};

7
bricks/gen/execall.cs
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@ -26,13 +26,12 @@ exec("./newcode/Wire 1x25f.cs");
exec("./newcode/Wire 1x26f.cs");
exec("./newcode/Wire 1x27f.cs");
exec("./newcode/Wire 1x28f.cs");
exec("./newcode/Wire 1x39f.cs");
exec("./newcode/Wire 1x29f.cs");
exec("./newcode/Wire 1x30f.cs");
exec("./newcode/Wire 1x31f.cs");
exec("./newcode/Wire 1x32f.cs");
exec("./newcode/Wire 1x48f.cs");
exec("./newcode/Wire 1x64f.cs");
exec("./newcode/Wire 1x1f.cs");
exec("./newcode/Wire 1x1x2f.cs");
exec("./newcode/Wire 1x1.cs");
exec("./newcode/Wire 1x1x4f.cs");
@ -82,10 +81,14 @@ exec("./newcode/Wire 1x1x47f.cs");
exec("./newcode/Wire 1x1x16.cs");
exec("./newcode/Wire 1x1x56f.cs");
exec("./newcode/Wire 1x1x64f.cs");
exec("./newcode/Wire 1x1x65f.cs");
exec("./newcode/Wire 1x1x22.cs");
exec("./newcode/Wire 1x1x24.cs");
exec("./newcode/Wire 1x1x80f.cs");
exec("./newcode/Wire 1x1x32.cs");
exec("./newcode/Wire 1x1x112f.cs");
exec("./newcode/Wire 1x1x128f.cs");
exec("./newcode/Wire 1x1x48.cs");
exec("./newcode/Wire 1x1x160f.cs");
exec("./newcode/Wire 1x2x5f.cs");
exec("./newcode/Wire 64x64f.cs");

2
bricks/gen/newbricks/Wire 1x1x112f.blb Normal file
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@ -0,0 +1,2 @@
1 1 112
BRICK

2
bricks/gen/newbricks/Wire 1x1x22.blb Normal file
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@ -0,0 +1,2 @@
1 1 66
BRICK

2
bricks/gen/newbricks/Wire 1x1x48.blb Normal file
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@ -0,0 +1,2 @@
1 1 144
BRICK

2
bricks/gen/newbricks/Wire 1x1x65f.blb Normal file
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@ -0,0 +1,2 @@
1 1 65
BRICK

2
bricks/gen/newbricks/Wire 1x29f.blb Normal file
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@ -0,0 +1,2 @@
1 29 1
BRICK

2
bricks/gen/newbricks/Wire 1x39f.blb
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@ -1,2 +0,0 @@
1 39 1
BRICK

10
bricks/gen/newcode/ROM 16x16.cs
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@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 10) then " @
" if Gate.getportstate(gate, 10)~=0 then " @
" Gate.setportstate(gate, 9, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -67,49 +67,41 @@ datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
logicPortPos[0] = "15 -15 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "13 -15 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "11 -15 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "9 -15 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "7 -15 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "5 -15 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 1;
logicPortPos[6] = "3 -15 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortCauseUpdate[6] = true;
logicPortType[7] = 1;
logicPortPos[7] = "1 -15 0";
logicPortDir[7] = 3;
logicPortUIName[7] = "Addr7";
logicPortCauseUpdate[7] = true;
logicPortType[8] = 0;
logicPortPos[8] = "15 15 0";

9
bricks/gen/newcode/ROM 16x8.cs
View File

@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom16x8_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 9) then " @
" if Gate.getportstate(gate, 9)~=0 then " @
" Gate.setportstate(gate, 8, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -66,43 +66,36 @@ datablock fxDtsBrickData(LogicGate_Rom16x8_Data){
logicPortPos[0] = "15 -7 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "13 -7 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "11 -7 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "9 -7 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "7 -7 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "5 -7 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 1;
logicPortPos[6] = "3 -7 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortCauseUpdate[6] = true;
logicPortType[7] = 0;
logicPortPos[7] = "15 7 0";

11
bricks/gen/newcode/ROM 32x16.cs
View File

@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom32x16_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 11) then " @
" if Gate.getportstate(gate, 11)~=0 then " @
" Gate.setportstate(gate, 10, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -68,55 +68,46 @@ datablock fxDtsBrickData(LogicGate_Rom32x16_Data){
logicPortPos[0] = "31 -15 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "29 -15 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "27 -15 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "25 -15 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "23 -15 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "21 -15 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 1;
logicPortPos[6] = "19 -15 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortCauseUpdate[6] = true;
logicPortType[7] = 1;
logicPortPos[7] = "17 -15 0";
logicPortDir[7] = 3;
logicPortUIName[7] = "Addr7";
logicPortCauseUpdate[7] = true;
logicPortType[8] = 1;
logicPortPos[8] = "15 -15 0";
logicPortDir[8] = 3;
logicPortUIName[8] = "Addr8";
logicPortCauseUpdate[8] = true;
logicPortType[9] = 0;
logicPortPos[9] = "31 15 0";

12
bricks/gen/newcode/ROM 32x32.cs
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@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 12) then " @
" if Gate.getportstate(gate, 12)~=0 then " @
" Gate.setportstate(gate, 11, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -69,61 +69,51 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
logicPortPos[0] = "31 -31 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "29 -31 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "27 -31 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "25 -31 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "23 -31 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "21 -31 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 1;
logicPortPos[6] = "19 -31 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortCauseUpdate[6] = true;
logicPortType[7] = 1;
logicPortPos[7] = "17 -31 0";
logicPortDir[7] = 3;
logicPortUIName[7] = "Addr7";
logicPortCauseUpdate[7] = true;
logicPortType[8] = 1;
logicPortPos[8] = "15 -31 0";
logicPortDir[8] = 3;
logicPortUIName[8] = "Addr8";
logicPortCauseUpdate[8] = true;
logicPortType[9] = 1;
logicPortPos[9] = "13 -31 0";
logicPortDir[9] = 3;
logicPortUIName[9] = "Addr9";
logicPortCauseUpdate[9] = true;
logicPortType[10] = 0;
logicPortPos[10] = "31 31 0";

6
bricks/gen/newcode/ROM 4x4.cs
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@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom4x4_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 6) then " @
" if Gate.getportstate(gate, 6)~=0 then " @
" Gate.setportstate(gate, 5, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -63,25 +63,21 @@ datablock fxDtsBrickData(LogicGate_Rom4x4_Data){
logicPortPos[0] = "3 -3 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "1 -3 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "-1 -3 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "-3 -3 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 0;
logicPortPos[4] = "3 3 0";

7
bricks/gen/newcode/ROM 8x4.cs
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@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom8x4_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 7) then " @
" if Gate.getportstate(gate, 7)~=0 then " @
" Gate.setportstate(gate, 6, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -64,31 +64,26 @@ datablock fxDtsBrickData(LogicGate_Rom8x4_Data){
logicPortPos[0] = "7 -3 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "5 -3 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "3 -3 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "1 -3 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "-1 -3 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 0;
logicPortPos[5] = "7 3 0";

8
bricks/gen/newcode/ROM 8x8.cs
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@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom8x8_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 8) then " @
" if Gate.getportstate(gate, 8)~=0 then " @
" Gate.setportstate(gate, 7, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@ -65,37 +65,31 @@ datablock fxDtsBrickData(LogicGate_Rom8x8_Data){
logicPortPos[0] = "7 -7 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "5 -7 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "3 -7 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "1 -7 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "-1 -7 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "-3 -7 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 0;
logicPortPos[6] = "7 7 0";

2
bricks/gen/newcode/Wire 1x1f.cs
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@ -4,7 +4,7 @@ datablock fxDtsBrickData(LogicWire_1x1f_Data){
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x1f";
category = "Logic Bricks";
subCategory = "Wires Vertical";
subCategory = "Wires Horizontal";
uiName = "Wire 1x1f";
logicBrickSize = "1 1 1";

19
bricks/gen/newcode/Wire 1x1x112f.cs Normal file
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@ -0,0 +1,19 @@
datablock fxDtsBrickData(LogicWire_1x1x112f_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Wire 1x1x112f.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x1x112f";
category = "Logic Bricks";
subCategory = "Wires Vertical";
uiName = "Wire 1x1x112f";
logicBrickSize = "1 1 112";
orientationFix = 0;
isLogic = true;
isLogicWire = true;
};

19
bricks/gen/newcode/Wire 1x1x22.cs Normal file
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@ -0,0 +1,19 @@
datablock fxDtsBrickData(LogicWire_1x1x22_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Wire 1x1x22.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x1x22";
category = "Logic Bricks";
subCategory = "Wires Vertical";
uiName = "Wire 1x1x22";
logicBrickSize = "1 1 66";
orientationFix = 0;
isLogic = true;
isLogicWire = true;
};

19
bricks/gen/newcode/Wire 1x1x48.cs Normal file
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@ -0,0 +1,19 @@
datablock fxDtsBrickData(LogicWire_1x1x48_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Wire 1x1x48.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x1x48";
category = "Logic Bricks";
subCategory = "Wires Vertical";
uiName = "Wire 1x1x48";
logicBrickSize = "1 1 144";
orientationFix = 0;
isLogic = true;
isLogicWire = true;
};

19
bricks/gen/newcode/Wire 1x1x65f.cs Normal file
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@ -0,0 +1,19 @@
datablock fxDtsBrickData(LogicWire_1x1x65f_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Wire 1x1x65f.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x1x65f";
category = "Logic Bricks";
subCategory = "Wires Vertical";
uiName = "Wire 1x1x65f";
logicBrickSize = "1 1 65";
orientationFix = 0;
isLogic = true;
isLogicWire = true;
};

19
bricks/gen/newcode/Wire 1x29f.cs Normal file
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@ -0,0 +1,19 @@
datablock fxDtsBrickData(LogicWire_1x29f_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Wire 1x29f.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x29f";
category = "Logic Bricks";
subCategory = "Wires Horizontal";
uiName = "Wire 1x29f";
logicBrickSize = "1 29 1";
orientationFix = 0;
isLogic = true;
isLogicWire = true;
};

19
bricks/gen/newcode/Wire 1x39f.cs
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@ -1,19 +0,0 @@
datablock fxDtsBrickData(LogicWire_1x39f_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Wire 1x39f.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Wire 1x39f";
category = "Logic Bricks";
subCategory = "Wires Horizontal";
uiName = "Wire 1x39f";
logicBrickSize = "1 39 1";
orientationFix = 0;
isLogic = true;
isLogicWire = true;
};

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0
bricks/special/rom2.cs Normal file
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