new rom
This commit is contained in:
parent
519a887dca
commit
fe8057f4ec
@ -382,10 +382,40 @@ exec("./newcode/Demux 6 Bit.cs");
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exec("./newcode/Demux 6 Bit Vertical.cs");
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exec("./newcode/Mux 6 Bit.cs");
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exec("./newcode/Mux 6 Bit Vertical.cs");
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exec("./newcode/Demux 7 Bit.cs");
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exec("./newcode/Demux 7 Bit Vertical.cs");
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exec("./newcode/Mux 7 Bit.cs");
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exec("./newcode/Mux 7 Bit Vertical.cs");
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exec("./newcode/Demux 8 Bit.cs");
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exec("./newcode/Demux 8 Bit Vertical.cs");
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exec("./newcode/Mux 8 Bit.cs");
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exec("./newcode/Mux 8 Bit Vertical.cs");
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exec("./newcode/ROM 4x4.cs");
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exec("./newcode/ROM 8x4.cs");
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exec("./newcode/ROM 4x4x4.cs");
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exec("./newcode/ROM 8x2x8.cs");
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exec("./newcode/ROM 8x8.cs");
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exec("./newcode/ROM 16x8.cs");
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exec("./newcode/ROM 8x8x4.cs");
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exec("./newcode/ROM 8x8x8.cs");
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exec("./newcode/ROM 16x4x16.cs");
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exec("./newcode/ROM 32x2x32.cs");
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exec("./newcode/ROM 64x1x64.cs");
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exec("./newcode/ROM 16x16.cs");
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exec("./newcode/ROM 32x16.cs");
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exec("./newcode/ROM 32x32.cs");
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exec("./newcode/ROM 16x16x4.cs");
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exec("./newcode/ROM 16x16x8.cs");
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exec("./newcode/ROM 16x16x16.cs");
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exec("./newcode/ROM 32x8x32.cs");
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exec("./newcode/ROM 64x4x64.cs");
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exec("./newcode/ROM 32x32x8.cs");
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exec("./newcode/ROM 32x32x16.cs");
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exec("./newcode/ROM 32x32x32.cs");
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exec("./newcode/ROM 64x16x64.cs");
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exec("./newcode/ROM 64x64x8.cs");
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exec("./newcode/ROM 64x64x16.cs");
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exec("./newcode/ROM 64x64x32.cs");
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exec("./newcode/ROM 64x64x64.cs");
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exec("./newcode/Adder 1 Bit.cs");
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exec("./newcode/Adder 2 Bit.cs");
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exec("./newcode/Adder 4 Bit.cs");
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exec("./newcode/Adder 8 Bit.cs");
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exec("./newcode/Adder 16 Bit.cs");
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exec("./newcode/Adder 32 Bit.cs");
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752
bricks/gen/newbricks/Adder 1 Bit.blb
Normal file
752
bricks/gen/newbricks/Adder 1 Bit.blb
Normal file
@ -0,0 +1,752 @@
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2 2 1
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SPECIAL
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bb
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bb
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1
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0 0 0
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2 2 1
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COVERAGE:
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1 : 4
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1 : 4
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1 : 2
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1 : 2
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1 : 2
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1 : 2
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----------------top quads:
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1
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TEX:PRINT
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POSITION:
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1 1 0.5
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1 -1 0.5
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-1 -1 0.5
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-1 1 0.5
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UV COORDS:
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1 0
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1 1
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0 1
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0 0
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NORMALS:
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0 0 1
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0 0 1
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0 0 1
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0 0 1
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----------------bottom quads:
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5
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TEX:BOTTOMLOOP
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POSITION:
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0.5 -0.5 -0.5
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0.5 0.5 -0.5
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-0.5 0.5 -0.5
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-0.5 -0.5 -0.5
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UV COORDS:
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0 0
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0 1
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1 1
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1 0
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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-1 -1 -0.5
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1 -1 -0.5
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0.5 -0.5 -0.5
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-0.5 -0.5 -0.5
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UV COORDS:
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-0.5 0
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1.5 0
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1 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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1 1 -0.5
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-1 1 -0.5
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-0.5 0.5 -0.5
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0.5 0.5 -0.5
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UV COORDS:
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-0.5 0
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1.5 0
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1 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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1 -1 -0.5
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1 1 -0.5
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0.5 0.5 -0.5
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0.5 -0.5 -0.5
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UV COORDS:
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-0.5 0
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1.5 0
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1 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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TEX:BOTTOMEDGE
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POSITION:
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-1 1 -0.5
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-1 -1 -0.5
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-0.5 -0.5 -0.5
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-0.5 0.5 -0.5
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UV COORDS:
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-0.5 0
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1.5 0
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1 0.5
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0 0.5
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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0 0 -1
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----------------north quads:
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6
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TEX:SIDE
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POSITION:
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-1 1 0.5
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-1 1 -0.5
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1 1 -0.5
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1 1 0.5
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UV COORDS:
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1 -0.0859375
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1 1.0859375
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0 1.0859375
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0 -0.0859375
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NORMALS:
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0 1 0
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0 1 0
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0 1 0
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0 1 0
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TEX:SIDE
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POSITION:
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0.82 1.25 -0.24
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0.18 1.25 -0.24
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0.1 1 -0.3
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0.9 1 -0.3
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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-0 0.095561 -0.995424
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-0 0.095561 -0.995424
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-0 0.095561 -0.995424
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-0 0.095561 -0.995424
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TEX:SIDE
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POSITION:
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0.82 1.25 -0.24
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0.82 1.25 0.24
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0.18 1.25 0.24
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0.18 1.25 -0.24
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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0 1 0
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0 1 0
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0 1 0
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0 1 0
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TEX:SIDE
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POSITION:
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0.18 1.25 0.24
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0.82 1.25 0.24
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0.9 1 0.3
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0.1 1 0.3
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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-0 0.095561 0.995424
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-0 0.095561 0.995424
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-0 0.095561 0.995424
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-0 0.095561 0.995424
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TEX:SIDE
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POSITION:
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0.18 1.25 -0.24
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0.18 1.25 0.24
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0.1 1 0.3
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0.1 1 -0.3
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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-0.952424 0.304776 0
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-0.952424 0.304776 0
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-0.952424 0.304776 0
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-0.952424 0.304776 0
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TEX:SIDE
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POSITION:
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0.82 1.25 0.24
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0.82 1.25 -0.24
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0.9 1 -0.3
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0.9 1 0.3
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UV COORDS:
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0.5 0.5
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0.5 0.5
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0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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0.952424 0.304776 0
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0.952424 0.304776 0
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0.952424 0.304776 0
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0.952424 0.304776 0
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----------------east quads:
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6
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TEX:SIDE
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POSITION:
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1 -1 0.5
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1 1 0.5
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1 1 -0.5
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1 -1 -0.5
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UV COORDS:
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0 -0.0859375
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||||
1 -0.0859375
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1 1.0859375
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0 1.0859375
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NORMALS:
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1 0 0
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1 0 0
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||||
1 0 0
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||||
1 0 0
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||||
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TEX:SIDE
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POSITION:
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1.14 -0.9 -0.3
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1.14 -0.1 -0.3
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1 -0.1 -0.3
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1 -0.9 -0.3
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UV COORDS:
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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0 0 -1
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0 0 -1
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0 0 -1
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||||
0 0 -1
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TEX:SIDE
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POSITION:
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1.14 -0.9 -0.3
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1.14 -0.9 0.3
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||||
1.14 -0.1 0.3
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1.14 -0.1 -0.3
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UV COORDS:
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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0.5 0.5
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COLORS:
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1 1 1 1
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1 1 1 1
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1 1 1 1
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1 1 1 1
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NORMALS:
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1 0 0
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1 0 0
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1 0 0
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||||
1 0 0
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||||
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TEX:SIDE
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POSITION:
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1.14 -0.1 0.3
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||||
1.14 -0.9 0.3
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||||
1 -0.9 0.3
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||||
1 -0.1 0.3
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||||
UV COORDS:
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
COLORS:
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1 1 1 1
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||||
1 1 1 1
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||||
1 1 1 1
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||||
1 1 1 1
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||||
NORMALS:
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0 0 1
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||||
0 0 1
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||||
0 0 1
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||||
0 0 1
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||||
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TEX:SIDE
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POSITION:
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||||
1.14 -0.1 -0.3
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||||
1.14 -0.1 0.3
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||||
1 -0.1 0.3
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||||
1 -0.1 -0.3
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||||
UV COORDS:
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
COLORS:
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||||
1 1 1 1
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||||
1 1 1 1
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||||
1 1 1 1
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||||
1 1 1 1
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||||
NORMALS:
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||||
0 1 0
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||||
0 1 0
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||||
0 1 0
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||||
0 1 0
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||||
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||||
TEX:SIDE
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||||
POSITION:
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||||
1.14 -0.9 0.3
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||||
1.14 -0.9 -0.3
|
||||
1 -0.9 -0.3
|
||||
1 -0.9 0.3
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||||
UV COORDS:
|
||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
0.5 0.5
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||||
COLORS:
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||||
1 1 1 1
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||||
1 1 1 1
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||||
1 1 1 1
|
||||
1 1 1 1
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||||
NORMALS:
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||||
0 -1 0
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||||
0 -1 0
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||||
0 -1 0
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||||
0 -1 0
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----------------south quads:
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11
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TEX:SIDE
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POSITION:
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1 -1 0.5
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||||
1 -1 -0.5
|
||||
-1 -1 -0.5
|
||||
-1 -1 0.5
|
||||
UV COORDS:
|
||||
1 -0.0859375
|
||||
1 1.0859375
|
||||
0 1.0859375
|
||||
0 -0.0859375
|
||||
NORMALS:
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
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||||
0.1 -1.14 -0.3
|
||||
0.9 -1.14 -0.3
|
||||
0.9 -1 -0.3
|
||||
0.1 -1 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
0.1 -1.14 -0.3
|
||||
0.1 -1.14 0.3
|
||||
0.9 -1.14 0.3
|
||||
0.9 -1.14 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
0.9 -1.14 0.3
|
||||
0.1 -1.14 0.3
|
||||
0.1 -1 0.3
|
||||
0.9 -1 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 0 1
|
||||
0 0 1
|
||||
0 0 1
|
||||
0 0 1
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
0.9 -1.14 -0.3
|
||||
0.9 -1.14 0.3
|
||||
0.9 -1 0.3
|
||||
0.9 -1 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
1 0 0
|
||||
1 0 0
|
||||
1 0 0
|
||||
1 0 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
0.1 -1.14 0.3
|
||||
0.1 -1.14 -0.3
|
||||
0.1 -1 -0.3
|
||||
0.1 -1 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-0.9 -1.14 -0.3
|
||||
-0.1 -1.14 -0.3
|
||||
-0.1 -1 -0.3
|
||||
-0.9 -1 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-0.9 -1.14 -0.3
|
||||
-0.9 -1.14 0.3
|
||||
-0.1 -1.14 0.3
|
||||
-0.1 -1.14 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
0 -1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-0.1 -1.14 0.3
|
||||
-0.9 -1.14 0.3
|
||||
-0.9 -1 0.3
|
||||
-0.1 -1 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 0 1
|
||||
0 0 1
|
||||
0 0 1
|
||||
0 0 1
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-0.1 -1.14 -0.3
|
||||
-0.1 -1.14 0.3
|
||||
-0.1 -1 0.3
|
||||
-0.1 -1 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
1 0 0
|
||||
1 0 0
|
||||
1 0 0
|
||||
1 0 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-0.9 -1.14 0.3
|
||||
-0.9 -1.14 -0.3
|
||||
-0.9 -1 -0.3
|
||||
-0.9 -1 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
----------------west quads:
|
||||
6
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-1 -1 -0.5
|
||||
-1 1 -0.5
|
||||
-1 1 0.5
|
||||
-1 -1 0.5
|
||||
UV COORDS:
|
||||
1 1.0859375
|
||||
0 1.0859375
|
||||
0 -0.0859375
|
||||
1 -0.0859375
|
||||
NORMALS:
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-1.25 -0.18 -0.24
|
||||
-1.25 -0.82 -0.24
|
||||
-1 -0.9 -0.3
|
||||
-1 -0.1 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.095561 0 -0.995424
|
||||
-0.095561 0 -0.995424
|
||||
-0.095561 0 -0.995424
|
||||
-0.095561 0 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-1.25 -0.18 -0.24
|
||||
-1.25 -0.18 0.24
|
||||
-1.25 -0.82 0.24
|
||||
-1.25 -0.82 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
-1 0 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-1.25 -0.82 0.24
|
||||
-1.25 -0.18 0.24
|
||||
-1 -0.1 0.3
|
||||
-1 -0.9 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.095561 0 0.995424
|
||||
-0.095561 0 0.995424
|
||||
-0.095561 0 0.995424
|
||||
-0.095561 0 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-1.25 -0.82 -0.24
|
||||
-1.25 -0.82 0.24
|
||||
-1 -0.9 0.3
|
||||
-1 -0.9 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.304776 -0.952424 0
|
||||
-0.304776 -0.952424 0
|
||||
-0.304776 -0.952424 0
|
||||
-0.304776 -0.952424 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
-1.25 -0.18 0.24
|
||||
-1.25 -0.18 -0.24
|
||||
-1 -0.1 -0.3
|
||||
-1 -0.1 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.304776 0.952424 0
|
||||
-0.304776 0.952424 0
|
||||
-0.304776 0.952424 0
|
||||
-0.304776 0.952424 0
|
||||
----------------omni quads:
|
||||
0
|
5702
bricks/gen/newbricks/Adder 16 Bit.blb
Normal file
5702
bricks/gen/newbricks/Adder 16 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
10982
bricks/gen/newbricks/Adder 32 Bit.blb
Normal file
10982
bricks/gen/newbricks/Adder 32 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
1742
bricks/gen/newbricks/Adder 4 Bit.blb
Normal file
1742
bricks/gen/newbricks/Adder 4 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
3062
bricks/gen/newbricks/Adder 8 Bit.blb
Normal file
3062
bricks/gen/newbricks/Adder 8 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
15270
bricks/gen/newbricks/Demux 7 Bit Vertical.blb
Normal file
15270
bricks/gen/newbricks/Demux 7 Bit Vertical.blb
Normal file
File diff suppressed because it is too large
Load Diff
15143
bricks/gen/newbricks/Demux 7 Bit.blb
Normal file
15143
bricks/gen/newbricks/Demux 7 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
29588
bricks/gen/newbricks/Demux 8 Bit Vertical.blb
Normal file
29588
bricks/gen/newbricks/Demux 8 Bit Vertical.blb
Normal file
File diff suppressed because it is too large
Load Diff
29333
bricks/gen/newbricks/Demux 8 Bit.blb
Normal file
29333
bricks/gen/newbricks/Demux 8 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
15380
bricks/gen/newbricks/Mux 7 Bit Vertical.blb
Normal file
15380
bricks/gen/newbricks/Mux 7 Bit Vertical.blb
Normal file
File diff suppressed because it is too large
Load Diff
15253
bricks/gen/newbricks/Mux 7 Bit.blb
Normal file
15253
bricks/gen/newbricks/Mux 7 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
29698
bricks/gen/newbricks/Mux 8 Bit Vertical.blb
Normal file
29698
bricks/gen/newbricks/Mux 8 Bit Vertical.blb
Normal file
File diff suppressed because it is too large
Load Diff
29443
bricks/gen/newbricks/Mux 8 Bit.blb
Normal file
29443
bricks/gen/newbricks/Mux 8 Bit.blb
Normal file
File diff suppressed because it is too large
Load Diff
2980
bricks/gen/newbricks/ROM 16x16x16.blb
Normal file
2980
bricks/gen/newbricks/ROM 16x16x16.blb
Normal file
File diff suppressed because it is too large
Load Diff
1660
bricks/gen/newbricks/ROM 16x16x4.blb
Normal file
1660
bricks/gen/newbricks/ROM 16x16x4.blb
Normal file
File diff suppressed because it is too large
Load Diff
2100
bricks/gen/newbricks/ROM 16x16x8.blb
Normal file
2100
bricks/gen/newbricks/ROM 16x16x8.blb
Normal file
File diff suppressed because it is too large
Load Diff
2736
bricks/gen/newbricks/ROM 16x4x16.blb
Normal file
2736
bricks/gen/newbricks/ROM 16x4x16.blb
Normal file
File diff suppressed because it is too large
Load Diff
4492
bricks/gen/newbricks/ROM 32x2x32.blb
Normal file
4492
bricks/gen/newbricks/ROM 32x2x32.blb
Normal file
File diff suppressed because it is too large
Load Diff
3232
bricks/gen/newbricks/ROM 32x32x16.blb
Normal file
3232
bricks/gen/newbricks/ROM 32x32x16.blb
Normal file
File diff suppressed because it is too large
Load Diff
4992
bricks/gen/newbricks/ROM 32x32x32.blb
Normal file
4992
bricks/gen/newbricks/ROM 32x32x32.blb
Normal file
File diff suppressed because it is too large
Load Diff
@ -183,7 +183,7 @@ NORMALS:
|
||||
0 0 -1
|
||||
0 0 -1
|
||||
----------------north quads:
|
||||
6
|
||||
41
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
@ -311,6 +311,776 @@ NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
14.82 16.25 -0.24
|
||||
14.18 16.25 -0.24
|
||||
14.1 16 -0.3
|
||||
14.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
14.82 16.25 -0.24
|
||||
14.82 16.25 0.24
|
||||
14.18 16.25 0.24
|
||||
14.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
14.18 16.25 0.24
|
||||
14.82 16.25 0.24
|
||||
14.9 16 0.3
|
||||
14.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
14.18 16.25 -0.24
|
||||
14.18 16.25 0.24
|
||||
14.1 16 0.3
|
||||
14.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
14.82 16.25 0.24
|
||||
14.82 16.25 -0.24
|
||||
14.9 16 -0.3
|
||||
14.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
13.82 16.25 -0.24
|
||||
13.18 16.25 -0.24
|
||||
13.1 16 -0.3
|
||||
13.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
13.82 16.25 -0.24
|
||||
13.82 16.25 0.24
|
||||
13.18 16.25 0.24
|
||||
13.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
13.18 16.25 0.24
|
||||
13.82 16.25 0.24
|
||||
13.9 16 0.3
|
||||
13.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
13.18 16.25 -0.24
|
||||
13.18 16.25 0.24
|
||||
13.1 16 0.3
|
||||
13.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
13.82 16.25 0.24
|
||||
13.82 16.25 -0.24
|
||||
13.9 16 -0.3
|
||||
13.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
12.82 16.25 -0.24
|
||||
12.18 16.25 -0.24
|
||||
12.1 16 -0.3
|
||||
12.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
12.82 16.25 -0.24
|
||||
12.82 16.25 0.24
|
||||
12.18 16.25 0.24
|
||||
12.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
12.18 16.25 0.24
|
||||
12.82 16.25 0.24
|
||||
12.9 16 0.3
|
||||
12.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
12.18 16.25 -0.24
|
||||
12.18 16.25 0.24
|
||||
12.1 16 0.3
|
||||
12.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
12.82 16.25 0.24
|
||||
12.82 16.25 -0.24
|
||||
12.9 16 -0.3
|
||||
12.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
11.82 16.25 -0.24
|
||||
11.18 16.25 -0.24
|
||||
11.1 16 -0.3
|
||||
11.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
11.82 16.25 -0.24
|
||||
11.82 16.25 0.24
|
||||
11.18 16.25 0.24
|
||||
11.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
11.18 16.25 0.24
|
||||
11.82 16.25 0.24
|
||||
11.9 16 0.3
|
||||
11.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
11.18 16.25 -0.24
|
||||
11.18 16.25 0.24
|
||||
11.1 16 0.3
|
||||
11.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
11.82 16.25 0.24
|
||||
11.82 16.25 -0.24
|
||||
11.9 16 -0.3
|
||||
11.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
10.82 16.25 -0.24
|
||||
10.18 16.25 -0.24
|
||||
10.1 16 -0.3
|
||||
10.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
10.82 16.25 -0.24
|
||||
10.82 16.25 0.24
|
||||
10.18 16.25 0.24
|
||||
10.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
10.18 16.25 0.24
|
||||
10.82 16.25 0.24
|
||||
10.9 16 0.3
|
||||
10.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
10.18 16.25 -0.24
|
||||
10.18 16.25 0.24
|
||||
10.1 16 0.3
|
||||
10.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
10.82 16.25 0.24
|
||||
10.82 16.25 -0.24
|
||||
10.9 16 -0.3
|
||||
10.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
9.82 16.25 -0.24
|
||||
9.18 16.25 -0.24
|
||||
9.1 16 -0.3
|
||||
9.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
9.82 16.25 -0.24
|
||||
9.82 16.25 0.24
|
||||
9.18 16.25 0.24
|
||||
9.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
9.18 16.25 0.24
|
||||
9.82 16.25 0.24
|
||||
9.9 16 0.3
|
||||
9.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
9.18 16.25 -0.24
|
||||
9.18 16.25 0.24
|
||||
9.1 16 0.3
|
||||
9.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
9.82 16.25 0.24
|
||||
9.82 16.25 -0.24
|
||||
9.9 16 -0.3
|
||||
9.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
8.82 16.25 -0.24
|
||||
8.18 16.25 -0.24
|
||||
8.1 16 -0.3
|
||||
8.9 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
-0 0.095561 -0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
8.82 16.25 -0.24
|
||||
8.82 16.25 0.24
|
||||
8.18 16.25 0.24
|
||||
8.18 16.25 -0.24
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
0 1 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
8.18 16.25 0.24
|
||||
8.82 16.25 0.24
|
||||
8.9 16 0.3
|
||||
8.1 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
-0 0.095561 0.995424
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
8.18 16.25 -0.24
|
||||
8.18 16.25 0.24
|
||||
8.1 16 0.3
|
||||
8.1 16 -0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
-0.952424 0.304776 0
|
||||
|
||||
TEX:SIDE
|
||||
POSITION:
|
||||
8.82 16.25 0.24
|
||||
8.82 16.25 -0.24
|
||||
8.9 16 -0.3
|
||||
8.9 16 0.3
|
||||
UV COORDS:
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
0.5 0.5
|
||||
COLORS:
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
1 1 1 1
|
||||
NORMALS:
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
0.952424 0.304776 0
|
||||
----------------east quads:
|
||||
6
|
||||
|
4724
bricks/gen/newbricks/ROM 32x8x32.blb
Normal file
4724
bricks/gen/newbricks/ROM 32x8x32.blb
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
8480
bricks/gen/newbricks/ROM 64x16x64.blb
Normal file
8480
bricks/gen/newbricks/ROM 64x16x64.blb
Normal file
File diff suppressed because it is too large
Load Diff
7993
bricks/gen/newbricks/ROM 64x1x64.blb
Normal file
7993
bricks/gen/newbricks/ROM 64x1x64.blb
Normal file
File diff suppressed because it is too large
Load Diff
8236
bricks/gen/newbricks/ROM 64x4x64.blb
Normal file
8236
bricks/gen/newbricks/ROM 64x4x64.blb
Normal file
File diff suppressed because it is too large
Load Diff
3516
bricks/gen/newbricks/ROM 64x64x16.blb
Normal file
3516
bricks/gen/newbricks/ROM 64x64x16.blb
Normal file
File diff suppressed because it is too large
Load Diff
5276
bricks/gen/newbricks/ROM 64x64x32.blb
Normal file
5276
bricks/gen/newbricks/ROM 64x64x32.blb
Normal file
File diff suppressed because it is too large
Load Diff
8796
bricks/gen/newbricks/ROM 64x64x64.blb
Normal file
8796
bricks/gen/newbricks/ROM 64x64x64.blb
Normal file
File diff suppressed because it is too large
Load Diff
2636
bricks/gen/newbricks/ROM 64x64x8.blb
Normal file
2636
bricks/gen/newbricks/ROM 64x64x8.blb
Normal file
File diff suppressed because it is too large
Load Diff
1632
bricks/gen/newbricks/ROM 8x2x8.blb
Normal file
1632
bricks/gen/newbricks/ROM 8x2x8.blb
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
1864
bricks/gen/newbricks/ROM 8x8x8.blb
Normal file
1864
bricks/gen/newbricks/ROM 8x8x8.blb
Normal file
File diff suppressed because it is too large
Load Diff
68
bricks/gen/newcode/Adder 1 Bit.cs
Normal file
68
bricks/gen/newcode/Adder 1 Bit.cs
Normal file
@ -0,0 +1,68 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Adder1Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Adder 1 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Adder 1 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Adder 1 Bit";
|
||||
logicUIName = "Adder 1 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "2 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
"local val = ( " @
|
||||
" ( Gate.getportstate(gate, 1) + Gate.getportstate(gate, 2) + Gate.getportstate(gate, 4)) " @
|
||||
") " @
|
||||
"if val >= 2 then val = val-2; Gate.setportstate(gate, 5, 1); else Gate.setportstate(gate, 5, 0) end " @
|
||||
"if val >= 1 then val = val-1; Gate.setportstate(gate, 3, 1); else Gate.setportstate(gate, 3, 0) end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 5;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "1 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "-1 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "B0";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "1 1 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "O0";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -1 0";
|
||||
logicPortDir[3] = 2;
|
||||
logicPortUIName[3] = "CIn";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "-1 -1 0";
|
||||
logicPortDir[4] = 0;
|
||||
logicPortUIName[4] = "COut";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
};
|
353
bricks/gen/newcode/Adder 16 Bit.cs
Normal file
353
bricks/gen/newcode/Adder 16 Bit.cs
Normal file
@ -0,0 +1,353 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Adder16Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Adder 16 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Adder 16 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Adder 16 Bit";
|
||||
logicUIName = "Adder 16 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
"local val = ( " @
|
||||
" ( Gate.getportstate(gate, 1) + Gate.getportstate(gate, 17) + Gate.getportstate(gate, 49)) " @
|
||||
" + ((Gate.getportstate(gate, 2) + Gate.getportstate(gate, 18)) * 2) " @
|
||||
" + ((Gate.getportstate(gate, 3) + Gate.getportstate(gate, 19)) * 4) " @
|
||||
" + ((Gate.getportstate(gate, 4) + Gate.getportstate(gate, 20)) * 8) " @
|
||||
" + ((Gate.getportstate(gate, 5) + Gate.getportstate(gate, 21)) * 16) " @
|
||||
" + ((Gate.getportstate(gate, 6) + Gate.getportstate(gate, 22)) * 32) " @
|
||||
" + ((Gate.getportstate(gate, 7) + Gate.getportstate(gate, 23)) * 64) " @
|
||||
" + ((Gate.getportstate(gate, 8) + Gate.getportstate(gate, 24)) * 128) " @
|
||||
" + ((Gate.getportstate(gate, 9) + Gate.getportstate(gate, 25)) * 256) " @
|
||||
" + ((Gate.getportstate(gate, 10) + Gate.getportstate(gate, 26)) * 512) " @
|
||||
" + ((Gate.getportstate(gate, 11) + Gate.getportstate(gate, 27)) * 1024) " @
|
||||
" + ((Gate.getportstate(gate, 12) + Gate.getportstate(gate, 28)) * 2048) " @
|
||||
" + ((Gate.getportstate(gate, 13) + Gate.getportstate(gate, 29)) * 4096) " @
|
||||
" + ((Gate.getportstate(gate, 14) + Gate.getportstate(gate, 30)) * 8192) " @
|
||||
" + ((Gate.getportstate(gate, 15) + Gate.getportstate(gate, 31)) * 16384) " @
|
||||
" + ((Gate.getportstate(gate, 16) + Gate.getportstate(gate, 32)) * 32768) " @
|
||||
") " @
|
||||
"if val >= 65536 then val = val-65536; Gate.setportstate(gate, 50, 1); else Gate.setportstate(gate, 50, 0) end " @
|
||||
"if val >= 32768 then val = val-32768; Gate.setportstate(gate, 48, 1); else Gate.setportstate(gate, 48, 0) end " @
|
||||
"if val >= 16384 then val = val-16384; Gate.setportstate(gate, 47, 1); else Gate.setportstate(gate, 47, 0) end " @
|
||||
"if val >= 8192 then val = val-8192; Gate.setportstate(gate, 46, 1); else Gate.setportstate(gate, 46, 0) end " @
|
||||
"if val >= 4096 then val = val-4096; Gate.setportstate(gate, 45, 1); else Gate.setportstate(gate, 45, 0) end " @
|
||||
"if val >= 2048 then val = val-2048; Gate.setportstate(gate, 44, 1); else Gate.setportstate(gate, 44, 0) end " @
|
||||
"if val >= 1024 then val = val-1024; Gate.setportstate(gate, 43, 1); else Gate.setportstate(gate, 43, 0) end " @
|
||||
"if val >= 512 then val = val-512; Gate.setportstate(gate, 42, 1); else Gate.setportstate(gate, 42, 0) end " @
|
||||
"if val >= 256 then val = val-256; Gate.setportstate(gate, 41, 1); else Gate.setportstate(gate, 41, 0) end " @
|
||||
"if val >= 128 then val = val-128; Gate.setportstate(gate, 40, 1); else Gate.setportstate(gate, 40, 0) end " @
|
||||
"if val >= 64 then val = val-64; Gate.setportstate(gate, 39, 1); else Gate.setportstate(gate, 39, 0) end " @
|
||||
"if val >= 32 then val = val-32; Gate.setportstate(gate, 38, 1); else Gate.setportstate(gate, 38, 0) end " @
|
||||
"if val >= 16 then val = val-16; Gate.setportstate(gate, 37, 1); else Gate.setportstate(gate, 37, 0) end " @
|
||||
"if val >= 8 then val = val-8; Gate.setportstate(gate, 36, 1); else Gate.setportstate(gate, 36, 0) end " @
|
||||
"if val >= 4 then val = val-4; Gate.setportstate(gate, 35, 1); else Gate.setportstate(gate, 35, 0) end " @
|
||||
"if val >= 2 then val = val-2; Gate.setportstate(gate, 34, 1); else Gate.setportstate(gate, 34, 0) end " @
|
||||
"if val >= 1 then val = val-1; Gate.setportstate(gate, 33, 1); else Gate.setportstate(gate, 33, 0) end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 50;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "11 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "A10";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "9 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "A11";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "A12";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "5 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "A13";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "3 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "A14";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "1 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "A15";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-1 -1 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "B0";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-3 -1 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "B1";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-5 -1 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "B2";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-7 -1 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "B3";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "-9 -1 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "B4";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-11 -1 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "B5";
|
||||
logicPortCauseUpdate[21] = true;
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-13 -1 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "B6";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-15 -1 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "B7";
|
||||
logicPortCauseUpdate[23] = true;
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-17 -1 0";
|
||||
logicPortDir[24] = 3;
|
||||
logicPortUIName[24] = "B8";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-19 -1 0";
|
||||
logicPortDir[25] = 3;
|
||||
logicPortUIName[25] = "B9";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-21 -1 0";
|
||||
logicPortDir[26] = 3;
|
||||
logicPortUIName[26] = "B10";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-23 -1 0";
|
||||
logicPortDir[27] = 3;
|
||||
logicPortUIName[27] = "B11";
|
||||
logicPortCauseUpdate[27] = true;
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-25 -1 0";
|
||||
logicPortDir[28] = 3;
|
||||
logicPortUIName[28] = "B12";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-27 -1 0";
|
||||
logicPortDir[29] = 3;
|
||||
logicPortUIName[29] = "B13";
|
||||
logicPortCauseUpdate[29] = true;
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-29 -1 0";
|
||||
logicPortDir[30] = 3;
|
||||
logicPortUIName[30] = "B14";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-31 -1 0";
|
||||
logicPortDir[31] = 3;
|
||||
logicPortUIName[31] = "B15";
|
||||
logicPortCauseUpdate[31] = true;
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "31 1 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O0";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "29 1 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O1";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "27 1 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O2";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "25 1 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O3";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "23 1 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O4";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "21 1 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O5";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "19 1 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O6";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "17 1 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O7";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "15 1 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O8";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "13 1 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O9";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "11 1 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "O10";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "9 1 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "O11";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "7 1 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "O12";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "5 1 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "O13";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "3 1 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "O14";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "1 1 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "O15";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "31 -1 0";
|
||||
logicPortDir[48] = 2;
|
||||
logicPortUIName[48] = "CIn";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-31 -1 0";
|
||||
logicPortDir[49] = 0;
|
||||
logicPortUIName[49] = "COut";
|
||||
logicPortCauseUpdate[49] = true;
|
||||
|
||||
};
|
87
bricks/gen/newcode/Adder 2 Bit.cs
Normal file
87
bricks/gen/newcode/Adder 2 Bit.cs
Normal file
@ -0,0 +1,87 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Adder2Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Adder 2 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Adder 2 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Adder 2 Bit";
|
||||
logicUIName = "Adder 2 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
"local val = ( " @
|
||||
" ( Gate.getportstate(gate, 1) + Gate.getportstate(gate, 3) + Gate.getportstate(gate, 7)) " @
|
||||
" + ((Gate.getportstate(gate, 2) + Gate.getportstate(gate, 4)) * 2) " @
|
||||
") " @
|
||||
"if val >= 4 then val = val-4; Gate.setportstate(gate, 8, 1); else Gate.setportstate(gate, 8, 0) end " @
|
||||
"if val >= 2 then val = val-2; Gate.setportstate(gate, 6, 1); else Gate.setportstate(gate, 6, 0) end " @
|
||||
"if val >= 1 then val = val-1; Gate.setportstate(gate, 5, 1); else Gate.setportstate(gate, 5, 0) end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 8;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "B0";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "B1";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 1 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "O0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 1 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "O1";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -1 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "CIn";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 -1 0";
|
||||
logicPortDir[7] = 0;
|
||||
logicPortUIName[7] = "COut";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
};
|
657
bricks/gen/newcode/Adder 32 Bit.cs
Normal file
657
bricks/gen/newcode/Adder 32 Bit.cs
Normal file
@ -0,0 +1,657 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Adder32Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Adder 32 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Adder 32 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Adder 32 Bit";
|
||||
logicUIName = "Adder 32 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
"local val = ( " @
|
||||
" ( Gate.getportstate(gate, 1) + Gate.getportstate(gate, 33) + Gate.getportstate(gate, 97)) " @
|
||||
" + ((Gate.getportstate(gate, 2) + Gate.getportstate(gate, 34)) * 2) " @
|
||||
" + ((Gate.getportstate(gate, 3) + Gate.getportstate(gate, 35)) * 4) " @
|
||||
" + ((Gate.getportstate(gate, 4) + Gate.getportstate(gate, 36)) * 8) " @
|
||||
" + ((Gate.getportstate(gate, 5) + Gate.getportstate(gate, 37)) * 16) " @
|
||||
" + ((Gate.getportstate(gate, 6) + Gate.getportstate(gate, 38)) * 32) " @
|
||||
" + ((Gate.getportstate(gate, 7) + Gate.getportstate(gate, 39)) * 64) " @
|
||||
" + ((Gate.getportstate(gate, 8) + Gate.getportstate(gate, 40)) * 128) " @
|
||||
" + ((Gate.getportstate(gate, 9) + Gate.getportstate(gate, 41)) * 256) " @
|
||||
" + ((Gate.getportstate(gate, 10) + Gate.getportstate(gate, 42)) * 512) " @
|
||||
" + ((Gate.getportstate(gate, 11) + Gate.getportstate(gate, 43)) * 1024) " @
|
||||
" + ((Gate.getportstate(gate, 12) + Gate.getportstate(gate, 44)) * 2048) " @
|
||||
" + ((Gate.getportstate(gate, 13) + Gate.getportstate(gate, 45)) * 4096) " @
|
||||
" + ((Gate.getportstate(gate, 14) + Gate.getportstate(gate, 46)) * 8192) " @
|
||||
" + ((Gate.getportstate(gate, 15) + Gate.getportstate(gate, 47)) * 16384) " @
|
||||
" + ((Gate.getportstate(gate, 16) + Gate.getportstate(gate, 48)) * 32768) " @
|
||||
" + ((Gate.getportstate(gate, 17) + Gate.getportstate(gate, 49)) * 65536) " @
|
||||
" + ((Gate.getportstate(gate, 18) + Gate.getportstate(gate, 50)) * 131072) " @
|
||||
" + ((Gate.getportstate(gate, 19) + Gate.getportstate(gate, 51)) * 262144) " @
|
||||
" + ((Gate.getportstate(gate, 20) + Gate.getportstate(gate, 52)) * 524288) " @
|
||||
" + ((Gate.getportstate(gate, 21) + Gate.getportstate(gate, 53)) * 1048576) " @
|
||||
" + ((Gate.getportstate(gate, 22) + Gate.getportstate(gate, 54)) * 2097152) " @
|
||||
" + ((Gate.getportstate(gate, 23) + Gate.getportstate(gate, 55)) * 4194304) " @
|
||||
" + ((Gate.getportstate(gate, 24) + Gate.getportstate(gate, 56)) * 8388608) " @
|
||||
" + ((Gate.getportstate(gate, 25) + Gate.getportstate(gate, 57)) * 16777216) " @
|
||||
" + ((Gate.getportstate(gate, 26) + Gate.getportstate(gate, 58)) * 33554432) " @
|
||||
" + ((Gate.getportstate(gate, 27) + Gate.getportstate(gate, 59)) * 67108864) " @
|
||||
" + ((Gate.getportstate(gate, 28) + Gate.getportstate(gate, 60)) * 134217728) " @
|
||||
" + ((Gate.getportstate(gate, 29) + Gate.getportstate(gate, 61)) * 268435456) " @
|
||||
" + ((Gate.getportstate(gate, 30) + Gate.getportstate(gate, 62)) * 536870912) " @
|
||||
" + ((Gate.getportstate(gate, 31) + Gate.getportstate(gate, 63)) * 1073741824) " @
|
||||
" + ((Gate.getportstate(gate, 32) + Gate.getportstate(gate, 64)) * 2147483648) " @
|
||||
") " @
|
||||
"if val >= 4294967296 then val = val-4294967296; Gate.setportstate(gate, 98, 1); else Gate.setportstate(gate, 98, 0) end " @
|
||||
"if val >= 2147483648 then val = val-2147483648; Gate.setportstate(gate, 96, 1); else Gate.setportstate(gate, 96, 0) end " @
|
||||
"if val >= 1073741824 then val = val-1073741824; Gate.setportstate(gate, 95, 1); else Gate.setportstate(gate, 95, 0) end " @
|
||||
"if val >= 536870912 then val = val-536870912; Gate.setportstate(gate, 94, 1); else Gate.setportstate(gate, 94, 0) end " @
|
||||
"if val >= 268435456 then val = val-268435456; Gate.setportstate(gate, 93, 1); else Gate.setportstate(gate, 93, 0) end " @
|
||||
"if val >= 134217728 then val = val-134217728; Gate.setportstate(gate, 92, 1); else Gate.setportstate(gate, 92, 0) end " @
|
||||
"if val >= 67108864 then val = val-67108864; Gate.setportstate(gate, 91, 1); else Gate.setportstate(gate, 91, 0) end " @
|
||||
"if val >= 33554432 then val = val-33554432; Gate.setportstate(gate, 90, 1); else Gate.setportstate(gate, 90, 0) end " @
|
||||
"if val >= 16777216 then val = val-16777216; Gate.setportstate(gate, 89, 1); else Gate.setportstate(gate, 89, 0) end " @
|
||||
"if val >= 8388608 then val = val-8388608; Gate.setportstate(gate, 88, 1); else Gate.setportstate(gate, 88, 0) end " @
|
||||
"if val >= 4194304 then val = val-4194304; Gate.setportstate(gate, 87, 1); else Gate.setportstate(gate, 87, 0) end " @
|
||||
"if val >= 2097152 then val = val-2097152; Gate.setportstate(gate, 86, 1); else Gate.setportstate(gate, 86, 0) end " @
|
||||
"if val >= 1048576 then val = val-1048576; Gate.setportstate(gate, 85, 1); else Gate.setportstate(gate, 85, 0) end " @
|
||||
"if val >= 524288 then val = val-524288; Gate.setportstate(gate, 84, 1); else Gate.setportstate(gate, 84, 0) end " @
|
||||
"if val >= 262144 then val = val-262144; Gate.setportstate(gate, 83, 1); else Gate.setportstate(gate, 83, 0) end " @
|
||||
"if val >= 131072 then val = val-131072; Gate.setportstate(gate, 82, 1); else Gate.setportstate(gate, 82, 0) end " @
|
||||
"if val >= 65536 then val = val-65536; Gate.setportstate(gate, 81, 1); else Gate.setportstate(gate, 81, 0) end " @
|
||||
"if val >= 32768 then val = val-32768; Gate.setportstate(gate, 80, 1); else Gate.setportstate(gate, 80, 0) end " @
|
||||
"if val >= 16384 then val = val-16384; Gate.setportstate(gate, 79, 1); else Gate.setportstate(gate, 79, 0) end " @
|
||||
"if val >= 8192 then val = val-8192; Gate.setportstate(gate, 78, 1); else Gate.setportstate(gate, 78, 0) end " @
|
||||
"if val >= 4096 then val = val-4096; Gate.setportstate(gate, 77, 1); else Gate.setportstate(gate, 77, 0) end " @
|
||||
"if val >= 2048 then val = val-2048; Gate.setportstate(gate, 76, 1); else Gate.setportstate(gate, 76, 0) end " @
|
||||
"if val >= 1024 then val = val-1024; Gate.setportstate(gate, 75, 1); else Gate.setportstate(gate, 75, 0) end " @
|
||||
"if val >= 512 then val = val-512; Gate.setportstate(gate, 74, 1); else Gate.setportstate(gate, 74, 0) end " @
|
||||
"if val >= 256 then val = val-256; Gate.setportstate(gate, 73, 1); else Gate.setportstate(gate, 73, 0) end " @
|
||||
"if val >= 128 then val = val-128; Gate.setportstate(gate, 72, 1); else Gate.setportstate(gate, 72, 0) end " @
|
||||
"if val >= 64 then val = val-64; Gate.setportstate(gate, 71, 1); else Gate.setportstate(gate, 71, 0) end " @
|
||||
"if val >= 32 then val = val-32; Gate.setportstate(gate, 70, 1); else Gate.setportstate(gate, 70, 0) end " @
|
||||
"if val >= 16 then val = val-16; Gate.setportstate(gate, 69, 1); else Gate.setportstate(gate, 69, 0) end " @
|
||||
"if val >= 8 then val = val-8; Gate.setportstate(gate, 68, 1); else Gate.setportstate(gate, 68, 0) end " @
|
||||
"if val >= 4 then val = val-4; Gate.setportstate(gate, 67, 1); else Gate.setportstate(gate, 67, 0) end " @
|
||||
"if val >= 2 then val = val-2; Gate.setportstate(gate, 66, 1); else Gate.setportstate(gate, 66, 0) end " @
|
||||
"if val >= 1 then val = val-1; Gate.setportstate(gate, 65, 1); else Gate.setportstate(gate, 65, 0) end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 98;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "A10";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "A11";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "39 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "A12";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "37 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "A13";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "35 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "A14";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "33 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "A15";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "31 -1 0";
|
||||
logicPortDir[16] = 3;
|
||||
logicPortUIName[16] = "A16";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "29 -1 0";
|
||||
logicPortDir[17] = 3;
|
||||
logicPortUIName[17] = "A17";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "27 -1 0";
|
||||
logicPortDir[18] = 3;
|
||||
logicPortUIName[18] = "A18";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "25 -1 0";
|
||||
logicPortDir[19] = 3;
|
||||
logicPortUIName[19] = "A19";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "23 -1 0";
|
||||
logicPortDir[20] = 3;
|
||||
logicPortUIName[20] = "A20";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "21 -1 0";
|
||||
logicPortDir[21] = 3;
|
||||
logicPortUIName[21] = "A21";
|
||||
logicPortCauseUpdate[21] = true;
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "19 -1 0";
|
||||
logicPortDir[22] = 3;
|
||||
logicPortUIName[22] = "A22";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "17 -1 0";
|
||||
logicPortDir[23] = 3;
|
||||
logicPortUIName[23] = "A23";
|
||||
logicPortCauseUpdate[23] = true;
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "15 -1 0";
|
||||
logicPortDir[24] = 3;
|
||||
logicPortUIName[24] = "A24";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "13 -1 0";
|
||||
logicPortDir[25] = 3;
|
||||
logicPortUIName[25] = "A25";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "11 -1 0";
|
||||
logicPortDir[26] = 3;
|
||||
logicPortUIName[26] = "A26";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "9 -1 0";
|
||||
logicPortDir[27] = 3;
|
||||
logicPortUIName[27] = "A27";
|
||||
logicPortCauseUpdate[27] = true;
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "7 -1 0";
|
||||
logicPortDir[28] = 3;
|
||||
logicPortUIName[28] = "A28";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "5 -1 0";
|
||||
logicPortDir[29] = 3;
|
||||
logicPortUIName[29] = "A29";
|
||||
logicPortCauseUpdate[29] = true;
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "3 -1 0";
|
||||
logicPortDir[30] = 3;
|
||||
logicPortUIName[30] = "A30";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "1 -1 0";
|
||||
logicPortDir[31] = 3;
|
||||
logicPortUIName[31] = "A31";
|
||||
logicPortCauseUpdate[31] = true;
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "-1 -1 0";
|
||||
logicPortDir[32] = 3;
|
||||
logicPortUIName[32] = "B0";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "-3 -1 0";
|
||||
logicPortDir[33] = 3;
|
||||
logicPortUIName[33] = "B1";
|
||||
logicPortCauseUpdate[33] = true;
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "-5 -1 0";
|
||||
logicPortDir[34] = 3;
|
||||
logicPortUIName[34] = "B2";
|
||||
logicPortCauseUpdate[34] = true;
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "-7 -1 0";
|
||||
logicPortDir[35] = 3;
|
||||
logicPortUIName[35] = "B3";
|
||||
logicPortCauseUpdate[35] = true;
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "-9 -1 0";
|
||||
logicPortDir[36] = 3;
|
||||
logicPortUIName[36] = "B4";
|
||||
logicPortCauseUpdate[36] = true;
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "-11 -1 0";
|
||||
logicPortDir[37] = 3;
|
||||
logicPortUIName[37] = "B5";
|
||||
logicPortCauseUpdate[37] = true;
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "-13 -1 0";
|
||||
logicPortDir[38] = 3;
|
||||
logicPortUIName[38] = "B6";
|
||||
logicPortCauseUpdate[38] = true;
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "-15 -1 0";
|
||||
logicPortDir[39] = 3;
|
||||
logicPortUIName[39] = "B7";
|
||||
logicPortCauseUpdate[39] = true;
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "-17 -1 0";
|
||||
logicPortDir[40] = 3;
|
||||
logicPortUIName[40] = "B8";
|
||||
logicPortCauseUpdate[40] = true;
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "-19 -1 0";
|
||||
logicPortDir[41] = 3;
|
||||
logicPortUIName[41] = "B9";
|
||||
logicPortCauseUpdate[41] = true;
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "-21 -1 0";
|
||||
logicPortDir[42] = 3;
|
||||
logicPortUIName[42] = "B10";
|
||||
logicPortCauseUpdate[42] = true;
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "-23 -1 0";
|
||||
logicPortDir[43] = 3;
|
||||
logicPortUIName[43] = "B11";
|
||||
logicPortCauseUpdate[43] = true;
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "-25 -1 0";
|
||||
logicPortDir[44] = 3;
|
||||
logicPortUIName[44] = "B12";
|
||||
logicPortCauseUpdate[44] = true;
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "-27 -1 0";
|
||||
logicPortDir[45] = 3;
|
||||
logicPortUIName[45] = "B13";
|
||||
logicPortCauseUpdate[45] = true;
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "-29 -1 0";
|
||||
logicPortDir[46] = 3;
|
||||
logicPortUIName[46] = "B14";
|
||||
logicPortCauseUpdate[46] = true;
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "-31 -1 0";
|
||||
logicPortDir[47] = 3;
|
||||
logicPortUIName[47] = "B15";
|
||||
logicPortCauseUpdate[47] = true;
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "-33 -1 0";
|
||||
logicPortDir[48] = 3;
|
||||
logicPortUIName[48] = "B16";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "-35 -1 0";
|
||||
logicPortDir[49] = 3;
|
||||
logicPortUIName[49] = "B17";
|
||||
logicPortCauseUpdate[49] = true;
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "-37 -1 0";
|
||||
logicPortDir[50] = 3;
|
||||
logicPortUIName[50] = "B18";
|
||||
logicPortCauseUpdate[50] = true;
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "-39 -1 0";
|
||||
logicPortDir[51] = 3;
|
||||
logicPortUIName[51] = "B19";
|
||||
logicPortCauseUpdate[51] = true;
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "-41 -1 0";
|
||||
logicPortDir[52] = 3;
|
||||
logicPortUIName[52] = "B20";
|
||||
logicPortCauseUpdate[52] = true;
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "-43 -1 0";
|
||||
logicPortDir[53] = 3;
|
||||
logicPortUIName[53] = "B21";
|
||||
logicPortCauseUpdate[53] = true;
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "-45 -1 0";
|
||||
logicPortDir[54] = 3;
|
||||
logicPortUIName[54] = "B22";
|
||||
logicPortCauseUpdate[54] = true;
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "-47 -1 0";
|
||||
logicPortDir[55] = 3;
|
||||
logicPortUIName[55] = "B23";
|
||||
logicPortCauseUpdate[55] = true;
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "-49 -1 0";
|
||||
logicPortDir[56] = 3;
|
||||
logicPortUIName[56] = "B24";
|
||||
logicPortCauseUpdate[56] = true;
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "-51 -1 0";
|
||||
logicPortDir[57] = 3;
|
||||
logicPortUIName[57] = "B25";
|
||||
logicPortCauseUpdate[57] = true;
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "-53 -1 0";
|
||||
logicPortDir[58] = 3;
|
||||
logicPortUIName[58] = "B26";
|
||||
logicPortCauseUpdate[58] = true;
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "-55 -1 0";
|
||||
logicPortDir[59] = 3;
|
||||
logicPortUIName[59] = "B27";
|
||||
logicPortCauseUpdate[59] = true;
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "-57 -1 0";
|
||||
logicPortDir[60] = 3;
|
||||
logicPortUIName[60] = "B28";
|
||||
logicPortCauseUpdate[60] = true;
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "-59 -1 0";
|
||||
logicPortDir[61] = 3;
|
||||
logicPortUIName[61] = "B29";
|
||||
logicPortCauseUpdate[61] = true;
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "-61 -1 0";
|
||||
logicPortDir[62] = 3;
|
||||
logicPortUIName[62] = "B30";
|
||||
logicPortCauseUpdate[62] = true;
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "-63 -1 0";
|
||||
logicPortDir[63] = 3;
|
||||
logicPortUIName[63] = "B31";
|
||||
logicPortCauseUpdate[63] = true;
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "63 1 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "O0";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "61 1 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "O1";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "59 1 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "O2";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "57 1 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "O3";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "55 1 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "O4";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "53 1 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "O5";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "51 1 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "O6";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "49 1 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "O7";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "47 1 0";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "O8";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "45 1 0";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "O9";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "43 1 0";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "O10";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "41 1 0";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "O11";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "39 1 0";
|
||||
logicPortDir[76] = 1;
|
||||
logicPortUIName[76] = "O12";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "37 1 0";
|
||||
logicPortDir[77] = 1;
|
||||
logicPortUIName[77] = "O13";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "35 1 0";
|
||||
logicPortDir[78] = 1;
|
||||
logicPortUIName[78] = "O14";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "33 1 0";
|
||||
logicPortDir[79] = 1;
|
||||
logicPortUIName[79] = "O15";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "31 1 0";
|
||||
logicPortDir[80] = 1;
|
||||
logicPortUIName[80] = "O16";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "29 1 0";
|
||||
logicPortDir[81] = 1;
|
||||
logicPortUIName[81] = "O17";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "27 1 0";
|
||||
logicPortDir[82] = 1;
|
||||
logicPortUIName[82] = "O18";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "25 1 0";
|
||||
logicPortDir[83] = 1;
|
||||
logicPortUIName[83] = "O19";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "23 1 0";
|
||||
logicPortDir[84] = 1;
|
||||
logicPortUIName[84] = "O20";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "21 1 0";
|
||||
logicPortDir[85] = 1;
|
||||
logicPortUIName[85] = "O21";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "19 1 0";
|
||||
logicPortDir[86] = 1;
|
||||
logicPortUIName[86] = "O22";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "17 1 0";
|
||||
logicPortDir[87] = 1;
|
||||
logicPortUIName[87] = "O23";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "15 1 0";
|
||||
logicPortDir[88] = 1;
|
||||
logicPortUIName[88] = "O24";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "13 1 0";
|
||||
logicPortDir[89] = 1;
|
||||
logicPortUIName[89] = "O25";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "11 1 0";
|
||||
logicPortDir[90] = 1;
|
||||
logicPortUIName[90] = "O26";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "9 1 0";
|
||||
logicPortDir[91] = 1;
|
||||
logicPortUIName[91] = "O27";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "7 1 0";
|
||||
logicPortDir[92] = 1;
|
||||
logicPortUIName[92] = "O28";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "5 1 0";
|
||||
logicPortDir[93] = 1;
|
||||
logicPortUIName[93] = "O29";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "3 1 0";
|
||||
logicPortDir[94] = 1;
|
||||
logicPortUIName[94] = "O30";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "1 1 0";
|
||||
logicPortDir[95] = 1;
|
||||
logicPortUIName[95] = "O31";
|
||||
|
||||
logicPortType[96] = 1;
|
||||
logicPortPos[96] = "63 -1 0";
|
||||
logicPortDir[96] = 2;
|
||||
logicPortUIName[96] = "CIn";
|
||||
logicPortCauseUpdate[96] = true;
|
||||
|
||||
logicPortType[97] = 0;
|
||||
logicPortPos[97] = "-63 -1 0";
|
||||
logicPortDir[97] = 0;
|
||||
logicPortUIName[97] = "COut";
|
||||
logicPortCauseUpdate[97] = true;
|
||||
|
||||
};
|
125
bricks/gen/newcode/Adder 4 Bit.cs
Normal file
125
bricks/gen/newcode/Adder 4 Bit.cs
Normal file
@ -0,0 +1,125 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Adder4Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Adder 4 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Adder 4 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Adder 4 Bit";
|
||||
logicUIName = "Adder 4 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
"local val = ( " @
|
||||
" ( Gate.getportstate(gate, 1) + Gate.getportstate(gate, 5) + Gate.getportstate(gate, 13)) " @
|
||||
" + ((Gate.getportstate(gate, 2) + Gate.getportstate(gate, 6)) * 2) " @
|
||||
" + ((Gate.getportstate(gate, 3) + Gate.getportstate(gate, 7)) * 4) " @
|
||||
" + ((Gate.getportstate(gate, 4) + Gate.getportstate(gate, 8)) * 8) " @
|
||||
") " @
|
||||
"if val >= 16 then val = val-16; Gate.setportstate(gate, 14, 1); else Gate.setportstate(gate, 14, 0) end " @
|
||||
"if val >= 8 then val = val-8; Gate.setportstate(gate, 12, 1); else Gate.setportstate(gate, 12, 0) end " @
|
||||
"if val >= 4 then val = val-4; Gate.setportstate(gate, 11, 1); else Gate.setportstate(gate, 11, 0) end " @
|
||||
"if val >= 2 then val = val-2; Gate.setportstate(gate, 10, 1); else Gate.setportstate(gate, 10, 0) end " @
|
||||
"if val >= 1 then val = val-1; Gate.setportstate(gate, 9, 1); else Gate.setportstate(gate, 9, 0) end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 14;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "B0";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "B1";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "-5 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "B2";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-7 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "B3";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "7 1 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "5 1 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "3 1 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "1 1 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "CIn";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-7 -1 0";
|
||||
logicPortDir[13] = 0;
|
||||
logicPortUIName[13] = "COut";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
};
|
201
bricks/gen/newcode/Adder 8 Bit.cs
Normal file
201
bricks/gen/newcode/Adder 8 Bit.cs
Normal file
@ -0,0 +1,201 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Adder8Bit_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Adder 8 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Adder 8 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Math";
|
||||
uiName = "Adder 8 Bit";
|
||||
logicUIName = "Adder 8 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
"local val = ( " @
|
||||
" ( Gate.getportstate(gate, 1) + Gate.getportstate(gate, 9) + Gate.getportstate(gate, 25)) " @
|
||||
" + ((Gate.getportstate(gate, 2) + Gate.getportstate(gate, 10)) * 2) " @
|
||||
" + ((Gate.getportstate(gate, 3) + Gate.getportstate(gate, 11)) * 4) " @
|
||||
" + ((Gate.getportstate(gate, 4) + Gate.getportstate(gate, 12)) * 8) " @
|
||||
" + ((Gate.getportstate(gate, 5) + Gate.getportstate(gate, 13)) * 16) " @
|
||||
" + ((Gate.getportstate(gate, 6) + Gate.getportstate(gate, 14)) * 32) " @
|
||||
" + ((Gate.getportstate(gate, 7) + Gate.getportstate(gate, 15)) * 64) " @
|
||||
" + ((Gate.getportstate(gate, 8) + Gate.getportstate(gate, 16)) * 128) " @
|
||||
") " @
|
||||
"if val >= 256 then val = val-256; Gate.setportstate(gate, 26, 1); else Gate.setportstate(gate, 26, 0) end " @
|
||||
"if val >= 128 then val = val-128; Gate.setportstate(gate, 24, 1); else Gate.setportstate(gate, 24, 0) end " @
|
||||
"if val >= 64 then val = val-64; Gate.setportstate(gate, 23, 1); else Gate.setportstate(gate, 23, 0) end " @
|
||||
"if val >= 32 then val = val-32; Gate.setportstate(gate, 22, 1); else Gate.setportstate(gate, 22, 0) end " @
|
||||
"if val >= 16 then val = val-16; Gate.setportstate(gate, 21, 1); else Gate.setportstate(gate, 21, 0) end " @
|
||||
"if val >= 8 then val = val-8; Gate.setportstate(gate, 20, 1); else Gate.setportstate(gate, 20, 0) end " @
|
||||
"if val >= 4 then val = val-4; Gate.setportstate(gate, 19, 1); else Gate.setportstate(gate, 19, 0) end " @
|
||||
"if val >= 2 then val = val-2; Gate.setportstate(gate, 18, 1); else Gate.setportstate(gate, 18, 0) end " @
|
||||
"if val >= 1 then val = val-1; Gate.setportstate(gate, 17, 1); else Gate.setportstate(gate, 17, 0) end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 26;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -1 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 -1 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-1 -1 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "B0";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-3 -1 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "B1";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-5 -1 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "B2";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "-7 -1 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "B3";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-9 -1 0";
|
||||
logicPortDir[12] = 3;
|
||||
logicPortUIName[12] = "B4";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-11 -1 0";
|
||||
logicPortDir[13] = 3;
|
||||
logicPortUIName[13] = "B5";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-13 -1 0";
|
||||
logicPortDir[14] = 3;
|
||||
logicPortUIName[14] = "B6";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-15 -1 0";
|
||||
logicPortDir[15] = 3;
|
||||
logicPortUIName[15] = "B7";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 1 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O0";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O1";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O2";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O3";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O4";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O5";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O6";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O7";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "15 -1 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "CIn";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-15 -1 0";
|
||||
logicPortDir[25] = 0;
|
||||
logicPortUIName[25] = "COut";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
};
|
@ -50,7 +50,6 @@ datablock fxDtsBrickData(LogicGate_Demux1Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -1";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "0 0 -1";
|
||||
|
@ -50,7 +50,6 @@ datablock fxDtsBrickData(LogicGate_Demux1_Data){
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 0;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
|
@ -51,13 +51,11 @@ datablock fxDtsBrickData(LogicGate_Demux2Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -3";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -1";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "0 0 -3";
|
||||
|
@ -51,13 +51,11 @@ datablock fxDtsBrickData(LogicGate_Demux2_Data){
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 0;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
|
@ -52,19 +52,16 @@ datablock fxDtsBrickData(LogicGate_Demux3Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -7";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -5";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -3";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "0 0 -7";
|
||||
|
@ -52,19 +52,16 @@ datablock fxDtsBrickData(LogicGate_Demux3_Data){
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 0;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
|
@ -53,25 +53,21 @@ datablock fxDtsBrickData(LogicGate_Demux4Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -15";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -13";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -11";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -9";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "0 0 -15";
|
||||
|
@ -53,25 +53,21 @@ datablock fxDtsBrickData(LogicGate_Demux4_Data){
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
|
@ -54,31 +54,26 @@ datablock fxDtsBrickData(LogicGate_Demux5Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -31";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -29";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -27";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -25";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -23";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "0 0 -31";
|
||||
|
@ -54,31 +54,26 @@ datablock fxDtsBrickData(LogicGate_Demux5_Data){
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "31 0 0";
|
||||
|
@ -55,37 +55,31 @@ datablock fxDtsBrickData(LogicGate_Demux6Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -63";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -61";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -59";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -57";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -55";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -53";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "0 0 -63";
|
||||
|
@ -55,37 +55,31 @@ datablock fxDtsBrickData(LogicGate_Demux6_Data){
|
||||
logicPortPos[0] = "63 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "63 0 0";
|
||||
|
736
bricks/gen/newcode/Demux 7 Bit Vertical.cs
Normal file
736
bricks/gen/newcode/Demux 7 Bit Vertical.cs
Normal file
@ -0,0 +1,736 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux7Vertical_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 7 Bit Vertical.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 7 Bit Vertical";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 7 Bit Vertical";
|
||||
logicUIName = "Demux 7 Bit Vertical";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 128";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 8 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 136)~=0 then " @
|
||||
" local idx = 8 + " @
|
||||
" (Gate.getportstate(gate, 1) * 1) + " @
|
||||
" (Gate.getportstate(gate, 2) * 2) + " @
|
||||
" (Gate.getportstate(gate, 3) * 4) + " @
|
||||
" (Gate.getportstate(gate, 4) * 8) + " @
|
||||
" (Gate.getportstate(gate, 5) * 16) + " @
|
||||
" (Gate.getportstate(gate, 6) * 32) + " @
|
||||
" (Gate.getportstate(gate, 7) * 64) " @
|
||||
" Gate.setportstate(gate, idx, 1) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" Gate.setportstate(gate, gate.laston, 0) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, gate.laston, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 136;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 -127";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -125";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -123";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -121";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -119";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -117";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -115";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Sel6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "0 0 -127";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "0 0 -125";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "0 0 -123";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "0 0 -121";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "0 0 -119";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "0 0 -117";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "0 0 -115";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "0 0 -113";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out7";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "0 0 -111";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out8";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "0 0 -109";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out9";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "0 0 -107";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out10";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "0 0 -105";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out11";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "0 0 -103";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out12";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "0 0 -101";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out13";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "0 0 -99";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out14";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "0 0 -97";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out15";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "0 0 -95";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out16";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "0 0 -93";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out17";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "0 0 -91";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out18";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "0 0 -89";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out19";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "0 0 -87";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out20";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "0 0 -85";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out21";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "0 0 -83";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out22";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "0 0 -81";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out23";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "0 0 -79";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out24";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "0 0 -77";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out25";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "0 0 -75";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out26";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "0 0 -73";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out27";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "0 0 -71";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out28";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "0 0 -69";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out29";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "0 0 -67";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out30";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "0 0 -65";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out31";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "0 0 -63";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out32";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "0 0 -61";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out33";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "0 0 -59";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out34";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "0 0 -57";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out35";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "0 0 -55";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out36";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "0 0 -53";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out37";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "0 0 -51";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out38";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "0 0 -49";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out39";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "0 0 -47";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out40";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "0 0 -45";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out41";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "0 0 -43";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out42";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "0 0 -41";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out43";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "0 0 -39";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out44";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "0 0 -37";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out45";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "0 0 -35";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out46";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "0 0 -33";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out47";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "0 0 -31";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out48";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "0 0 -29";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out49";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "0 0 -27";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out50";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "0 0 -25";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out51";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "0 0 -23";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out52";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "0 0 -21";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out53";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "0 0 -19";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out54";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "0 0 -17";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out55";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "0 0 -15";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out56";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "0 0 -13";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "Out57";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "0 0 -11";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "Out58";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "0 0 -9";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "Out59";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "0 0 -7";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "Out60";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "0 0 -5";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "Out61";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "0 0 -3";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "Out62";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "0 0 -1";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "Out63";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "0 0 1";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "Out64";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "0 0 3";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "Out65";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "0 0 5";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "Out66";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "0 0 7";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "Out67";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "0 0 9";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "Out68";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "0 0 11";
|
||||
logicPortDir[76] = 1;
|
||||
logicPortUIName[76] = "Out69";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "0 0 13";
|
||||
logicPortDir[77] = 1;
|
||||
logicPortUIName[77] = "Out70";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "0 0 15";
|
||||
logicPortDir[78] = 1;
|
||||
logicPortUIName[78] = "Out71";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "0 0 17";
|
||||
logicPortDir[79] = 1;
|
||||
logicPortUIName[79] = "Out72";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "0 0 19";
|
||||
logicPortDir[80] = 1;
|
||||
logicPortUIName[80] = "Out73";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "0 0 21";
|
||||
logicPortDir[81] = 1;
|
||||
logicPortUIName[81] = "Out74";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "0 0 23";
|
||||
logicPortDir[82] = 1;
|
||||
logicPortUIName[82] = "Out75";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "0 0 25";
|
||||
logicPortDir[83] = 1;
|
||||
logicPortUIName[83] = "Out76";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "0 0 27";
|
||||
logicPortDir[84] = 1;
|
||||
logicPortUIName[84] = "Out77";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "0 0 29";
|
||||
logicPortDir[85] = 1;
|
||||
logicPortUIName[85] = "Out78";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "0 0 31";
|
||||
logicPortDir[86] = 1;
|
||||
logicPortUIName[86] = "Out79";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "0 0 33";
|
||||
logicPortDir[87] = 1;
|
||||
logicPortUIName[87] = "Out80";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "0 0 35";
|
||||
logicPortDir[88] = 1;
|
||||
logicPortUIName[88] = "Out81";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "0 0 37";
|
||||
logicPortDir[89] = 1;
|
||||
logicPortUIName[89] = "Out82";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "0 0 39";
|
||||
logicPortDir[90] = 1;
|
||||
logicPortUIName[90] = "Out83";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "0 0 41";
|
||||
logicPortDir[91] = 1;
|
||||
logicPortUIName[91] = "Out84";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "0 0 43";
|
||||
logicPortDir[92] = 1;
|
||||
logicPortUIName[92] = "Out85";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "0 0 45";
|
||||
logicPortDir[93] = 1;
|
||||
logicPortUIName[93] = "Out86";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "0 0 47";
|
||||
logicPortDir[94] = 1;
|
||||
logicPortUIName[94] = "Out87";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "0 0 49";
|
||||
logicPortDir[95] = 1;
|
||||
logicPortUIName[95] = "Out88";
|
||||
|
||||
logicPortType[96] = 0;
|
||||
logicPortPos[96] = "0 0 51";
|
||||
logicPortDir[96] = 1;
|
||||
logicPortUIName[96] = "Out89";
|
||||
|
||||
logicPortType[97] = 0;
|
||||
logicPortPos[97] = "0 0 53";
|
||||
logicPortDir[97] = 1;
|
||||
logicPortUIName[97] = "Out90";
|
||||
|
||||
logicPortType[98] = 0;
|
||||
logicPortPos[98] = "0 0 55";
|
||||
logicPortDir[98] = 1;
|
||||
logicPortUIName[98] = "Out91";
|
||||
|
||||
logicPortType[99] = 0;
|
||||
logicPortPos[99] = "0 0 57";
|
||||
logicPortDir[99] = 1;
|
||||
logicPortUIName[99] = "Out92";
|
||||
|
||||
logicPortType[100] = 0;
|
||||
logicPortPos[100] = "0 0 59";
|
||||
logicPortDir[100] = 1;
|
||||
logicPortUIName[100] = "Out93";
|
||||
|
||||
logicPortType[101] = 0;
|
||||
logicPortPos[101] = "0 0 61";
|
||||
logicPortDir[101] = 1;
|
||||
logicPortUIName[101] = "Out94";
|
||||
|
||||
logicPortType[102] = 0;
|
||||
logicPortPos[102] = "0 0 63";
|
||||
logicPortDir[102] = 1;
|
||||
logicPortUIName[102] = "Out95";
|
||||
|
||||
logicPortType[103] = 0;
|
||||
logicPortPos[103] = "0 0 65";
|
||||
logicPortDir[103] = 1;
|
||||
logicPortUIName[103] = "Out96";
|
||||
|
||||
logicPortType[104] = 0;
|
||||
logicPortPos[104] = "0 0 67";
|
||||
logicPortDir[104] = 1;
|
||||
logicPortUIName[104] = "Out97";
|
||||
|
||||
logicPortType[105] = 0;
|
||||
logicPortPos[105] = "0 0 69";
|
||||
logicPortDir[105] = 1;
|
||||
logicPortUIName[105] = "Out98";
|
||||
|
||||
logicPortType[106] = 0;
|
||||
logicPortPos[106] = "0 0 71";
|
||||
logicPortDir[106] = 1;
|
||||
logicPortUIName[106] = "Out99";
|
||||
|
||||
logicPortType[107] = 0;
|
||||
logicPortPos[107] = "0 0 73";
|
||||
logicPortDir[107] = 1;
|
||||
logicPortUIName[107] = "Out100";
|
||||
|
||||
logicPortType[108] = 0;
|
||||
logicPortPos[108] = "0 0 75";
|
||||
logicPortDir[108] = 1;
|
||||
logicPortUIName[108] = "Out101";
|
||||
|
||||
logicPortType[109] = 0;
|
||||
logicPortPos[109] = "0 0 77";
|
||||
logicPortDir[109] = 1;
|
||||
logicPortUIName[109] = "Out102";
|
||||
|
||||
logicPortType[110] = 0;
|
||||
logicPortPos[110] = "0 0 79";
|
||||
logicPortDir[110] = 1;
|
||||
logicPortUIName[110] = "Out103";
|
||||
|
||||
logicPortType[111] = 0;
|
||||
logicPortPos[111] = "0 0 81";
|
||||
logicPortDir[111] = 1;
|
||||
logicPortUIName[111] = "Out104";
|
||||
|
||||
logicPortType[112] = 0;
|
||||
logicPortPos[112] = "0 0 83";
|
||||
logicPortDir[112] = 1;
|
||||
logicPortUIName[112] = "Out105";
|
||||
|
||||
logicPortType[113] = 0;
|
||||
logicPortPos[113] = "0 0 85";
|
||||
logicPortDir[113] = 1;
|
||||
logicPortUIName[113] = "Out106";
|
||||
|
||||
logicPortType[114] = 0;
|
||||
logicPortPos[114] = "0 0 87";
|
||||
logicPortDir[114] = 1;
|
||||
logicPortUIName[114] = "Out107";
|
||||
|
||||
logicPortType[115] = 0;
|
||||
logicPortPos[115] = "0 0 89";
|
||||
logicPortDir[115] = 1;
|
||||
logicPortUIName[115] = "Out108";
|
||||
|
||||
logicPortType[116] = 0;
|
||||
logicPortPos[116] = "0 0 91";
|
||||
logicPortDir[116] = 1;
|
||||
logicPortUIName[116] = "Out109";
|
||||
|
||||
logicPortType[117] = 0;
|
||||
logicPortPos[117] = "0 0 93";
|
||||
logicPortDir[117] = 1;
|
||||
logicPortUIName[117] = "Out110";
|
||||
|
||||
logicPortType[118] = 0;
|
||||
logicPortPos[118] = "0 0 95";
|
||||
logicPortDir[118] = 1;
|
||||
logicPortUIName[118] = "Out111";
|
||||
|
||||
logicPortType[119] = 0;
|
||||
logicPortPos[119] = "0 0 97";
|
||||
logicPortDir[119] = 1;
|
||||
logicPortUIName[119] = "Out112";
|
||||
|
||||
logicPortType[120] = 0;
|
||||
logicPortPos[120] = "0 0 99";
|
||||
logicPortDir[120] = 1;
|
||||
logicPortUIName[120] = "Out113";
|
||||
|
||||
logicPortType[121] = 0;
|
||||
logicPortPos[121] = "0 0 101";
|
||||
logicPortDir[121] = 1;
|
||||
logicPortUIName[121] = "Out114";
|
||||
|
||||
logicPortType[122] = 0;
|
||||
logicPortPos[122] = "0 0 103";
|
||||
logicPortDir[122] = 1;
|
||||
logicPortUIName[122] = "Out115";
|
||||
|
||||
logicPortType[123] = 0;
|
||||
logicPortPos[123] = "0 0 105";
|
||||
logicPortDir[123] = 1;
|
||||
logicPortUIName[123] = "Out116";
|
||||
|
||||
logicPortType[124] = 0;
|
||||
logicPortPos[124] = "0 0 107";
|
||||
logicPortDir[124] = 1;
|
||||
logicPortUIName[124] = "Out117";
|
||||
|
||||
logicPortType[125] = 0;
|
||||
logicPortPos[125] = "0 0 109";
|
||||
logicPortDir[125] = 1;
|
||||
logicPortUIName[125] = "Out118";
|
||||
|
||||
logicPortType[126] = 0;
|
||||
logicPortPos[126] = "0 0 111";
|
||||
logicPortDir[126] = 1;
|
||||
logicPortUIName[126] = "Out119";
|
||||
|
||||
logicPortType[127] = 0;
|
||||
logicPortPos[127] = "0 0 113";
|
||||
logicPortDir[127] = 1;
|
||||
logicPortUIName[127] = "Out120";
|
||||
|
||||
logicPortType[128] = 0;
|
||||
logicPortPos[128] = "0 0 115";
|
||||
logicPortDir[128] = 1;
|
||||
logicPortUIName[128] = "Out121";
|
||||
|
||||
logicPortType[129] = 0;
|
||||
logicPortPos[129] = "0 0 117";
|
||||
logicPortDir[129] = 1;
|
||||
logicPortUIName[129] = "Out122";
|
||||
|
||||
logicPortType[130] = 0;
|
||||
logicPortPos[130] = "0 0 119";
|
||||
logicPortDir[130] = 1;
|
||||
logicPortUIName[130] = "Out123";
|
||||
|
||||
logicPortType[131] = 0;
|
||||
logicPortPos[131] = "0 0 121";
|
||||
logicPortDir[131] = 1;
|
||||
logicPortUIName[131] = "Out124";
|
||||
|
||||
logicPortType[132] = 0;
|
||||
logicPortPos[132] = "0 0 123";
|
||||
logicPortDir[132] = 1;
|
||||
logicPortUIName[132] = "Out125";
|
||||
|
||||
logicPortType[133] = 0;
|
||||
logicPortPos[133] = "0 0 125";
|
||||
logicPortDir[133] = 1;
|
||||
logicPortUIName[133] = "Out126";
|
||||
|
||||
logicPortType[134] = 0;
|
||||
logicPortPos[134] = "0 0 127";
|
||||
logicPortDir[134] = 1;
|
||||
logicPortUIName[134] = "Out127";
|
||||
|
||||
logicPortType[135] = 1;
|
||||
logicPortPos[135] = "0 0 -127";
|
||||
logicPortDir[135] = 5;
|
||||
logicPortUIName[135] = "Enable";
|
||||
logicPortCauseUpdate[135] = true;
|
||||
|
||||
};
|
736
bricks/gen/newcode/Demux 7 Bit.cs
Normal file
736
bricks/gen/newcode/Demux 7 Bit.cs
Normal file
@ -0,0 +1,736 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Demux7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Demux 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Demux 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Demux 7 Bit";
|
||||
logicUIName = "Demux 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "128 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.laston = 8 " @
|
||||
"end"
|
||||
;
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 136)~=0 then " @
|
||||
" local idx = 8 + " @
|
||||
" (Gate.getportstate(gate, 1) * 1) + " @
|
||||
" (Gate.getportstate(gate, 2) * 2) + " @
|
||||
" (Gate.getportstate(gate, 3) * 4) + " @
|
||||
" (Gate.getportstate(gate, 4) * 8) + " @
|
||||
" (Gate.getportstate(gate, 5) * 16) + " @
|
||||
" (Gate.getportstate(gate, 6) * 32) + " @
|
||||
" (Gate.getportstate(gate, 7) * 64) " @
|
||||
" Gate.setportstate(gate, idx, 1) " @
|
||||
" if gate.laston~=idx then " @
|
||||
" Gate.setportstate(gate, gate.laston, 0) " @
|
||||
" gate.laston = idx " @
|
||||
" end " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, gate.laston, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 136;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "127 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "125 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "123 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "121 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "119 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "117 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "115 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Sel6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "127 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out0";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "125 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out1";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "123 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out2";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "121 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out3";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "119 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "Out4";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "117 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "Out5";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "115 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "Out6";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "113 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "Out7";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "111 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "Out8";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "109 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "Out9";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "107 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "Out10";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "105 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "Out11";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "103 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "Out12";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "101 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "Out13";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "99 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "Out14";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "97 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "Out15";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "95 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "Out16";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "93 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "Out17";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "91 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "Out18";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "89 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "Out19";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "87 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "Out20";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "85 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "Out21";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "83 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "Out22";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "81 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "Out23";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "79 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "Out24";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "77 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "Out25";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "75 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "Out26";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "73 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "Out27";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "71 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "Out28";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "69 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "Out29";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "67 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "Out30";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "65 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "Out31";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "63 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "Out32";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "61 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "Out33";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "59 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "Out34";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "57 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "Out35";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "55 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "Out36";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "53 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "Out37";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "51 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "Out38";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "49 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "Out39";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "47 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "Out40";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "45 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "Out41";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "43 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "Out42";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "41 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "Out43";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "39 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "Out44";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "37 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "Out45";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "35 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "Out46";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "33 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out47";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "31 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out48";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "29 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out49";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "27 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out50";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "25 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out51";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "23 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out52";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "21 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out53";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "19 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out54";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "17 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out55";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "15 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out56";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "13 0 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "Out57";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "11 0 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "Out58";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "9 0 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "Out59";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "7 0 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "Out60";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "5 0 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "Out61";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "3 0 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "Out62";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "1 0 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "Out63";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "-1 0 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "Out64";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "-3 0 0";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "Out65";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "-5 0 0";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "Out66";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "-7 0 0";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "Out67";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "-9 0 0";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "Out68";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "-11 0 0";
|
||||
logicPortDir[76] = 1;
|
||||
logicPortUIName[76] = "Out69";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "-13 0 0";
|
||||
logicPortDir[77] = 1;
|
||||
logicPortUIName[77] = "Out70";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "-15 0 0";
|
||||
logicPortDir[78] = 1;
|
||||
logicPortUIName[78] = "Out71";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "-17 0 0";
|
||||
logicPortDir[79] = 1;
|
||||
logicPortUIName[79] = "Out72";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "-19 0 0";
|
||||
logicPortDir[80] = 1;
|
||||
logicPortUIName[80] = "Out73";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "-21 0 0";
|
||||
logicPortDir[81] = 1;
|
||||
logicPortUIName[81] = "Out74";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "-23 0 0";
|
||||
logicPortDir[82] = 1;
|
||||
logicPortUIName[82] = "Out75";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "-25 0 0";
|
||||
logicPortDir[83] = 1;
|
||||
logicPortUIName[83] = "Out76";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "-27 0 0";
|
||||
logicPortDir[84] = 1;
|
||||
logicPortUIName[84] = "Out77";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "-29 0 0";
|
||||
logicPortDir[85] = 1;
|
||||
logicPortUIName[85] = "Out78";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "-31 0 0";
|
||||
logicPortDir[86] = 1;
|
||||
logicPortUIName[86] = "Out79";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "-33 0 0";
|
||||
logicPortDir[87] = 1;
|
||||
logicPortUIName[87] = "Out80";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "-35 0 0";
|
||||
logicPortDir[88] = 1;
|
||||
logicPortUIName[88] = "Out81";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "-37 0 0";
|
||||
logicPortDir[89] = 1;
|
||||
logicPortUIName[89] = "Out82";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "-39 0 0";
|
||||
logicPortDir[90] = 1;
|
||||
logicPortUIName[90] = "Out83";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "-41 0 0";
|
||||
logicPortDir[91] = 1;
|
||||
logicPortUIName[91] = "Out84";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "-43 0 0";
|
||||
logicPortDir[92] = 1;
|
||||
logicPortUIName[92] = "Out85";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "-45 0 0";
|
||||
logicPortDir[93] = 1;
|
||||
logicPortUIName[93] = "Out86";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "-47 0 0";
|
||||
logicPortDir[94] = 1;
|
||||
logicPortUIName[94] = "Out87";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "-49 0 0";
|
||||
logicPortDir[95] = 1;
|
||||
logicPortUIName[95] = "Out88";
|
||||
|
||||
logicPortType[96] = 0;
|
||||
logicPortPos[96] = "-51 0 0";
|
||||
logicPortDir[96] = 1;
|
||||
logicPortUIName[96] = "Out89";
|
||||
|
||||
logicPortType[97] = 0;
|
||||
logicPortPos[97] = "-53 0 0";
|
||||
logicPortDir[97] = 1;
|
||||
logicPortUIName[97] = "Out90";
|
||||
|
||||
logicPortType[98] = 0;
|
||||
logicPortPos[98] = "-55 0 0";
|
||||
logicPortDir[98] = 1;
|
||||
logicPortUIName[98] = "Out91";
|
||||
|
||||
logicPortType[99] = 0;
|
||||
logicPortPos[99] = "-57 0 0";
|
||||
logicPortDir[99] = 1;
|
||||
logicPortUIName[99] = "Out92";
|
||||
|
||||
logicPortType[100] = 0;
|
||||
logicPortPos[100] = "-59 0 0";
|
||||
logicPortDir[100] = 1;
|
||||
logicPortUIName[100] = "Out93";
|
||||
|
||||
logicPortType[101] = 0;
|
||||
logicPortPos[101] = "-61 0 0";
|
||||
logicPortDir[101] = 1;
|
||||
logicPortUIName[101] = "Out94";
|
||||
|
||||
logicPortType[102] = 0;
|
||||
logicPortPos[102] = "-63 0 0";
|
||||
logicPortDir[102] = 1;
|
||||
logicPortUIName[102] = "Out95";
|
||||
|
||||
logicPortType[103] = 0;
|
||||
logicPortPos[103] = "-65 0 0";
|
||||
logicPortDir[103] = 1;
|
||||
logicPortUIName[103] = "Out96";
|
||||
|
||||
logicPortType[104] = 0;
|
||||
logicPortPos[104] = "-67 0 0";
|
||||
logicPortDir[104] = 1;
|
||||
logicPortUIName[104] = "Out97";
|
||||
|
||||
logicPortType[105] = 0;
|
||||
logicPortPos[105] = "-69 0 0";
|
||||
logicPortDir[105] = 1;
|
||||
logicPortUIName[105] = "Out98";
|
||||
|
||||
logicPortType[106] = 0;
|
||||
logicPortPos[106] = "-71 0 0";
|
||||
logicPortDir[106] = 1;
|
||||
logicPortUIName[106] = "Out99";
|
||||
|
||||
logicPortType[107] = 0;
|
||||
logicPortPos[107] = "-73 0 0";
|
||||
logicPortDir[107] = 1;
|
||||
logicPortUIName[107] = "Out100";
|
||||
|
||||
logicPortType[108] = 0;
|
||||
logicPortPos[108] = "-75 0 0";
|
||||
logicPortDir[108] = 1;
|
||||
logicPortUIName[108] = "Out101";
|
||||
|
||||
logicPortType[109] = 0;
|
||||
logicPortPos[109] = "-77 0 0";
|
||||
logicPortDir[109] = 1;
|
||||
logicPortUIName[109] = "Out102";
|
||||
|
||||
logicPortType[110] = 0;
|
||||
logicPortPos[110] = "-79 0 0";
|
||||
logicPortDir[110] = 1;
|
||||
logicPortUIName[110] = "Out103";
|
||||
|
||||
logicPortType[111] = 0;
|
||||
logicPortPos[111] = "-81 0 0";
|
||||
logicPortDir[111] = 1;
|
||||
logicPortUIName[111] = "Out104";
|
||||
|
||||
logicPortType[112] = 0;
|
||||
logicPortPos[112] = "-83 0 0";
|
||||
logicPortDir[112] = 1;
|
||||
logicPortUIName[112] = "Out105";
|
||||
|
||||
logicPortType[113] = 0;
|
||||
logicPortPos[113] = "-85 0 0";
|
||||
logicPortDir[113] = 1;
|
||||
logicPortUIName[113] = "Out106";
|
||||
|
||||
logicPortType[114] = 0;
|
||||
logicPortPos[114] = "-87 0 0";
|
||||
logicPortDir[114] = 1;
|
||||
logicPortUIName[114] = "Out107";
|
||||
|
||||
logicPortType[115] = 0;
|
||||
logicPortPos[115] = "-89 0 0";
|
||||
logicPortDir[115] = 1;
|
||||
logicPortUIName[115] = "Out108";
|
||||
|
||||
logicPortType[116] = 0;
|
||||
logicPortPos[116] = "-91 0 0";
|
||||
logicPortDir[116] = 1;
|
||||
logicPortUIName[116] = "Out109";
|
||||
|
||||
logicPortType[117] = 0;
|
||||
logicPortPos[117] = "-93 0 0";
|
||||
logicPortDir[117] = 1;
|
||||
logicPortUIName[117] = "Out110";
|
||||
|
||||
logicPortType[118] = 0;
|
||||
logicPortPos[118] = "-95 0 0";
|
||||
logicPortDir[118] = 1;
|
||||
logicPortUIName[118] = "Out111";
|
||||
|
||||
logicPortType[119] = 0;
|
||||
logicPortPos[119] = "-97 0 0";
|
||||
logicPortDir[119] = 1;
|
||||
logicPortUIName[119] = "Out112";
|
||||
|
||||
logicPortType[120] = 0;
|
||||
logicPortPos[120] = "-99 0 0";
|
||||
logicPortDir[120] = 1;
|
||||
logicPortUIName[120] = "Out113";
|
||||
|
||||
logicPortType[121] = 0;
|
||||
logicPortPos[121] = "-101 0 0";
|
||||
logicPortDir[121] = 1;
|
||||
logicPortUIName[121] = "Out114";
|
||||
|
||||
logicPortType[122] = 0;
|
||||
logicPortPos[122] = "-103 0 0";
|
||||
logicPortDir[122] = 1;
|
||||
logicPortUIName[122] = "Out115";
|
||||
|
||||
logicPortType[123] = 0;
|
||||
logicPortPos[123] = "-105 0 0";
|
||||
logicPortDir[123] = 1;
|
||||
logicPortUIName[123] = "Out116";
|
||||
|
||||
logicPortType[124] = 0;
|
||||
logicPortPos[124] = "-107 0 0";
|
||||
logicPortDir[124] = 1;
|
||||
logicPortUIName[124] = "Out117";
|
||||
|
||||
logicPortType[125] = 0;
|
||||
logicPortPos[125] = "-109 0 0";
|
||||
logicPortDir[125] = 1;
|
||||
logicPortUIName[125] = "Out118";
|
||||
|
||||
logicPortType[126] = 0;
|
||||
logicPortPos[126] = "-111 0 0";
|
||||
logicPortDir[126] = 1;
|
||||
logicPortUIName[126] = "Out119";
|
||||
|
||||
logicPortType[127] = 0;
|
||||
logicPortPos[127] = "-113 0 0";
|
||||
logicPortDir[127] = 1;
|
||||
logicPortUIName[127] = "Out120";
|
||||
|
||||
logicPortType[128] = 0;
|
||||
logicPortPos[128] = "-115 0 0";
|
||||
logicPortDir[128] = 1;
|
||||
logicPortUIName[128] = "Out121";
|
||||
|
||||
logicPortType[129] = 0;
|
||||
logicPortPos[129] = "-117 0 0";
|
||||
logicPortDir[129] = 1;
|
||||
logicPortUIName[129] = "Out122";
|
||||
|
||||
logicPortType[130] = 0;
|
||||
logicPortPos[130] = "-119 0 0";
|
||||
logicPortDir[130] = 1;
|
||||
logicPortUIName[130] = "Out123";
|
||||
|
||||
logicPortType[131] = 0;
|
||||
logicPortPos[131] = "-121 0 0";
|
||||
logicPortDir[131] = 1;
|
||||
logicPortUIName[131] = "Out124";
|
||||
|
||||
logicPortType[132] = 0;
|
||||
logicPortPos[132] = "-123 0 0";
|
||||
logicPortDir[132] = 1;
|
||||
logicPortUIName[132] = "Out125";
|
||||
|
||||
logicPortType[133] = 0;
|
||||
logicPortPos[133] = "-125 0 0";
|
||||
logicPortDir[133] = 1;
|
||||
logicPortUIName[133] = "Out126";
|
||||
|
||||
logicPortType[134] = 0;
|
||||
logicPortPos[134] = "-127 0 0";
|
||||
logicPortDir[134] = 1;
|
||||
logicPortUIName[134] = "Out127";
|
||||
|
||||
logicPortType[135] = 1;
|
||||
logicPortPos[135] = "127 0 0";
|
||||
logicPortDir[135] = 2;
|
||||
logicPortUIName[135] = "Enable";
|
||||
logicPortCauseUpdate[135] = true;
|
||||
|
||||
};
|
1382
bricks/gen/newcode/Demux 8 Bit Vertical.cs
Normal file
1382
bricks/gen/newcode/Demux 8 Bit Vertical.cs
Normal file
File diff suppressed because it is too large
Load Diff
1382
bricks/gen/newcode/Demux 8 Bit.cs
Normal file
1382
bricks/gen/newcode/Demux 8 Bit.cs
Normal file
File diff suppressed because it is too large
Load Diff
@ -42,19 +42,16 @@ datablock fxDtsBrickData(LogicGate_Mux1Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -1";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -1";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "In0";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 1";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "In1";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -1";
|
||||
|
@ -42,19 +42,16 @@ datablock fxDtsBrickData(LogicGate_Mux1_Data){
|
||||
logicPortPos[0] = "1 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 1;
|
||||
logicPortUIName[1] = "In0";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "In1";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
|
@ -43,37 +43,31 @@ datablock fxDtsBrickData(LogicGate_Mux2Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -3";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -1";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -3";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "In0";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -1";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "In1";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 1";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "In2";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 3";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In3";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -3";
|
||||
|
@ -43,37 +43,31 @@ datablock fxDtsBrickData(LogicGate_Mux2_Data){
|
||||
logicPortPos[0] = "3 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 1;
|
||||
logicPortUIName[2] = "In0";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "In1";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "In2";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In3";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 0 0";
|
||||
|
@ -44,67 +44,56 @@ datablock fxDtsBrickData(LogicGate_Mux3Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -7";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -5";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -3";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -7";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "In0";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -5";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "In1";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -3";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In2";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -1";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In3";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 1";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In4";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "0 0 3";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In5";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "0 0 5";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In6";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "0 0 7";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In7";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "0 0 -7";
|
||||
|
@ -44,67 +44,56 @@ datablock fxDtsBrickData(LogicGate_Mux3_Data){
|
||||
logicPortPos[0] = "7 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "7 0 0";
|
||||
logicPortDir[3] = 1;
|
||||
logicPortUIName[3] = "In0";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "5 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "In1";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In2";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "1 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In3";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "-1 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In4";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "-3 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In5";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "-5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In6";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "-7 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In7";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "7 0 0";
|
||||
|
@ -45,121 +45,101 @@ datablock fxDtsBrickData(LogicGate_Mux4Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -15";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -13";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -11";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -9";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -15";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "In0";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -13";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In1";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -11";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In2";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 -9";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In3";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "0 0 -7";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In4";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "0 0 -5";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In5";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "0 0 -3";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In6";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "0 0 -1";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In7";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "0 0 1";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In8";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "0 0 3";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In9";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "0 0 5";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In10";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "0 0 7";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In11";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "0 0 9";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In12";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "0 0 11";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In13";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "0 0 13";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In14";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "0 0 15";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In15";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "0 0 -15";
|
||||
|
@ -45,121 +45,101 @@ datablock fxDtsBrickData(LogicGate_Mux4_Data){
|
||||
logicPortPos[0] = "15 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "15 0 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "In0";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "13 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In1";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "11 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In2";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "9 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In3";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "7 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In4";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "5 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In5";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "3 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In6";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "1 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In7";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "-1 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In8";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "-3 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In9";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "-5 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In10";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "-7 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In11";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "-9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In12";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "-11 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In13";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "-13 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In14";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "-15 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In15";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "15 0 0";
|
||||
|
@ -46,223 +46,186 @@ datablock fxDtsBrickData(LogicGate_Mux5Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -31";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -29";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -27";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -25";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -23";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -31";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In0";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -29";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In1";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 -27";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In2";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "0 0 -25";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In3";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "0 0 -23";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In4";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "0 0 -21";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In5";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "0 0 -19";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In6";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "0 0 -17";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In7";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "0 0 -15";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In8";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "0 0 -13";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In9";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "0 0 -11";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In10";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "0 0 -9";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In11";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "0 0 -7";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In12";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "0 0 -5";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In13";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "0 0 -3";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In14";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "0 0 -1";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "In15";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "0 0 1";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "In16";
|
||||
logicPortCauseUpdate[21] = true;
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "0 0 3";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "In17";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "0 0 5";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "In18";
|
||||
logicPortCauseUpdate[23] = true;
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "0 0 7";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "In19";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "0 0 9";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "In20";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "0 0 11";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "In21";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "0 0 13";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "In22";
|
||||
logicPortCauseUpdate[27] = true;
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "0 0 15";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "In23";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "0 0 17";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "In24";
|
||||
logicPortCauseUpdate[29] = true;
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "0 0 19";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "In25";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "0 0 21";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "In26";
|
||||
logicPortCauseUpdate[31] = true;
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "0 0 23";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "In27";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "0 0 25";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "In28";
|
||||
logicPortCauseUpdate[33] = true;
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "0 0 27";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "In29";
|
||||
logicPortCauseUpdate[34] = true;
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "0 0 29";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "In30";
|
||||
logicPortCauseUpdate[35] = true;
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "0 0 31";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "In31";
|
||||
logicPortCauseUpdate[36] = true;
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "0 0 -31";
|
||||
|
@ -46,223 +46,186 @@ datablock fxDtsBrickData(LogicGate_Mux5_Data){
|
||||
logicPortPos[0] = "31 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "31 0 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "In0";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "29 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In1";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "27 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In2";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "25 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In3";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "23 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In4";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "21 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In5";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "19 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In6";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "17 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In7";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "15 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In8";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "13 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In9";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "11 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In10";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "9 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In11";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "7 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In12";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "5 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In13";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "3 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In14";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "1 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "In15";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "-1 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "In16";
|
||||
logicPortCauseUpdate[21] = true;
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "-3 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "In17";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "-5 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "In18";
|
||||
logicPortCauseUpdate[23] = true;
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "-7 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "In19";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "-9 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "In20";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "-11 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "In21";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "-13 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "In22";
|
||||
logicPortCauseUpdate[27] = true;
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "-15 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "In23";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "-17 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "In24";
|
||||
logicPortCauseUpdate[29] = true;
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "-19 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "In25";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "-21 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "In26";
|
||||
logicPortCauseUpdate[31] = true;
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "-23 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "In27";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "-25 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "In28";
|
||||
logicPortCauseUpdate[33] = true;
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "-27 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "In29";
|
||||
logicPortCauseUpdate[34] = true;
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "-29 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "In30";
|
||||
logicPortCauseUpdate[35] = true;
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "-31 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "In31";
|
||||
logicPortCauseUpdate[36] = true;
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "31 0 0";
|
||||
|
@ -47,421 +47,351 @@ datablock fxDtsBrickData(LogicGate_Mux6Vertical_Data){
|
||||
logicPortPos[0] = "0 0 -63";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -61";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -59";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -57";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -55";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -53";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -63";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In0";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 -61";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In1";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "0 0 -59";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In2";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "0 0 -57";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In3";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "0 0 -55";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In4";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "0 0 -53";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In5";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "0 0 -51";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In6";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "0 0 -49";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In7";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "0 0 -47";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In8";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "0 0 -45";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In9";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "0 0 -43";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In10";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "0 0 -41";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In11";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "0 0 -39";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In12";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "0 0 -37";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In13";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "0 0 -35";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "In14";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "0 0 -33";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "In15";
|
||||
logicPortCauseUpdate[21] = true;
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "0 0 -31";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "In16";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "0 0 -29";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "In17";
|
||||
logicPortCauseUpdate[23] = true;
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "0 0 -27";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "In18";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "0 0 -25";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "In19";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "0 0 -23";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "In20";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "0 0 -21";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "In21";
|
||||
logicPortCauseUpdate[27] = true;
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "0 0 -19";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "In22";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "0 0 -17";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "In23";
|
||||
logicPortCauseUpdate[29] = true;
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "0 0 -15";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "In24";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "0 0 -13";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "In25";
|
||||
logicPortCauseUpdate[31] = true;
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "0 0 -11";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "In26";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "0 0 -9";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "In27";
|
||||
logicPortCauseUpdate[33] = true;
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "0 0 -7";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "In28";
|
||||
logicPortCauseUpdate[34] = true;
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "0 0 -5";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "In29";
|
||||
logicPortCauseUpdate[35] = true;
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "0 0 -3";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "In30";
|
||||
logicPortCauseUpdate[36] = true;
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "0 0 -1";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "In31";
|
||||
logicPortCauseUpdate[37] = true;
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "0 0 1";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "In32";
|
||||
logicPortCauseUpdate[38] = true;
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "0 0 3";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "In33";
|
||||
logicPortCauseUpdate[39] = true;
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "0 0 5";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "In34";
|
||||
logicPortCauseUpdate[40] = true;
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "0 0 7";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "In35";
|
||||
logicPortCauseUpdate[41] = true;
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "0 0 9";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "In36";
|
||||
logicPortCauseUpdate[42] = true;
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "0 0 11";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "In37";
|
||||
logicPortCauseUpdate[43] = true;
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "0 0 13";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "In38";
|
||||
logicPortCauseUpdate[44] = true;
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "0 0 15";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "In39";
|
||||
logicPortCauseUpdate[45] = true;
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "0 0 17";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "In40";
|
||||
logicPortCauseUpdate[46] = true;
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "0 0 19";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "In41";
|
||||
logicPortCauseUpdate[47] = true;
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "0 0 21";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "In42";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "0 0 23";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "In43";
|
||||
logicPortCauseUpdate[49] = true;
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "0 0 25";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "In44";
|
||||
logicPortCauseUpdate[50] = true;
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "0 0 27";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "In45";
|
||||
logicPortCauseUpdate[51] = true;
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "0 0 29";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "In46";
|
||||
logicPortCauseUpdate[52] = true;
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "0 0 31";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "In47";
|
||||
logicPortCauseUpdate[53] = true;
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "0 0 33";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "In48";
|
||||
logicPortCauseUpdate[54] = true;
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "0 0 35";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "In49";
|
||||
logicPortCauseUpdate[55] = true;
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "0 0 37";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "In50";
|
||||
logicPortCauseUpdate[56] = true;
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "0 0 39";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "In51";
|
||||
logicPortCauseUpdate[57] = true;
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "0 0 41";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "In52";
|
||||
logicPortCauseUpdate[58] = true;
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "0 0 43";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "In53";
|
||||
logicPortCauseUpdate[59] = true;
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "0 0 45";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "In54";
|
||||
logicPortCauseUpdate[60] = true;
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "0 0 47";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "In55";
|
||||
logicPortCauseUpdate[61] = true;
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "0 0 49";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "In56";
|
||||
logicPortCauseUpdate[62] = true;
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "0 0 51";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "In57";
|
||||
logicPortCauseUpdate[63] = true;
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "0 0 53";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "In58";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
logicPortType[65] = 1;
|
||||
logicPortPos[65] = "0 0 55";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "In59";
|
||||
logicPortCauseUpdate[65] = true;
|
||||
|
||||
logicPortType[66] = 1;
|
||||
logicPortPos[66] = "0 0 57";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "In60";
|
||||
logicPortCauseUpdate[66] = true;
|
||||
|
||||
logicPortType[67] = 1;
|
||||
logicPortPos[67] = "0 0 59";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "In61";
|
||||
logicPortCauseUpdate[67] = true;
|
||||
|
||||
logicPortType[68] = 1;
|
||||
logicPortPos[68] = "0 0 61";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "In62";
|
||||
logicPortCauseUpdate[68] = true;
|
||||
|
||||
logicPortType[69] = 1;
|
||||
logicPortPos[69] = "0 0 63";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "In63";
|
||||
logicPortCauseUpdate[69] = true;
|
||||
|
||||
logicPortType[70] = 1;
|
||||
logicPortPos[70] = "0 0 -63";
|
||||
|
@ -47,421 +47,351 @@ datablock fxDtsBrickData(LogicGate_Mux6_Data){
|
||||
logicPortPos[0] = "63 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
logicPortCauseUpdate[0] = true;
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
logicPortCauseUpdate[1] = true;
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
logicPortCauseUpdate[2] = true;
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
logicPortCauseUpdate[3] = true;
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
logicPortCauseUpdate[4] = true;
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "63 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "In0";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "61 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In1";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "59 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In2";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "57 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In3";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "55 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In4";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "53 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In5";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "51 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In6";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "49 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In7";
|
||||
logicPortCauseUpdate[13] = true;
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "47 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In8";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "45 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In9";
|
||||
logicPortCauseUpdate[15] = true;
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "43 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In10";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "41 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In11";
|
||||
logicPortCauseUpdate[17] = true;
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "39 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In12";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "37 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In13";
|
||||
logicPortCauseUpdate[19] = true;
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "35 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "In14";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "33 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "In15";
|
||||
logicPortCauseUpdate[21] = true;
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "31 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "In16";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "29 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "In17";
|
||||
logicPortCauseUpdate[23] = true;
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "27 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "In18";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "25 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "In19";
|
||||
logicPortCauseUpdate[25] = true;
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "23 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "In20";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "21 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "In21";
|
||||
logicPortCauseUpdate[27] = true;
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "19 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "In22";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "17 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "In23";
|
||||
logicPortCauseUpdate[29] = true;
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "15 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "In24";
|
||||
logicPortCauseUpdate[30] = true;
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "13 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "In25";
|
||||
logicPortCauseUpdate[31] = true;
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "11 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "In26";
|
||||
logicPortCauseUpdate[32] = true;
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "9 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "In27";
|
||||
logicPortCauseUpdate[33] = true;
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "7 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "In28";
|
||||
logicPortCauseUpdate[34] = true;
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "5 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "In29";
|
||||
logicPortCauseUpdate[35] = true;
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "3 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "In30";
|
||||
logicPortCauseUpdate[36] = true;
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "1 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "In31";
|
||||
logicPortCauseUpdate[37] = true;
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "-1 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "In32";
|
||||
logicPortCauseUpdate[38] = true;
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "-3 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "In33";
|
||||
logicPortCauseUpdate[39] = true;
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "-5 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "In34";
|
||||
logicPortCauseUpdate[40] = true;
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "-7 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "In35";
|
||||
logicPortCauseUpdate[41] = true;
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "-9 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "In36";
|
||||
logicPortCauseUpdate[42] = true;
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "-11 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "In37";
|
||||
logicPortCauseUpdate[43] = true;
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "-13 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "In38";
|
||||
logicPortCauseUpdate[44] = true;
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "-15 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "In39";
|
||||
logicPortCauseUpdate[45] = true;
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "-17 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "In40";
|
||||
logicPortCauseUpdate[46] = true;
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "-19 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "In41";
|
||||
logicPortCauseUpdate[47] = true;
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "-21 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "In42";
|
||||
logicPortCauseUpdate[48] = true;
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "-23 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "In43";
|
||||
logicPortCauseUpdate[49] = true;
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "-25 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "In44";
|
||||
logicPortCauseUpdate[50] = true;
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "-27 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "In45";
|
||||
logicPortCauseUpdate[51] = true;
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "-29 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "In46";
|
||||
logicPortCauseUpdate[52] = true;
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "-31 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "In47";
|
||||
logicPortCauseUpdate[53] = true;
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "-33 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "In48";
|
||||
logicPortCauseUpdate[54] = true;
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "-35 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "In49";
|
||||
logicPortCauseUpdate[55] = true;
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "-37 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "In50";
|
||||
logicPortCauseUpdate[56] = true;
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "-39 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "In51";
|
||||
logicPortCauseUpdate[57] = true;
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "-41 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "In52";
|
||||
logicPortCauseUpdate[58] = true;
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "-43 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "In53";
|
||||
logicPortCauseUpdate[59] = true;
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "-45 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "In54";
|
||||
logicPortCauseUpdate[60] = true;
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "-47 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "In55";
|
||||
logicPortCauseUpdate[61] = true;
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "-49 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "In56";
|
||||
logicPortCauseUpdate[62] = true;
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "-51 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "In57";
|
||||
logicPortCauseUpdate[63] = true;
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "-53 0 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "In58";
|
||||
logicPortCauseUpdate[64] = true;
|
||||
|
||||
logicPortType[65] = 1;
|
||||
logicPortPos[65] = "-55 0 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "In59";
|
||||
logicPortCauseUpdate[65] = true;
|
||||
|
||||
logicPortType[66] = 1;
|
||||
logicPortPos[66] = "-57 0 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "In60";
|
||||
logicPortCauseUpdate[66] = true;
|
||||
|
||||
logicPortType[67] = 1;
|
||||
logicPortPos[67] = "-59 0 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "In61";
|
||||
logicPortCauseUpdate[67] = true;
|
||||
|
||||
logicPortType[68] = 1;
|
||||
logicPortPos[68] = "-61 0 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "In62";
|
||||
logicPortCauseUpdate[68] = true;
|
||||
|
||||
logicPortType[69] = 1;
|
||||
logicPortPos[69] = "-63 0 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "In63";
|
||||
logicPortCauseUpdate[69] = true;
|
||||
|
||||
logicPortType[70] = 1;
|
||||
logicPortPos[70] = "63 0 0";
|
||||
|
733
bricks/gen/newcode/Mux 7 Bit Vertical.cs
Normal file
733
bricks/gen/newcode/Mux 7 Bit Vertical.cs
Normal file
@ -0,0 +1,733 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Mux7Vertical_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Mux 7 Bit Vertical.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Mux 7 Bit Vertical";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Mux 7 Bit Vertical";
|
||||
logicUIName = "Mux 7 Bit Vertical";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "1 1 128";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 136) then " @
|
||||
" local idx = 8 + " @
|
||||
" (Gate.getportstate(gate, 1) * 1) + " @
|
||||
" (Gate.getportstate(gate, 2) * 2) + " @
|
||||
" (Gate.getportstate(gate, 3) * 4) + " @
|
||||
" (Gate.getportstate(gate, 4) * 8) + " @
|
||||
" (Gate.getportstate(gate, 5) * 16) + " @
|
||||
" (Gate.getportstate(gate, 6) * 32) + " @
|
||||
" (Gate.getportstate(gate, 7) * 64) " @
|
||||
" Gate.setportstate(gate, 137, Gate.getportstate(gate, idx)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 137, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 137;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "0 0 -127";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "0 0 -125";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "0 0 -123";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "0 0 -121";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "0 0 -119";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "0 0 -117";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "0 0 -115";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Sel6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "0 0 -127";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In0";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "0 0 -125";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In1";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "0 0 -123";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In2";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "0 0 -121";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In3";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "0 0 -119";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In4";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "0 0 -117";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In5";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "0 0 -115";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "0 0 -113";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In7";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "0 0 -111";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In8";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "0 0 -109";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In9";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "0 0 -107";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In10";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "0 0 -105";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In11";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "0 0 -103";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In12";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "0 0 -101";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "In13";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "0 0 -99";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "In14";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "0 0 -97";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "In15";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "0 0 -95";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "In16";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "0 0 -93";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "In17";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "0 0 -91";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "In18";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "0 0 -89";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "In19";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "0 0 -87";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "In20";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "0 0 -85";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "In21";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "0 0 -83";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "In22";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "0 0 -81";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "In23";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "0 0 -79";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "In24";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "0 0 -77";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "In25";
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "0 0 -75";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "In26";
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "0 0 -73";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "In27";
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "0 0 -71";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "In28";
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "0 0 -69";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "In29";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "0 0 -67";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "In30";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "0 0 -65";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "In31";
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "0 0 -63";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "In32";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "0 0 -61";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "In33";
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "0 0 -59";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "In34";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "0 0 -57";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "In35";
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "0 0 -55";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "In36";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "0 0 -53";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "In37";
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "0 0 -51";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "In38";
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "0 0 -49";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "In39";
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "0 0 -47";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "In40";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "0 0 -45";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "In41";
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "0 0 -43";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "In42";
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "0 0 -41";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "In43";
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "0 0 -39";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "In44";
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "0 0 -37";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "In45";
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "0 0 -35";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "In46";
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "0 0 -33";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "In47";
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "0 0 -31";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "In48";
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "0 0 -29";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "In49";
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "0 0 -27";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "In50";
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "0 0 -25";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "In51";
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "0 0 -23";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "In52";
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "0 0 -21";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "In53";
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "0 0 -19";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "In54";
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "0 0 -17";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "In55";
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "0 0 -15";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "In56";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "0 0 -13";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "In57";
|
||||
|
||||
logicPortType[65] = 1;
|
||||
logicPortPos[65] = "0 0 -11";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "In58";
|
||||
|
||||
logicPortType[66] = 1;
|
||||
logicPortPos[66] = "0 0 -9";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "In59";
|
||||
|
||||
logicPortType[67] = 1;
|
||||
logicPortPos[67] = "0 0 -7";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "In60";
|
||||
|
||||
logicPortType[68] = 1;
|
||||
logicPortPos[68] = "0 0 -5";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "In61";
|
||||
|
||||
logicPortType[69] = 1;
|
||||
logicPortPos[69] = "0 0 -3";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "In62";
|
||||
|
||||
logicPortType[70] = 1;
|
||||
logicPortPos[70] = "0 0 -1";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "In63";
|
||||
|
||||
logicPortType[71] = 1;
|
||||
logicPortPos[71] = "0 0 1";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "In64";
|
||||
|
||||
logicPortType[72] = 1;
|
||||
logicPortPos[72] = "0 0 3";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "In65";
|
||||
|
||||
logicPortType[73] = 1;
|
||||
logicPortPos[73] = "0 0 5";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "In66";
|
||||
|
||||
logicPortType[74] = 1;
|
||||
logicPortPos[74] = "0 0 7";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "In67";
|
||||
|
||||
logicPortType[75] = 1;
|
||||
logicPortPos[75] = "0 0 9";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "In68";
|
||||
|
||||
logicPortType[76] = 1;
|
||||
logicPortPos[76] = "0 0 11";
|
||||
logicPortDir[76] = 1;
|
||||
logicPortUIName[76] = "In69";
|
||||
|
||||
logicPortType[77] = 1;
|
||||
logicPortPos[77] = "0 0 13";
|
||||
logicPortDir[77] = 1;
|
||||
logicPortUIName[77] = "In70";
|
||||
|
||||
logicPortType[78] = 1;
|
||||
logicPortPos[78] = "0 0 15";
|
||||
logicPortDir[78] = 1;
|
||||
logicPortUIName[78] = "In71";
|
||||
|
||||
logicPortType[79] = 1;
|
||||
logicPortPos[79] = "0 0 17";
|
||||
logicPortDir[79] = 1;
|
||||
logicPortUIName[79] = "In72";
|
||||
|
||||
logicPortType[80] = 1;
|
||||
logicPortPos[80] = "0 0 19";
|
||||
logicPortDir[80] = 1;
|
||||
logicPortUIName[80] = "In73";
|
||||
|
||||
logicPortType[81] = 1;
|
||||
logicPortPos[81] = "0 0 21";
|
||||
logicPortDir[81] = 1;
|
||||
logicPortUIName[81] = "In74";
|
||||
|
||||
logicPortType[82] = 1;
|
||||
logicPortPos[82] = "0 0 23";
|
||||
logicPortDir[82] = 1;
|
||||
logicPortUIName[82] = "In75";
|
||||
|
||||
logicPortType[83] = 1;
|
||||
logicPortPos[83] = "0 0 25";
|
||||
logicPortDir[83] = 1;
|
||||
logicPortUIName[83] = "In76";
|
||||
|
||||
logicPortType[84] = 1;
|
||||
logicPortPos[84] = "0 0 27";
|
||||
logicPortDir[84] = 1;
|
||||
logicPortUIName[84] = "In77";
|
||||
|
||||
logicPortType[85] = 1;
|
||||
logicPortPos[85] = "0 0 29";
|
||||
logicPortDir[85] = 1;
|
||||
logicPortUIName[85] = "In78";
|
||||
|
||||
logicPortType[86] = 1;
|
||||
logicPortPos[86] = "0 0 31";
|
||||
logicPortDir[86] = 1;
|
||||
logicPortUIName[86] = "In79";
|
||||
|
||||
logicPortType[87] = 1;
|
||||
logicPortPos[87] = "0 0 33";
|
||||
logicPortDir[87] = 1;
|
||||
logicPortUIName[87] = "In80";
|
||||
|
||||
logicPortType[88] = 1;
|
||||
logicPortPos[88] = "0 0 35";
|
||||
logicPortDir[88] = 1;
|
||||
logicPortUIName[88] = "In81";
|
||||
|
||||
logicPortType[89] = 1;
|
||||
logicPortPos[89] = "0 0 37";
|
||||
logicPortDir[89] = 1;
|
||||
logicPortUIName[89] = "In82";
|
||||
|
||||
logicPortType[90] = 1;
|
||||
logicPortPos[90] = "0 0 39";
|
||||
logicPortDir[90] = 1;
|
||||
logicPortUIName[90] = "In83";
|
||||
|
||||
logicPortType[91] = 1;
|
||||
logicPortPos[91] = "0 0 41";
|
||||
logicPortDir[91] = 1;
|
||||
logicPortUIName[91] = "In84";
|
||||
|
||||
logicPortType[92] = 1;
|
||||
logicPortPos[92] = "0 0 43";
|
||||
logicPortDir[92] = 1;
|
||||
logicPortUIName[92] = "In85";
|
||||
|
||||
logicPortType[93] = 1;
|
||||
logicPortPos[93] = "0 0 45";
|
||||
logicPortDir[93] = 1;
|
||||
logicPortUIName[93] = "In86";
|
||||
|
||||
logicPortType[94] = 1;
|
||||
logicPortPos[94] = "0 0 47";
|
||||
logicPortDir[94] = 1;
|
||||
logicPortUIName[94] = "In87";
|
||||
|
||||
logicPortType[95] = 1;
|
||||
logicPortPos[95] = "0 0 49";
|
||||
logicPortDir[95] = 1;
|
||||
logicPortUIName[95] = "In88";
|
||||
|
||||
logicPortType[96] = 1;
|
||||
logicPortPos[96] = "0 0 51";
|
||||
logicPortDir[96] = 1;
|
||||
logicPortUIName[96] = "In89";
|
||||
|
||||
logicPortType[97] = 1;
|
||||
logicPortPos[97] = "0 0 53";
|
||||
logicPortDir[97] = 1;
|
||||
logicPortUIName[97] = "In90";
|
||||
|
||||
logicPortType[98] = 1;
|
||||
logicPortPos[98] = "0 0 55";
|
||||
logicPortDir[98] = 1;
|
||||
logicPortUIName[98] = "In91";
|
||||
|
||||
logicPortType[99] = 1;
|
||||
logicPortPos[99] = "0 0 57";
|
||||
logicPortDir[99] = 1;
|
||||
logicPortUIName[99] = "In92";
|
||||
|
||||
logicPortType[100] = 1;
|
||||
logicPortPos[100] = "0 0 59";
|
||||
logicPortDir[100] = 1;
|
||||
logicPortUIName[100] = "In93";
|
||||
|
||||
logicPortType[101] = 1;
|
||||
logicPortPos[101] = "0 0 61";
|
||||
logicPortDir[101] = 1;
|
||||
logicPortUIName[101] = "In94";
|
||||
|
||||
logicPortType[102] = 1;
|
||||
logicPortPos[102] = "0 0 63";
|
||||
logicPortDir[102] = 1;
|
||||
logicPortUIName[102] = "In95";
|
||||
|
||||
logicPortType[103] = 1;
|
||||
logicPortPos[103] = "0 0 65";
|
||||
logicPortDir[103] = 1;
|
||||
logicPortUIName[103] = "In96";
|
||||
|
||||
logicPortType[104] = 1;
|
||||
logicPortPos[104] = "0 0 67";
|
||||
logicPortDir[104] = 1;
|
||||
logicPortUIName[104] = "In97";
|
||||
|
||||
logicPortType[105] = 1;
|
||||
logicPortPos[105] = "0 0 69";
|
||||
logicPortDir[105] = 1;
|
||||
logicPortUIName[105] = "In98";
|
||||
|
||||
logicPortType[106] = 1;
|
||||
logicPortPos[106] = "0 0 71";
|
||||
logicPortDir[106] = 1;
|
||||
logicPortUIName[106] = "In99";
|
||||
|
||||
logicPortType[107] = 1;
|
||||
logicPortPos[107] = "0 0 73";
|
||||
logicPortDir[107] = 1;
|
||||
logicPortUIName[107] = "In100";
|
||||
|
||||
logicPortType[108] = 1;
|
||||
logicPortPos[108] = "0 0 75";
|
||||
logicPortDir[108] = 1;
|
||||
logicPortUIName[108] = "In101";
|
||||
|
||||
logicPortType[109] = 1;
|
||||
logicPortPos[109] = "0 0 77";
|
||||
logicPortDir[109] = 1;
|
||||
logicPortUIName[109] = "In102";
|
||||
|
||||
logicPortType[110] = 1;
|
||||
logicPortPos[110] = "0 0 79";
|
||||
logicPortDir[110] = 1;
|
||||
logicPortUIName[110] = "In103";
|
||||
|
||||
logicPortType[111] = 1;
|
||||
logicPortPos[111] = "0 0 81";
|
||||
logicPortDir[111] = 1;
|
||||
logicPortUIName[111] = "In104";
|
||||
|
||||
logicPortType[112] = 1;
|
||||
logicPortPos[112] = "0 0 83";
|
||||
logicPortDir[112] = 1;
|
||||
logicPortUIName[112] = "In105";
|
||||
|
||||
logicPortType[113] = 1;
|
||||
logicPortPos[113] = "0 0 85";
|
||||
logicPortDir[113] = 1;
|
||||
logicPortUIName[113] = "In106";
|
||||
|
||||
logicPortType[114] = 1;
|
||||
logicPortPos[114] = "0 0 87";
|
||||
logicPortDir[114] = 1;
|
||||
logicPortUIName[114] = "In107";
|
||||
|
||||
logicPortType[115] = 1;
|
||||
logicPortPos[115] = "0 0 89";
|
||||
logicPortDir[115] = 1;
|
||||
logicPortUIName[115] = "In108";
|
||||
|
||||
logicPortType[116] = 1;
|
||||
logicPortPos[116] = "0 0 91";
|
||||
logicPortDir[116] = 1;
|
||||
logicPortUIName[116] = "In109";
|
||||
|
||||
logicPortType[117] = 1;
|
||||
logicPortPos[117] = "0 0 93";
|
||||
logicPortDir[117] = 1;
|
||||
logicPortUIName[117] = "In110";
|
||||
|
||||
logicPortType[118] = 1;
|
||||
logicPortPos[118] = "0 0 95";
|
||||
logicPortDir[118] = 1;
|
||||
logicPortUIName[118] = "In111";
|
||||
|
||||
logicPortType[119] = 1;
|
||||
logicPortPos[119] = "0 0 97";
|
||||
logicPortDir[119] = 1;
|
||||
logicPortUIName[119] = "In112";
|
||||
|
||||
logicPortType[120] = 1;
|
||||
logicPortPos[120] = "0 0 99";
|
||||
logicPortDir[120] = 1;
|
||||
logicPortUIName[120] = "In113";
|
||||
|
||||
logicPortType[121] = 1;
|
||||
logicPortPos[121] = "0 0 101";
|
||||
logicPortDir[121] = 1;
|
||||
logicPortUIName[121] = "In114";
|
||||
|
||||
logicPortType[122] = 1;
|
||||
logicPortPos[122] = "0 0 103";
|
||||
logicPortDir[122] = 1;
|
||||
logicPortUIName[122] = "In115";
|
||||
|
||||
logicPortType[123] = 1;
|
||||
logicPortPos[123] = "0 0 105";
|
||||
logicPortDir[123] = 1;
|
||||
logicPortUIName[123] = "In116";
|
||||
|
||||
logicPortType[124] = 1;
|
||||
logicPortPos[124] = "0 0 107";
|
||||
logicPortDir[124] = 1;
|
||||
logicPortUIName[124] = "In117";
|
||||
|
||||
logicPortType[125] = 1;
|
||||
logicPortPos[125] = "0 0 109";
|
||||
logicPortDir[125] = 1;
|
||||
logicPortUIName[125] = "In118";
|
||||
|
||||
logicPortType[126] = 1;
|
||||
logicPortPos[126] = "0 0 111";
|
||||
logicPortDir[126] = 1;
|
||||
logicPortUIName[126] = "In119";
|
||||
|
||||
logicPortType[127] = 1;
|
||||
logicPortPos[127] = "0 0 113";
|
||||
logicPortDir[127] = 1;
|
||||
logicPortUIName[127] = "In120";
|
||||
|
||||
logicPortType[128] = 1;
|
||||
logicPortPos[128] = "0 0 115";
|
||||
logicPortDir[128] = 1;
|
||||
logicPortUIName[128] = "In121";
|
||||
|
||||
logicPortType[129] = 1;
|
||||
logicPortPos[129] = "0 0 117";
|
||||
logicPortDir[129] = 1;
|
||||
logicPortUIName[129] = "In122";
|
||||
|
||||
logicPortType[130] = 1;
|
||||
logicPortPos[130] = "0 0 119";
|
||||
logicPortDir[130] = 1;
|
||||
logicPortUIName[130] = "In123";
|
||||
|
||||
logicPortType[131] = 1;
|
||||
logicPortPos[131] = "0 0 121";
|
||||
logicPortDir[131] = 1;
|
||||
logicPortUIName[131] = "In124";
|
||||
|
||||
logicPortType[132] = 1;
|
||||
logicPortPos[132] = "0 0 123";
|
||||
logicPortDir[132] = 1;
|
||||
logicPortUIName[132] = "In125";
|
||||
|
||||
logicPortType[133] = 1;
|
||||
logicPortPos[133] = "0 0 125";
|
||||
logicPortDir[133] = 1;
|
||||
logicPortUIName[133] = "In126";
|
||||
|
||||
logicPortType[134] = 1;
|
||||
logicPortPos[134] = "0 0 127";
|
||||
logicPortDir[134] = 1;
|
||||
logicPortUIName[134] = "In127";
|
||||
|
||||
logicPortType[135] = 1;
|
||||
logicPortPos[135] = "0 0 -127";
|
||||
logicPortDir[135] = 5;
|
||||
logicPortUIName[135] = "Enable";
|
||||
logicPortCauseUpdate[135] = true;
|
||||
|
||||
logicPortType[136] = 0;
|
||||
logicPortPos[136] = "0 0 127";
|
||||
logicPortDir[136] = 4;
|
||||
logicPortUIName[136] = "Out";
|
||||
|
||||
};
|
733
bricks/gen/newcode/Mux 7 Bit.cs
Normal file
733
bricks/gen/newcode/Mux 7 Bit.cs
Normal file
@ -0,0 +1,733 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Mux7_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Mux 7 Bit.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/Mux 7 Bit";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Mux";
|
||||
uiName = "Mux 7 Bit";
|
||||
logicUIName = "Mux 7 Bit";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "128 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit = "";
|
||||
logicInput = "";
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 136) then " @
|
||||
" local idx = 8 + " @
|
||||
" (Gate.getportstate(gate, 1) * 1) + " @
|
||||
" (Gate.getportstate(gate, 2) * 2) + " @
|
||||
" (Gate.getportstate(gate, 3) * 4) + " @
|
||||
" (Gate.getportstate(gate, 4) * 8) + " @
|
||||
" (Gate.getportstate(gate, 5) * 16) + " @
|
||||
" (Gate.getportstate(gate, 6) * 32) + " @
|
||||
" (Gate.getportstate(gate, 7) * 64) " @
|
||||
" Gate.setportstate(gate, 137, Gate.getportstate(gate, idx)) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 137, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 137;
|
||||
|
||||
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "127 0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Sel0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "125 0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Sel1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "123 0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Sel2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "121 0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Sel3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "119 0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Sel4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "117 0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Sel5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "115 0 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Sel6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "127 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "In0";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "125 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "In1";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "123 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "In2";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "121 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "In3";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "119 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "In4";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "117 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "In5";
|
||||
|
||||
logicPortType[13] = 1;
|
||||
logicPortPos[13] = "115 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "In6";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "113 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "In7";
|
||||
|
||||
logicPortType[15] = 1;
|
||||
logicPortPos[15] = "111 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "In8";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "109 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "In9";
|
||||
|
||||
logicPortType[17] = 1;
|
||||
logicPortPos[17] = "107 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "In10";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "105 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "In11";
|
||||
|
||||
logicPortType[19] = 1;
|
||||
logicPortPos[19] = "103 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "In12";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "101 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "In13";
|
||||
|
||||
logicPortType[21] = 1;
|
||||
logicPortPos[21] = "99 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "In14";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "97 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "In15";
|
||||
|
||||
logicPortType[23] = 1;
|
||||
logicPortPos[23] = "95 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "In16";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "93 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "In17";
|
||||
|
||||
logicPortType[25] = 1;
|
||||
logicPortPos[25] = "91 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "In18";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "89 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "In19";
|
||||
|
||||
logicPortType[27] = 1;
|
||||
logicPortPos[27] = "87 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "In20";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "85 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "In21";
|
||||
|
||||
logicPortType[29] = 1;
|
||||
logicPortPos[29] = "83 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "In22";
|
||||
|
||||
logicPortType[30] = 1;
|
||||
logicPortPos[30] = "81 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "In23";
|
||||
|
||||
logicPortType[31] = 1;
|
||||
logicPortPos[31] = "79 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "In24";
|
||||
|
||||
logicPortType[32] = 1;
|
||||
logicPortPos[32] = "77 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "In25";
|
||||
|
||||
logicPortType[33] = 1;
|
||||
logicPortPos[33] = "75 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "In26";
|
||||
|
||||
logicPortType[34] = 1;
|
||||
logicPortPos[34] = "73 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "In27";
|
||||
|
||||
logicPortType[35] = 1;
|
||||
logicPortPos[35] = "71 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "In28";
|
||||
|
||||
logicPortType[36] = 1;
|
||||
logicPortPos[36] = "69 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "In29";
|
||||
|
||||
logicPortType[37] = 1;
|
||||
logicPortPos[37] = "67 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "In30";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "65 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "In31";
|
||||
|
||||
logicPortType[39] = 1;
|
||||
logicPortPos[39] = "63 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "In32";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "61 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "In33";
|
||||
|
||||
logicPortType[41] = 1;
|
||||
logicPortPos[41] = "59 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "In34";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "57 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "In35";
|
||||
|
||||
logicPortType[43] = 1;
|
||||
logicPortPos[43] = "55 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "In36";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "53 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "In37";
|
||||
|
||||
logicPortType[45] = 1;
|
||||
logicPortPos[45] = "51 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "In38";
|
||||
|
||||
logicPortType[46] = 1;
|
||||
logicPortPos[46] = "49 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "In39";
|
||||
|
||||
logicPortType[47] = 1;
|
||||
logicPortPos[47] = "47 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "In40";
|
||||
|
||||
logicPortType[48] = 1;
|
||||
logicPortPos[48] = "45 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "In41";
|
||||
|
||||
logicPortType[49] = 1;
|
||||
logicPortPos[49] = "43 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "In42";
|
||||
|
||||
logicPortType[50] = 1;
|
||||
logicPortPos[50] = "41 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "In43";
|
||||
|
||||
logicPortType[51] = 1;
|
||||
logicPortPos[51] = "39 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "In44";
|
||||
|
||||
logicPortType[52] = 1;
|
||||
logicPortPos[52] = "37 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "In45";
|
||||
|
||||
logicPortType[53] = 1;
|
||||
logicPortPos[53] = "35 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "In46";
|
||||
|
||||
logicPortType[54] = 1;
|
||||
logicPortPos[54] = "33 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "In47";
|
||||
|
||||
logicPortType[55] = 1;
|
||||
logicPortPos[55] = "31 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "In48";
|
||||
|
||||
logicPortType[56] = 1;
|
||||
logicPortPos[56] = "29 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "In49";
|
||||
|
||||
logicPortType[57] = 1;
|
||||
logicPortPos[57] = "27 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "In50";
|
||||
|
||||
logicPortType[58] = 1;
|
||||
logicPortPos[58] = "25 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "In51";
|
||||
|
||||
logicPortType[59] = 1;
|
||||
logicPortPos[59] = "23 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "In52";
|
||||
|
||||
logicPortType[60] = 1;
|
||||
logicPortPos[60] = "21 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "In53";
|
||||
|
||||
logicPortType[61] = 1;
|
||||
logicPortPos[61] = "19 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "In54";
|
||||
|
||||
logicPortType[62] = 1;
|
||||
logicPortPos[62] = "17 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "In55";
|
||||
|
||||
logicPortType[63] = 1;
|
||||
logicPortPos[63] = "15 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "In56";
|
||||
|
||||
logicPortType[64] = 1;
|
||||
logicPortPos[64] = "13 0 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "In57";
|
||||
|
||||
logicPortType[65] = 1;
|
||||
logicPortPos[65] = "11 0 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "In58";
|
||||
|
||||
logicPortType[66] = 1;
|
||||
logicPortPos[66] = "9 0 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "In59";
|
||||
|
||||
logicPortType[67] = 1;
|
||||
logicPortPos[67] = "7 0 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "In60";
|
||||
|
||||
logicPortType[68] = 1;
|
||||
logicPortPos[68] = "5 0 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "In61";
|
||||
|
||||
logicPortType[69] = 1;
|
||||
logicPortPos[69] = "3 0 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "In62";
|
||||
|
||||
logicPortType[70] = 1;
|
||||
logicPortPos[70] = "1 0 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "In63";
|
||||
|
||||
logicPortType[71] = 1;
|
||||
logicPortPos[71] = "-1 0 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "In64";
|
||||
|
||||
logicPortType[72] = 1;
|
||||
logicPortPos[72] = "-3 0 0";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "In65";
|
||||
|
||||
logicPortType[73] = 1;
|
||||
logicPortPos[73] = "-5 0 0";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "In66";
|
||||
|
||||
logicPortType[74] = 1;
|
||||
logicPortPos[74] = "-7 0 0";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "In67";
|
||||
|
||||
logicPortType[75] = 1;
|
||||
logicPortPos[75] = "-9 0 0";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "In68";
|
||||
|
||||
logicPortType[76] = 1;
|
||||
logicPortPos[76] = "-11 0 0";
|
||||
logicPortDir[76] = 1;
|
||||
logicPortUIName[76] = "In69";
|
||||
|
||||
logicPortType[77] = 1;
|
||||
logicPortPos[77] = "-13 0 0";
|
||||
logicPortDir[77] = 1;
|
||||
logicPortUIName[77] = "In70";
|
||||
|
||||
logicPortType[78] = 1;
|
||||
logicPortPos[78] = "-15 0 0";
|
||||
logicPortDir[78] = 1;
|
||||
logicPortUIName[78] = "In71";
|
||||
|
||||
logicPortType[79] = 1;
|
||||
logicPortPos[79] = "-17 0 0";
|
||||
logicPortDir[79] = 1;
|
||||
logicPortUIName[79] = "In72";
|
||||
|
||||
logicPortType[80] = 1;
|
||||
logicPortPos[80] = "-19 0 0";
|
||||
logicPortDir[80] = 1;
|
||||
logicPortUIName[80] = "In73";
|
||||
|
||||
logicPortType[81] = 1;
|
||||
logicPortPos[81] = "-21 0 0";
|
||||
logicPortDir[81] = 1;
|
||||
logicPortUIName[81] = "In74";
|
||||
|
||||
logicPortType[82] = 1;
|
||||
logicPortPos[82] = "-23 0 0";
|
||||
logicPortDir[82] = 1;
|
||||
logicPortUIName[82] = "In75";
|
||||
|
||||
logicPortType[83] = 1;
|
||||
logicPortPos[83] = "-25 0 0";
|
||||
logicPortDir[83] = 1;
|
||||
logicPortUIName[83] = "In76";
|
||||
|
||||
logicPortType[84] = 1;
|
||||
logicPortPos[84] = "-27 0 0";
|
||||
logicPortDir[84] = 1;
|
||||
logicPortUIName[84] = "In77";
|
||||
|
||||
logicPortType[85] = 1;
|
||||
logicPortPos[85] = "-29 0 0";
|
||||
logicPortDir[85] = 1;
|
||||
logicPortUIName[85] = "In78";
|
||||
|
||||
logicPortType[86] = 1;
|
||||
logicPortPos[86] = "-31 0 0";
|
||||
logicPortDir[86] = 1;
|
||||
logicPortUIName[86] = "In79";
|
||||
|
||||
logicPortType[87] = 1;
|
||||
logicPortPos[87] = "-33 0 0";
|
||||
logicPortDir[87] = 1;
|
||||
logicPortUIName[87] = "In80";
|
||||
|
||||
logicPortType[88] = 1;
|
||||
logicPortPos[88] = "-35 0 0";
|
||||
logicPortDir[88] = 1;
|
||||
logicPortUIName[88] = "In81";
|
||||
|
||||
logicPortType[89] = 1;
|
||||
logicPortPos[89] = "-37 0 0";
|
||||
logicPortDir[89] = 1;
|
||||
logicPortUIName[89] = "In82";
|
||||
|
||||
logicPortType[90] = 1;
|
||||
logicPortPos[90] = "-39 0 0";
|
||||
logicPortDir[90] = 1;
|
||||
logicPortUIName[90] = "In83";
|
||||
|
||||
logicPortType[91] = 1;
|
||||
logicPortPos[91] = "-41 0 0";
|
||||
logicPortDir[91] = 1;
|
||||
logicPortUIName[91] = "In84";
|
||||
|
||||
logicPortType[92] = 1;
|
||||
logicPortPos[92] = "-43 0 0";
|
||||
logicPortDir[92] = 1;
|
||||
logicPortUIName[92] = "In85";
|
||||
|
||||
logicPortType[93] = 1;
|
||||
logicPortPos[93] = "-45 0 0";
|
||||
logicPortDir[93] = 1;
|
||||
logicPortUIName[93] = "In86";
|
||||
|
||||
logicPortType[94] = 1;
|
||||
logicPortPos[94] = "-47 0 0";
|
||||
logicPortDir[94] = 1;
|
||||
logicPortUIName[94] = "In87";
|
||||
|
||||
logicPortType[95] = 1;
|
||||
logicPortPos[95] = "-49 0 0";
|
||||
logicPortDir[95] = 1;
|
||||
logicPortUIName[95] = "In88";
|
||||
|
||||
logicPortType[96] = 1;
|
||||
logicPortPos[96] = "-51 0 0";
|
||||
logicPortDir[96] = 1;
|
||||
logicPortUIName[96] = "In89";
|
||||
|
||||
logicPortType[97] = 1;
|
||||
logicPortPos[97] = "-53 0 0";
|
||||
logicPortDir[97] = 1;
|
||||
logicPortUIName[97] = "In90";
|
||||
|
||||
logicPortType[98] = 1;
|
||||
logicPortPos[98] = "-55 0 0";
|
||||
logicPortDir[98] = 1;
|
||||
logicPortUIName[98] = "In91";
|
||||
|
||||
logicPortType[99] = 1;
|
||||
logicPortPos[99] = "-57 0 0";
|
||||
logicPortDir[99] = 1;
|
||||
logicPortUIName[99] = "In92";
|
||||
|
||||
logicPortType[100] = 1;
|
||||
logicPortPos[100] = "-59 0 0";
|
||||
logicPortDir[100] = 1;
|
||||
logicPortUIName[100] = "In93";
|
||||
|
||||
logicPortType[101] = 1;
|
||||
logicPortPos[101] = "-61 0 0";
|
||||
logicPortDir[101] = 1;
|
||||
logicPortUIName[101] = "In94";
|
||||
|
||||
logicPortType[102] = 1;
|
||||
logicPortPos[102] = "-63 0 0";
|
||||
logicPortDir[102] = 1;
|
||||
logicPortUIName[102] = "In95";
|
||||
|
||||
logicPortType[103] = 1;
|
||||
logicPortPos[103] = "-65 0 0";
|
||||
logicPortDir[103] = 1;
|
||||
logicPortUIName[103] = "In96";
|
||||
|
||||
logicPortType[104] = 1;
|
||||
logicPortPos[104] = "-67 0 0";
|
||||
logicPortDir[104] = 1;
|
||||
logicPortUIName[104] = "In97";
|
||||
|
||||
logicPortType[105] = 1;
|
||||
logicPortPos[105] = "-69 0 0";
|
||||
logicPortDir[105] = 1;
|
||||
logicPortUIName[105] = "In98";
|
||||
|
||||
logicPortType[106] = 1;
|
||||
logicPortPos[106] = "-71 0 0";
|
||||
logicPortDir[106] = 1;
|
||||
logicPortUIName[106] = "In99";
|
||||
|
||||
logicPortType[107] = 1;
|
||||
logicPortPos[107] = "-73 0 0";
|
||||
logicPortDir[107] = 1;
|
||||
logicPortUIName[107] = "In100";
|
||||
|
||||
logicPortType[108] = 1;
|
||||
logicPortPos[108] = "-75 0 0";
|
||||
logicPortDir[108] = 1;
|
||||
logicPortUIName[108] = "In101";
|
||||
|
||||
logicPortType[109] = 1;
|
||||
logicPortPos[109] = "-77 0 0";
|
||||
logicPortDir[109] = 1;
|
||||
logicPortUIName[109] = "In102";
|
||||
|
||||
logicPortType[110] = 1;
|
||||
logicPortPos[110] = "-79 0 0";
|
||||
logicPortDir[110] = 1;
|
||||
logicPortUIName[110] = "In103";
|
||||
|
||||
logicPortType[111] = 1;
|
||||
logicPortPos[111] = "-81 0 0";
|
||||
logicPortDir[111] = 1;
|
||||
logicPortUIName[111] = "In104";
|
||||
|
||||
logicPortType[112] = 1;
|
||||
logicPortPos[112] = "-83 0 0";
|
||||
logicPortDir[112] = 1;
|
||||
logicPortUIName[112] = "In105";
|
||||
|
||||
logicPortType[113] = 1;
|
||||
logicPortPos[113] = "-85 0 0";
|
||||
logicPortDir[113] = 1;
|
||||
logicPortUIName[113] = "In106";
|
||||
|
||||
logicPortType[114] = 1;
|
||||
logicPortPos[114] = "-87 0 0";
|
||||
logicPortDir[114] = 1;
|
||||
logicPortUIName[114] = "In107";
|
||||
|
||||
logicPortType[115] = 1;
|
||||
logicPortPos[115] = "-89 0 0";
|
||||
logicPortDir[115] = 1;
|
||||
logicPortUIName[115] = "In108";
|
||||
|
||||
logicPortType[116] = 1;
|
||||
logicPortPos[116] = "-91 0 0";
|
||||
logicPortDir[116] = 1;
|
||||
logicPortUIName[116] = "In109";
|
||||
|
||||
logicPortType[117] = 1;
|
||||
logicPortPos[117] = "-93 0 0";
|
||||
logicPortDir[117] = 1;
|
||||
logicPortUIName[117] = "In110";
|
||||
|
||||
logicPortType[118] = 1;
|
||||
logicPortPos[118] = "-95 0 0";
|
||||
logicPortDir[118] = 1;
|
||||
logicPortUIName[118] = "In111";
|
||||
|
||||
logicPortType[119] = 1;
|
||||
logicPortPos[119] = "-97 0 0";
|
||||
logicPortDir[119] = 1;
|
||||
logicPortUIName[119] = "In112";
|
||||
|
||||
logicPortType[120] = 1;
|
||||
logicPortPos[120] = "-99 0 0";
|
||||
logicPortDir[120] = 1;
|
||||
logicPortUIName[120] = "In113";
|
||||
|
||||
logicPortType[121] = 1;
|
||||
logicPortPos[121] = "-101 0 0";
|
||||
logicPortDir[121] = 1;
|
||||
logicPortUIName[121] = "In114";
|
||||
|
||||
logicPortType[122] = 1;
|
||||
logicPortPos[122] = "-103 0 0";
|
||||
logicPortDir[122] = 1;
|
||||
logicPortUIName[122] = "In115";
|
||||
|
||||
logicPortType[123] = 1;
|
||||
logicPortPos[123] = "-105 0 0";
|
||||
logicPortDir[123] = 1;
|
||||
logicPortUIName[123] = "In116";
|
||||
|
||||
logicPortType[124] = 1;
|
||||
logicPortPos[124] = "-107 0 0";
|
||||
logicPortDir[124] = 1;
|
||||
logicPortUIName[124] = "In117";
|
||||
|
||||
logicPortType[125] = 1;
|
||||
logicPortPos[125] = "-109 0 0";
|
||||
logicPortDir[125] = 1;
|
||||
logicPortUIName[125] = "In118";
|
||||
|
||||
logicPortType[126] = 1;
|
||||
logicPortPos[126] = "-111 0 0";
|
||||
logicPortDir[126] = 1;
|
||||
logicPortUIName[126] = "In119";
|
||||
|
||||
logicPortType[127] = 1;
|
||||
logicPortPos[127] = "-113 0 0";
|
||||
logicPortDir[127] = 1;
|
||||
logicPortUIName[127] = "In120";
|
||||
|
||||
logicPortType[128] = 1;
|
||||
logicPortPos[128] = "-115 0 0";
|
||||
logicPortDir[128] = 1;
|
||||
logicPortUIName[128] = "In121";
|
||||
|
||||
logicPortType[129] = 1;
|
||||
logicPortPos[129] = "-117 0 0";
|
||||
logicPortDir[129] = 1;
|
||||
logicPortUIName[129] = "In122";
|
||||
|
||||
logicPortType[130] = 1;
|
||||
logicPortPos[130] = "-119 0 0";
|
||||
logicPortDir[130] = 1;
|
||||
logicPortUIName[130] = "In123";
|
||||
|
||||
logicPortType[131] = 1;
|
||||
logicPortPos[131] = "-121 0 0";
|
||||
logicPortDir[131] = 1;
|
||||
logicPortUIName[131] = "In124";
|
||||
|
||||
logicPortType[132] = 1;
|
||||
logicPortPos[132] = "-123 0 0";
|
||||
logicPortDir[132] = 1;
|
||||
logicPortUIName[132] = "In125";
|
||||
|
||||
logicPortType[133] = 1;
|
||||
logicPortPos[133] = "-125 0 0";
|
||||
logicPortDir[133] = 1;
|
||||
logicPortUIName[133] = "In126";
|
||||
|
||||
logicPortType[134] = 1;
|
||||
logicPortPos[134] = "-127 0 0";
|
||||
logicPortDir[134] = 1;
|
||||
logicPortUIName[134] = "In127";
|
||||
|
||||
logicPortType[135] = 1;
|
||||
logicPortPos[135] = "127 0 0";
|
||||
logicPortDir[135] = 2;
|
||||
logicPortUIName[135] = "Enable";
|
||||
logicPortCauseUpdate[135] = true;
|
||||
|
||||
logicPortType[136] = 0;
|
||||
logicPortPos[136] = "-127 0 0";
|
||||
logicPortDir[136] = 0;
|
||||
logicPortUIName[136] = "Out";
|
||||
|
||||
};
|
1379
bricks/gen/newcode/Mux 8 Bit Vertical.cs
Normal file
1379
bricks/gen/newcode/Mux 8 Bit Vertical.cs
Normal file
File diff suppressed because it is too large
Load Diff
1379
bricks/gen/newcode/Mux 8 Bit.cs
Normal file
1379
bricks/gen/newcode/Mux 8 Bit.cs
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,10 +1,10 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x16x1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 16x16";
|
||||
logicUIName = "ROM 16x16";
|
||||
logicUIDesc = "";
|
||||
@ -61,61 +61,58 @@ datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 16;
|
||||
logicRomZ = 1;
|
||||
logicRomX = 16;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -15 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -15 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -15 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -15 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -15 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Addr4";
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -15 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Addr5";
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -15 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Addr6";
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 -15 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "Addr7";
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "15 15 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "Out";
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "15 -15 0";
|
||||
logicPortDir[9] = 2;
|
||||
logicPortUIName[9] = "In";
|
||||
logicPortUIName[9] = "Clock";
|
||||
logicPortCauseUpdate[9] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom16x16_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
||||
|
198
bricks/gen/newcode/ROM 16x16x16.cs
Normal file
198
bricks/gen/newcode/ROM 16x16x16.cs
Normal file
@ -0,0 +1,198 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x16x16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16x16.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16x16";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 16x16x16";
|
||||
logicUIName = "ROM 16x16x16";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 16 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 4095 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 25)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" ) " @
|
||||
" for i = 0, 15 do " @
|
||||
" Gate.setportstate(gate, 9+i, gate.romdata[addr+256*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 9, 24 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 25;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 16;
|
||||
logicRomZ = 16;
|
||||
logicRomX = 16;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -15 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -15 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -15 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -15 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -15 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -15 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -15 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 -15 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "15 15 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "13 15 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "11 15 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "9 15 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "7 15 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "5 15 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "3 15 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "1 15 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-1 15 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O8";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-3 15 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O9";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-5 15 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O10";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-7 15 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O11";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-9 15 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O12";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-11 15 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O13";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-13 15 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O14";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-15 15 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O15";
|
||||
|
||||
logicPortType[24] = 1;
|
||||
logicPortPos[24] = "15 -15 0";
|
||||
logicPortDir[24] = 2;
|
||||
logicPortUIName[24] = "Clock";
|
||||
logicPortCauseUpdate[24] = true;
|
||||
|
||||
};
|
138
bricks/gen/newcode/ROM 16x16x4.cs
Normal file
138
bricks/gen/newcode/ROM 16x16x4.cs
Normal file
@ -0,0 +1,138 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x16x4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16x4.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16x4";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 16x16x4";
|
||||
logicUIName = "ROM 16x16x4";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 16 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 1023 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 13)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" ) " @
|
||||
" for i = 0, 3 do " @
|
||||
" Gate.setportstate(gate, 9+i, gate.romdata[addr+256*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 9, 12 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 16;
|
||||
logicRomZ = 4;
|
||||
logicRomX = 16;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -15 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -15 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -15 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -15 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -15 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -15 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -15 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 -15 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "15 15 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "13 15 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "11 15 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "9 15 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O3";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "15 -15 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
158
bricks/gen/newcode/ROM 16x16x8.cs
Normal file
158
bricks/gen/newcode/ROM 16x16x8.cs
Normal file
@ -0,0 +1,158 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x16x8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 16x16x8";
|
||||
logicUIName = "ROM 16x16x8";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 16 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 2047 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 17)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" ) " @
|
||||
" for i = 0, 7 do " @
|
||||
" Gate.setportstate(gate, 9+i, gate.romdata[addr+256*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 9, 16 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 17;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 16;
|
||||
logicRomZ = 8;
|
||||
logicRomX = 16;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -15 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -15 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -15 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -15 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -15 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -15 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -15 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "1 -15 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "15 15 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "13 15 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "11 15 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "9 15 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "7 15 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "5 15 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "3 15 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "1 15 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O7";
|
||||
|
||||
logicPortType[16] = 1;
|
||||
logicPortPos[16] = "15 -15 0";
|
||||
logicPortDir[16] = 2;
|
||||
logicPortUIName[16] = "Clock";
|
||||
logicPortCauseUpdate[16] = true;
|
||||
|
||||
};
|
186
bricks/gen/newcode/ROM 16x4x16.cs
Normal file
186
bricks/gen/newcode/ROM 16x4x16.cs
Normal file
@ -0,0 +1,186 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x4x16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x4x16.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x4x16";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 16x4x16";
|
||||
logicUIName = "ROM 16x4x16";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 4 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 1023 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 23)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" ) " @
|
||||
" for i = 0, 15 do " @
|
||||
" Gate.setportstate(gate, 7+i, gate.romdata[addr+64*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 7, 22 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 23;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 4;
|
||||
logicRomZ = 16;
|
||||
logicRomX = 16;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -3 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -3 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -3 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -3 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -3 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -3 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "15 3 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "13 3 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "11 3 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "9 3 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "7 3 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "5 3 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O5";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "3 3 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O6";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "1 3 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O7";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "-1 3 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O8";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "-3 3 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O9";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "-5 3 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O10";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "-7 3 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O11";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "-9 3 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O12";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "-11 3 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O13";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "-13 3 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O14";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "-15 3 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O15";
|
||||
|
||||
logicPortType[22] = 1;
|
||||
logicPortPos[22] = "15 -3 0";
|
||||
logicPortDir[22] = 2;
|
||||
logicPortUIName[22] = "Clock";
|
||||
logicPortCauseUpdate[22] = true;
|
||||
|
||||
};
|
@ -1,115 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom16x8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
uiName = "ROM 16x8";
|
||||
logicUIName = "ROM 16x8";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "16 8 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 127 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 9)~=0 then " @
|
||||
" Gate.setportstate(gate, 8, gate.romdata[( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" )]) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 8, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 8;
|
||||
logicRomX = 16;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "15 -7 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "13 -7 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "11 -7 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "9 -7 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "7 -7 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Addr4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "5 -7 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Addr5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "3 -7 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Addr6";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "15 7 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "Out";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -7 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "In";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom16x8_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
@ -1,127 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x16.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x16";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
uiName = "ROM 32x16";
|
||||
logicUIName = "ROM 32x16";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 16 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 511 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 11)~=0 then " @
|
||||
" Gate.setportstate(gate, 10, gate.romdata[( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" )]) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 10, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 16;
|
||||
logicRomX = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -15 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -15 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -15 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -15 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -15 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Addr4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -15 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Addr5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 -15 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Addr6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 -15 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "Addr7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -15 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "Addr8";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "31 15 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "Out";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "31 -15 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "In";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom32x16_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
266
bricks/gen/newcode/ROM 32x2x32.cs
Normal file
266
bricks/gen/newcode/ROM 32x2x32.cs
Normal file
@ -0,0 +1,266 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x2x32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x2x32.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x2x32";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 32x2x32";
|
||||
logicUIName = "ROM 32x2x32";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 2047 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 39)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" ) " @
|
||||
" for i = 0, 31 do " @
|
||||
" Gate.setportstate(gate, 7+i, gate.romdata[addr+64*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 7, 38 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 39;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 2;
|
||||
logicRomZ = 32;
|
||||
logicRomX = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -1 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -1 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "31 1 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "29 1 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "27 1 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "25 1 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "23 1 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "21 1 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O5";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "19 1 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O6";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "17 1 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O7";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "15 1 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O8";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "13 1 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O9";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "11 1 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O10";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "9 1 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O11";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "7 1 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O12";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "5 1 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O13";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "3 1 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O14";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "1 1 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O15";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "-1 1 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O16";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "-3 1 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O17";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-5 1 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O18";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-7 1 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O19";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-9 1 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O20";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-11 1 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O21";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-13 1 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O22";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-15 1 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O23";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-17 1 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O24";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-19 1 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O25";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "-21 1 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O26";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "-23 1 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O27";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "-25 1 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O28";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "-27 1 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O29";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-29 1 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O30";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-31 1 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O31";
|
||||
|
||||
logicPortType[38] = 1;
|
||||
logicPortPos[38] = "31 -1 0";
|
||||
logicPortDir[38] = 2;
|
||||
logicPortUIName[38] = "Clock";
|
||||
logicPortCauseUpdate[38] = true;
|
||||
|
||||
};
|
210
bricks/gen/newcode/ROM 32x32x16.cs
Normal file
210
bricks/gen/newcode/ROM 32x32x16.cs
Normal file
@ -0,0 +1,210 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x32x16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x32x16.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x32x16";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 32x32x16";
|
||||
logicUIName = "ROM 32x32x16";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 32 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 16383 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 27)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" ) " @
|
||||
" for i = 0, 15 do " @
|
||||
" Gate.setportstate(gate, 11+i, gate.romdata[addr+1024*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 11, 26 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 27;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 32;
|
||||
logicRomZ = 16;
|
||||
logicRomX = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -31 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -31 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -31 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -31 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -31 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -31 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 -31 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 -31 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -31 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -31 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "31 31 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "29 31 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "27 31 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "25 31 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "23 31 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "21 31 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "19 31 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "17 31 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "15 31 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "13 31 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O9";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "11 31 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O10";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "9 31 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O11";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "7 31 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O12";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "5 31 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O13";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "3 31 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O14";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "1 31 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O15";
|
||||
|
||||
logicPortType[26] = 1;
|
||||
logicPortPos[26] = "31 -31 0";
|
||||
logicPortDir[26] = 2;
|
||||
logicPortUIName[26] = "Clock";
|
||||
logicPortCauseUpdate[26] = true;
|
||||
|
||||
};
|
290
bricks/gen/newcode/ROM 32x32x32.cs
Normal file
290
bricks/gen/newcode/ROM 32x32x32.cs
Normal file
@ -0,0 +1,290 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x32x32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x32x32.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x32x32";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 32x32x32";
|
||||
logicUIName = "ROM 32x32x32";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 32 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 32767 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 43)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" ) " @
|
||||
" for i = 0, 31 do " @
|
||||
" Gate.setportstate(gate, 11+i, gate.romdata[addr+1024*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 11, 42 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 43;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 32;
|
||||
logicRomZ = 32;
|
||||
logicRomX = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -31 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -31 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -31 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -31 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -31 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -31 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 -31 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 -31 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -31 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -31 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "31 31 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "29 31 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "27 31 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "25 31 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "23 31 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "21 31 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "19 31 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "17 31 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "15 31 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "13 31 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O9";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "11 31 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O10";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "9 31 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O11";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "7 31 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O12";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "5 31 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O13";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "3 31 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O14";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "1 31 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O15";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-1 31 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O16";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-3 31 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O17";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-5 31 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O18";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-7 31 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O19";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-9 31 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O20";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-11 31 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O21";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "-13 31 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O22";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "-15 31 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O23";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "-17 31 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O24";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "-19 31 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O25";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-21 31 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O26";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-23 31 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O27";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-25 31 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O28";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-27 31 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O29";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-29 31 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O30";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-31 31 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O31";
|
||||
|
||||
logicPortType[42] = 1;
|
||||
logicPortPos[42] = "31 -31 0";
|
||||
logicPortDir[42] = 2;
|
||||
logicPortUIName[42] = "Clock";
|
||||
logicPortCauseUpdate[42] = true;
|
||||
|
||||
};
|
@ -1,12 +1,12 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x32.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x32";
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x32x8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x32x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x32x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
uiName = "ROM 32x32";
|
||||
logicUIName = "ROM 32x32";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 32x32x8";
|
||||
logicUIName = "ROM 32x32x8";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
@ -22,7 +22,7 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 1023 do " @
|
||||
" for i = 0, 8191 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
@ -39,8 +39,8 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 12)~=0 then " @
|
||||
" Gate.setportstate(gate, 11, gate.romdata[( " @
|
||||
" if Gate.getportstate(gate, 19)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
@ -51,83 +51,120 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" )]) " @
|
||||
" ) " @
|
||||
" for i = 0, 7 do " @
|
||||
" Gate.setportstate(gate, 11+i, gate.romdata[addr+1024*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 11, 0) " @
|
||||
" for i = 11, 18 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 12;
|
||||
numLogicPorts = 19;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 32;
|
||||
logicRomZ = 8;
|
||||
logicRomX = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -31 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -31 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -31 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -31 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -31 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Addr4";
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -31 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Addr5";
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 -31 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "Addr6";
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 -31 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "Addr7";
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "15 -31 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "Addr8";
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "13 -31 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "Addr9";
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "31 31 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "Out";
|
||||
logicPortUIName[10] = "O0";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "31 -31 0";
|
||||
logicPortDir[11] = 2;
|
||||
logicPortUIName[11] = "In";
|
||||
logicPortCauseUpdate[11] = true;
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "29 31 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "27 31 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "25 31 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "23 31 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "21 31 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "19 31 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "17 31 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O7";
|
||||
|
||||
logicPortType[18] = 1;
|
||||
logicPortPos[18] = "31 -31 0";
|
||||
logicPortDir[18] = 2;
|
||||
logicPortUIName[18] = "Clock";
|
||||
logicPortCauseUpdate[18] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom32x32_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
278
bricks/gen/newcode/ROM 32x8x32.cs
Normal file
278
bricks/gen/newcode/ROM 32x8x32.cs
Normal file
@ -0,0 +1,278 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom32x8x32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 32x8x32.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 32x8x32";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 32x8x32";
|
||||
logicUIName = "ROM 32x8x32";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "32 8 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 8191 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 41)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" ) " @
|
||||
" for i = 0, 31 do " @
|
||||
" Gate.setportstate(gate, 9+i, gate.romdata[addr+256*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 9, 40 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 41;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 8;
|
||||
logicRomZ = 32;
|
||||
logicRomX = 32;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "31 -7 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "29 -7 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "27 -7 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "25 -7 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "23 -7 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "21 -7 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "19 -7 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "17 -7 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "31 7 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "29 7 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "27 7 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "25 7 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "23 7 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "21 7 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "19 7 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "17 7 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "15 7 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O8";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "13 7 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O9";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "11 7 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O10";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "9 7 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O11";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "7 7 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O12";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "5 7 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O13";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "3 7 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O14";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "1 7 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O15";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "-1 7 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O16";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "-3 7 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O17";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "-5 7 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O18";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "-7 7 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O19";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "-9 7 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O20";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "-11 7 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O21";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "-13 7 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O22";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "-15 7 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O23";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "-17 7 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O24";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "-19 7 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O25";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "-21 7 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O26";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "-23 7 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O27";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "-25 7 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O28";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "-27 7 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O29";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-29 7 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O30";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-31 7 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O31";
|
||||
|
||||
logicPortType[40] = 1;
|
||||
logicPortPos[40] = "31 -7 0";
|
||||
logicPortDir[40] = 2;
|
||||
logicPortUIName[40] = "Clock";
|
||||
logicPortCauseUpdate[40] = true;
|
||||
|
||||
};
|
@ -1,10 +1,10 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom4x4_Data){
|
||||
datablock fxDtsBrickData(LogicGate_Rom4x4x1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 4x4.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 4x4";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 4x4";
|
||||
logicUIName = "ROM 4x4";
|
||||
logicUIDesc = "";
|
||||
@ -57,41 +57,38 @@ datablock fxDtsBrickData(LogicGate_Rom4x4_Data){
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 4;
|
||||
logicRomZ = 1;
|
||||
logicRomX = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 -3 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 -3 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 -3 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 -3 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 3 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "Out";
|
||||
logicPortUIName[4] = "O0";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "3 -3 0";
|
||||
logicPortDir[5] = 2;
|
||||
logicPortUIName[5] = "In";
|
||||
logicPortUIName[5] = "Clock";
|
||||
logicPortCauseUpdate[5] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom4x4_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
||||
|
114
bricks/gen/newcode/ROM 4x4x4.cs
Normal file
114
bricks/gen/newcode/ROM 4x4x4.cs
Normal file
@ -0,0 +1,114 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom4x4x4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 4x4x4.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 4x4x4";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 4x4x4";
|
||||
logicUIName = "ROM 4x4x4";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "4 4 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 63 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 9)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" ) " @
|
||||
" for i = 0, 3 do " @
|
||||
" Gate.setportstate(gate, 5+i, gate.romdata[addr+16*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 5, 8 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 9;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 4;
|
||||
logicRomZ = 4;
|
||||
logicRomX = 4;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "3 -3 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "1 -3 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "-1 -3 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "-3 -3 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "3 3 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "O0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "1 3 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "O1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "-1 3 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "-3 3 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O3";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "3 -3 0";
|
||||
logicPortDir[8] = 2;
|
||||
logicPortUIName[8] = "Clock";
|
||||
logicPortCauseUpdate[8] = true;
|
||||
|
||||
};
|
450
bricks/gen/newcode/ROM 64x16x64.cs
Normal file
450
bricks/gen/newcode/ROM 64x16x64.cs
Normal file
@ -0,0 +1,450 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x16x64_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x16x64.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x16x64";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x16x64";
|
||||
logicUIName = "ROM 64x16x64";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 16 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 65535 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 75)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" ) " @
|
||||
" for i = 0, 63 do " @
|
||||
" Gate.setportstate(gate, 11+i, gate.romdata[addr+1024*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 11, 74 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 75;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 16;
|
||||
logicRomZ = 64;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -15 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -15 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -15 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -15 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -15 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -15 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -15 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -15 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 -15 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 -15 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "63 15 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O0";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "61 15 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O1";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "59 15 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O2";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "57 15 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O3";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "55 15 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O4";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "53 15 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O5";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "51 15 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O6";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "49 15 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O7";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "47 15 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O8";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "45 15 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O9";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "43 15 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O10";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "41 15 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O11";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "39 15 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O12";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "37 15 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O13";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "35 15 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O14";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "33 15 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O15";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "31 15 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O16";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "29 15 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O17";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "27 15 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O18";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "25 15 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O19";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "23 15 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O20";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "21 15 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O21";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "19 15 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O22";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "17 15 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O23";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "15 15 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O24";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "13 15 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O25";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "11 15 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O26";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "9 15 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O27";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "7 15 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O28";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "5 15 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O29";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "3 15 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O30";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "1 15 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O31";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-1 15 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "O32";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-3 15 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "O33";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-5 15 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "O34";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-7 15 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "O35";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-9 15 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "O36";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-11 15 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "O37";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-13 15 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "O38";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-15 15 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "O39";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-17 15 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "O40";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-19 15 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "O41";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-21 15 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "O42";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-23 15 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "O43";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-25 15 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "O44";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-27 15 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "O45";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-29 15 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "O46";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-31 15 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "O47";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-33 15 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "O48";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-35 15 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "O49";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-37 15 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "O50";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-39 15 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "O51";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-41 15 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "O52";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-43 15 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "O53";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "-45 15 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "O54";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "-47 15 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "O55";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "-49 15 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "O56";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "-51 15 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "O57";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "-53 15 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "O58";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "-55 15 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "O59";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "-57 15 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "O60";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "-59 15 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "O61";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "-61 15 0";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "O62";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "-63 15 0";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "O63";
|
||||
|
||||
logicPortType[74] = 1;
|
||||
logicPortPos[74] = "63 -15 0";
|
||||
logicPortDir[74] = 2;
|
||||
logicPortUIName[74] = "Clock";
|
||||
logicPortCauseUpdate[74] = true;
|
||||
|
||||
};
|
426
bricks/gen/newcode/ROM 64x1x64.cs
Normal file
426
bricks/gen/newcode/ROM 64x1x64.cs
Normal file
@ -0,0 +1,426 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x1x64_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x1x64.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x1x64";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x1x64";
|
||||
logicUIName = "ROM 64x1x64";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 1 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 4095 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 71)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" ) " @
|
||||
" for i = 0, 63 do " @
|
||||
" Gate.setportstate(gate, 7+i, gate.romdata[addr+64*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 7, 70 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 71;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 1;
|
||||
logicRomZ = 64;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -0 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -0 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -0 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -0 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -0 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -0 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "63 0 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "61 0 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "59 0 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "57 0 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "55 0 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "53 0 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O5";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "51 0 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O6";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "49 0 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O7";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "47 0 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O8";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "45 0 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O9";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "43 0 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O10";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "41 0 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O11";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "39 0 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O12";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "37 0 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O13";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "35 0 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O14";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "33 0 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O15";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "31 0 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O16";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "29 0 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O17";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "27 0 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O18";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "25 0 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O19";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "23 0 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O20";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "21 0 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O21";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "19 0 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O22";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "17 0 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O23";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "15 0 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O24";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "13 0 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O25";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "11 0 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O26";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "9 0 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O27";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "7 0 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O28";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "5 0 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O29";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "3 0 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O30";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "1 0 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O31";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "-1 0 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O32";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "-3 0 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O33";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-5 0 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O34";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-7 0 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O35";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-9 0 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "O36";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-11 0 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "O37";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-13 0 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "O38";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-15 0 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "O39";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-17 0 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "O40";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-19 0 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "O41";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-21 0 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "O42";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-23 0 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "O43";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-25 0 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "O44";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-27 0 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "O45";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-29 0 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "O46";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-31 0 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "O47";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-33 0 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "O48";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-35 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "O49";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-37 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "O50";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-39 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "O51";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-41 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "O52";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-43 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "O53";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-45 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "O54";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-47 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "O55";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-49 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "O56";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-51 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "O57";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "-53 0 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "O58";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "-55 0 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "O59";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "-57 0 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "O60";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "-59 0 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "O61";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "-61 0 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "O62";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "-63 0 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "O63";
|
||||
|
||||
logicPortType[70] = 1;
|
||||
logicPortPos[70] = "63 -0 0";
|
||||
logicPortDir[70] = 2;
|
||||
logicPortUIName[70] = "Clock";
|
||||
logicPortCauseUpdate[70] = true;
|
||||
|
||||
};
|
438
bricks/gen/newcode/ROM 64x4x64.cs
Normal file
438
bricks/gen/newcode/ROM 64x4x64.cs
Normal file
@ -0,0 +1,438 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x4x64_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x4x64.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x4x64";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x4x64";
|
||||
logicUIName = "ROM 64x4x64";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 4 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 16383 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 73)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" ) " @
|
||||
" for i = 0, 63 do " @
|
||||
" Gate.setportstate(gate, 9+i, gate.romdata[addr+256*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 9, 72 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 73;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 4;
|
||||
logicRomZ = 64;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -3 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -3 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -3 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -3 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -3 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -3 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -3 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -3 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "63 3 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O0";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "61 3 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O1";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "59 3 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O2";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "57 3 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O3";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "55 3 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O4";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "53 3 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O5";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "51 3 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O6";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "49 3 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O7";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "47 3 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O8";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "45 3 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O9";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "43 3 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O10";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "41 3 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O11";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "39 3 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O12";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "37 3 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O13";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "35 3 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O14";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "33 3 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O15";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "31 3 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O16";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "29 3 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O17";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "27 3 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O18";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "25 3 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O19";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "23 3 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O20";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "21 3 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O21";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "19 3 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O22";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "17 3 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O23";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "15 3 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O24";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "13 3 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O25";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "11 3 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O26";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "9 3 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O27";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "7 3 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O28";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "5 3 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O29";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "3 3 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O30";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "1 3 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O31";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "-1 3 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O32";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "-3 3 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O33";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "-5 3 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "O34";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "-7 3 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "O35";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-9 3 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "O36";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-11 3 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "O37";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-13 3 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "O38";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-15 3 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "O39";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-17 3 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "O40";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-19 3 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "O41";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-21 3 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "O42";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-23 3 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "O43";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-25 3 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "O44";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-27 3 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "O45";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-29 3 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "O46";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-31 3 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "O47";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-33 3 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "O48";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-35 3 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "O49";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-37 3 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "O50";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-39 3 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "O51";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-41 3 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "O52";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-43 3 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "O53";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-45 3 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "O54";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-47 3 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "O55";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "-49 3 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "O56";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "-51 3 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "O57";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "-53 3 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "O58";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "-55 3 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "O59";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "-57 3 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "O60";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "-59 3 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "O61";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "-61 3 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "O62";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "-63 3 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "O63";
|
||||
|
||||
logicPortType[72] = 1;
|
||||
logicPortPos[72] = "63 -3 0";
|
||||
logicPortDir[72] = 2;
|
||||
logicPortUIName[72] = "Clock";
|
||||
logicPortCauseUpdate[72] = true;
|
||||
|
||||
};
|
222
bricks/gen/newcode/ROM 64x64x16.cs
Normal file
222
bricks/gen/newcode/ROM 64x64x16.cs
Normal file
@ -0,0 +1,222 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x64x16_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x64x16.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x64x16";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x64x16";
|
||||
logicUIName = "ROM 64x64x16";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 64 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 65535 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 29)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" + (Gate.getportstate(gate, 11) * 1024) " @
|
||||
" + (Gate.getportstate(gate, 12) * 2048) " @
|
||||
" ) " @
|
||||
" for i = 0, 15 do " @
|
||||
" Gate.setportstate(gate, 13+i, gate.romdata[addr+4096*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 13, 28 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 29;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 64;
|
||||
logicRomZ = 16;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -63 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -63 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -63 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -63 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -63 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -63 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -63 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -63 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 -63 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 -63 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 -63 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "A10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 -63 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "A11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "63 63 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "61 63 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "59 63 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "57 63 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "55 63 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "53 63 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "51 63 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "49 63 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "47 63 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "45 63 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "43 63 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "41 63 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O11";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "39 63 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O12";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "37 63 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O13";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "35 63 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O14";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "33 63 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O15";
|
||||
|
||||
logicPortType[28] = 1;
|
||||
logicPortPos[28] = "63 -63 0";
|
||||
logicPortDir[28] = 2;
|
||||
logicPortUIName[28] = "Clock";
|
||||
logicPortCauseUpdate[28] = true;
|
||||
|
||||
};
|
302
bricks/gen/newcode/ROM 64x64x32.cs
Normal file
302
bricks/gen/newcode/ROM 64x64x32.cs
Normal file
@ -0,0 +1,302 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x64x32_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x64x32.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x64x32";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x64x32";
|
||||
logicUIName = "ROM 64x64x32";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 64 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 131071 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 45)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" + (Gate.getportstate(gate, 11) * 1024) " @
|
||||
" + (Gate.getportstate(gate, 12) * 2048) " @
|
||||
" ) " @
|
||||
" for i = 0, 31 do " @
|
||||
" Gate.setportstate(gate, 13+i, gate.romdata[addr+4096*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 13, 44 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 45;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 64;
|
||||
logicRomZ = 32;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -63 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -63 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -63 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -63 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -63 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -63 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -63 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -63 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 -63 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 -63 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 -63 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "A10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 -63 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "A11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "63 63 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "61 63 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "59 63 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "57 63 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "55 63 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "53 63 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "51 63 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "49 63 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "47 63 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "45 63 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "43 63 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "41 63 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O11";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "39 63 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O12";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "37 63 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O13";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "35 63 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O14";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "33 63 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O15";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "31 63 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O16";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "29 63 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O17";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "27 63 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O18";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "25 63 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O19";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "23 63 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O20";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "21 63 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O21";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "19 63 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O22";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "17 63 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O23";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "15 63 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O24";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "13 63 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O25";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "11 63 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O26";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "9 63 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O27";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "7 63 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O28";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "5 63 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O29";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "3 63 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "O30";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "1 63 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "O31";
|
||||
|
||||
logicPortType[44] = 1;
|
||||
logicPortPos[44] = "63 -63 0";
|
||||
logicPortDir[44] = 2;
|
||||
logicPortUIName[44] = "Clock";
|
||||
logicPortCauseUpdate[44] = true;
|
||||
|
||||
};
|
462
bricks/gen/newcode/ROM 64x64x64.cs
Normal file
462
bricks/gen/newcode/ROM 64x64x64.cs
Normal file
@ -0,0 +1,462 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x64x64_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x64x64.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x64x64";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x64x64";
|
||||
logicUIName = "ROM 64x64x64";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 64 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 262143 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 77)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" + (Gate.getportstate(gate, 11) * 1024) " @
|
||||
" + (Gate.getportstate(gate, 12) * 2048) " @
|
||||
" ) " @
|
||||
" for i = 0, 63 do " @
|
||||
" Gate.setportstate(gate, 13+i, gate.romdata[addr+4096*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 13, 76 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 77;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 64;
|
||||
logicRomZ = 64;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -63 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -63 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -63 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -63 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -63 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -63 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -63 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -63 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 -63 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 -63 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 -63 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "A10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 -63 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "A11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "63 63 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "61 63 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "59 63 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "57 63 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "55 63 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "53 63 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "51 63 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "49 63 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O7";
|
||||
|
||||
logicPortType[20] = 0;
|
||||
logicPortPos[20] = "47 63 0";
|
||||
logicPortDir[20] = 1;
|
||||
logicPortUIName[20] = "O8";
|
||||
|
||||
logicPortType[21] = 0;
|
||||
logicPortPos[21] = "45 63 0";
|
||||
logicPortDir[21] = 1;
|
||||
logicPortUIName[21] = "O9";
|
||||
|
||||
logicPortType[22] = 0;
|
||||
logicPortPos[22] = "43 63 0";
|
||||
logicPortDir[22] = 1;
|
||||
logicPortUIName[22] = "O10";
|
||||
|
||||
logicPortType[23] = 0;
|
||||
logicPortPos[23] = "41 63 0";
|
||||
logicPortDir[23] = 1;
|
||||
logicPortUIName[23] = "O11";
|
||||
|
||||
logicPortType[24] = 0;
|
||||
logicPortPos[24] = "39 63 0";
|
||||
logicPortDir[24] = 1;
|
||||
logicPortUIName[24] = "O12";
|
||||
|
||||
logicPortType[25] = 0;
|
||||
logicPortPos[25] = "37 63 0";
|
||||
logicPortDir[25] = 1;
|
||||
logicPortUIName[25] = "O13";
|
||||
|
||||
logicPortType[26] = 0;
|
||||
logicPortPos[26] = "35 63 0";
|
||||
logicPortDir[26] = 1;
|
||||
logicPortUIName[26] = "O14";
|
||||
|
||||
logicPortType[27] = 0;
|
||||
logicPortPos[27] = "33 63 0";
|
||||
logicPortDir[27] = 1;
|
||||
logicPortUIName[27] = "O15";
|
||||
|
||||
logicPortType[28] = 0;
|
||||
logicPortPos[28] = "31 63 0";
|
||||
logicPortDir[28] = 1;
|
||||
logicPortUIName[28] = "O16";
|
||||
|
||||
logicPortType[29] = 0;
|
||||
logicPortPos[29] = "29 63 0";
|
||||
logicPortDir[29] = 1;
|
||||
logicPortUIName[29] = "O17";
|
||||
|
||||
logicPortType[30] = 0;
|
||||
logicPortPos[30] = "27 63 0";
|
||||
logicPortDir[30] = 1;
|
||||
logicPortUIName[30] = "O18";
|
||||
|
||||
logicPortType[31] = 0;
|
||||
logicPortPos[31] = "25 63 0";
|
||||
logicPortDir[31] = 1;
|
||||
logicPortUIName[31] = "O19";
|
||||
|
||||
logicPortType[32] = 0;
|
||||
logicPortPos[32] = "23 63 0";
|
||||
logicPortDir[32] = 1;
|
||||
logicPortUIName[32] = "O20";
|
||||
|
||||
logicPortType[33] = 0;
|
||||
logicPortPos[33] = "21 63 0";
|
||||
logicPortDir[33] = 1;
|
||||
logicPortUIName[33] = "O21";
|
||||
|
||||
logicPortType[34] = 0;
|
||||
logicPortPos[34] = "19 63 0";
|
||||
logicPortDir[34] = 1;
|
||||
logicPortUIName[34] = "O22";
|
||||
|
||||
logicPortType[35] = 0;
|
||||
logicPortPos[35] = "17 63 0";
|
||||
logicPortDir[35] = 1;
|
||||
logicPortUIName[35] = "O23";
|
||||
|
||||
logicPortType[36] = 0;
|
||||
logicPortPos[36] = "15 63 0";
|
||||
logicPortDir[36] = 1;
|
||||
logicPortUIName[36] = "O24";
|
||||
|
||||
logicPortType[37] = 0;
|
||||
logicPortPos[37] = "13 63 0";
|
||||
logicPortDir[37] = 1;
|
||||
logicPortUIName[37] = "O25";
|
||||
|
||||
logicPortType[38] = 0;
|
||||
logicPortPos[38] = "11 63 0";
|
||||
logicPortDir[38] = 1;
|
||||
logicPortUIName[38] = "O26";
|
||||
|
||||
logicPortType[39] = 0;
|
||||
logicPortPos[39] = "9 63 0";
|
||||
logicPortDir[39] = 1;
|
||||
logicPortUIName[39] = "O27";
|
||||
|
||||
logicPortType[40] = 0;
|
||||
logicPortPos[40] = "7 63 0";
|
||||
logicPortDir[40] = 1;
|
||||
logicPortUIName[40] = "O28";
|
||||
|
||||
logicPortType[41] = 0;
|
||||
logicPortPos[41] = "5 63 0";
|
||||
logicPortDir[41] = 1;
|
||||
logicPortUIName[41] = "O29";
|
||||
|
||||
logicPortType[42] = 0;
|
||||
logicPortPos[42] = "3 63 0";
|
||||
logicPortDir[42] = 1;
|
||||
logicPortUIName[42] = "O30";
|
||||
|
||||
logicPortType[43] = 0;
|
||||
logicPortPos[43] = "1 63 0";
|
||||
logicPortDir[43] = 1;
|
||||
logicPortUIName[43] = "O31";
|
||||
|
||||
logicPortType[44] = 0;
|
||||
logicPortPos[44] = "-1 63 0";
|
||||
logicPortDir[44] = 1;
|
||||
logicPortUIName[44] = "O32";
|
||||
|
||||
logicPortType[45] = 0;
|
||||
logicPortPos[45] = "-3 63 0";
|
||||
logicPortDir[45] = 1;
|
||||
logicPortUIName[45] = "O33";
|
||||
|
||||
logicPortType[46] = 0;
|
||||
logicPortPos[46] = "-5 63 0";
|
||||
logicPortDir[46] = 1;
|
||||
logicPortUIName[46] = "O34";
|
||||
|
||||
logicPortType[47] = 0;
|
||||
logicPortPos[47] = "-7 63 0";
|
||||
logicPortDir[47] = 1;
|
||||
logicPortUIName[47] = "O35";
|
||||
|
||||
logicPortType[48] = 0;
|
||||
logicPortPos[48] = "-9 63 0";
|
||||
logicPortDir[48] = 1;
|
||||
logicPortUIName[48] = "O36";
|
||||
|
||||
logicPortType[49] = 0;
|
||||
logicPortPos[49] = "-11 63 0";
|
||||
logicPortDir[49] = 1;
|
||||
logicPortUIName[49] = "O37";
|
||||
|
||||
logicPortType[50] = 0;
|
||||
logicPortPos[50] = "-13 63 0";
|
||||
logicPortDir[50] = 1;
|
||||
logicPortUIName[50] = "O38";
|
||||
|
||||
logicPortType[51] = 0;
|
||||
logicPortPos[51] = "-15 63 0";
|
||||
logicPortDir[51] = 1;
|
||||
logicPortUIName[51] = "O39";
|
||||
|
||||
logicPortType[52] = 0;
|
||||
logicPortPos[52] = "-17 63 0";
|
||||
logicPortDir[52] = 1;
|
||||
logicPortUIName[52] = "O40";
|
||||
|
||||
logicPortType[53] = 0;
|
||||
logicPortPos[53] = "-19 63 0";
|
||||
logicPortDir[53] = 1;
|
||||
logicPortUIName[53] = "O41";
|
||||
|
||||
logicPortType[54] = 0;
|
||||
logicPortPos[54] = "-21 63 0";
|
||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "O42";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "-23 63 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "O43";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "-25 63 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "O44";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "-27 63 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "O45";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "-29 63 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "O46";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "-31 63 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "O47";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "-33 63 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "O48";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "-35 63 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "O49";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "-37 63 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "O50";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "-39 63 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "O51";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "-41 63 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "O52";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "-43 63 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "O53";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "-45 63 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "O54";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "-47 63 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "O55";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "-49 63 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "O56";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "-51 63 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "O57";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "-53 63 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "O58";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "-55 63 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "O59";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "-57 63 0";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "O60";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "-59 63 0";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "O61";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "-61 63 0";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "O62";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "-63 63 0";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "O63";
|
||||
|
||||
logicPortType[76] = 1;
|
||||
logicPortPos[76] = "63 -63 0";
|
||||
logicPortDir[76] = 2;
|
||||
logicPortUIName[76] = "Clock";
|
||||
logicPortCauseUpdate[76] = true;
|
||||
|
||||
};
|
182
bricks/gen/newcode/ROM 64x64x8.cs
Normal file
182
bricks/gen/newcode/ROM 64x64x8.cs
Normal file
@ -0,0 +1,182 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom64x64x8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 64x64x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 64x64x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 64x64x8";
|
||||
logicUIName = "ROM 64x64x8";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "64 64 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 32767 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 21)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" + (Gate.getportstate(gate, 7) * 64) " @
|
||||
" + (Gate.getportstate(gate, 8) * 128) " @
|
||||
" + (Gate.getportstate(gate, 9) * 256) " @
|
||||
" + (Gate.getportstate(gate, 10) * 512) " @
|
||||
" + (Gate.getportstate(gate, 11) * 1024) " @
|
||||
" + (Gate.getportstate(gate, 12) * 2048) " @
|
||||
" ) " @
|
||||
" for i = 0, 7 do " @
|
||||
" Gate.setportstate(gate, 13+i, gate.romdata[addr+4096*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 13, 20 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 21;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 64;
|
||||
logicRomZ = 8;
|
||||
logicRomX = 64;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "63 -63 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "61 -63 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "59 -63 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "57 -63 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "55 -63 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "53 -63 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "51 -63 0";
|
||||
logicPortDir[6] = 3;
|
||||
logicPortUIName[6] = "A6";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "49 -63 0";
|
||||
logicPortDir[7] = 3;
|
||||
logicPortUIName[7] = "A7";
|
||||
|
||||
logicPortType[8] = 1;
|
||||
logicPortPos[8] = "47 -63 0";
|
||||
logicPortDir[8] = 3;
|
||||
logicPortUIName[8] = "A8";
|
||||
|
||||
logicPortType[9] = 1;
|
||||
logicPortPos[9] = "45 -63 0";
|
||||
logicPortDir[9] = 3;
|
||||
logicPortUIName[9] = "A9";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "43 -63 0";
|
||||
logicPortDir[10] = 3;
|
||||
logicPortUIName[10] = "A10";
|
||||
|
||||
logicPortType[11] = 1;
|
||||
logicPortPos[11] = "41 -63 0";
|
||||
logicPortDir[11] = 3;
|
||||
logicPortUIName[11] = "A11";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "63 63 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O0";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "61 63 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O1";
|
||||
|
||||
logicPortType[14] = 0;
|
||||
logicPortPos[14] = "59 63 0";
|
||||
logicPortDir[14] = 1;
|
||||
logicPortUIName[14] = "O2";
|
||||
|
||||
logicPortType[15] = 0;
|
||||
logicPortPos[15] = "57 63 0";
|
||||
logicPortDir[15] = 1;
|
||||
logicPortUIName[15] = "O3";
|
||||
|
||||
logicPortType[16] = 0;
|
||||
logicPortPos[16] = "55 63 0";
|
||||
logicPortDir[16] = 1;
|
||||
logicPortUIName[16] = "O4";
|
||||
|
||||
logicPortType[17] = 0;
|
||||
logicPortPos[17] = "53 63 0";
|
||||
logicPortDir[17] = 1;
|
||||
logicPortUIName[17] = "O5";
|
||||
|
||||
logicPortType[18] = 0;
|
||||
logicPortPos[18] = "51 63 0";
|
||||
logicPortDir[18] = 1;
|
||||
logicPortUIName[18] = "O6";
|
||||
|
||||
logicPortType[19] = 0;
|
||||
logicPortPos[19] = "49 63 0";
|
||||
logicPortDir[19] = 1;
|
||||
logicPortUIName[19] = "O7";
|
||||
|
||||
logicPortType[20] = 1;
|
||||
logicPortPos[20] = "63 -63 0";
|
||||
logicPortDir[20] = 2;
|
||||
logicPortUIName[20] = "Clock";
|
||||
logicPortCauseUpdate[20] = true;
|
||||
|
||||
};
|
134
bricks/gen/newcode/ROM 8x2x8.cs
Normal file
134
bricks/gen/newcode/ROM 8x2x8.cs
Normal file
@ -0,0 +1,134 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom8x2x8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 8x2x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 8x2x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 8x2x8";
|
||||
logicUIName = "ROM 8x2x8";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 2 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 127 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 13)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" ) " @
|
||||
" for i = 0, 7 do " @
|
||||
" Gate.setportstate(gate, 5+i, gate.romdata[addr+16*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 5, 12 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 13;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 2;
|
||||
logicRomZ = 8;
|
||||
logicRomX = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 -1 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 -1 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 -1 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -1 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 0;
|
||||
logicPortPos[4] = "7 1 0";
|
||||
logicPortDir[4] = 1;
|
||||
logicPortUIName[4] = "O0";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "5 1 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "O1";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "3 1 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O2";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "1 1 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O3";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "-1 1 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O4";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "-3 1 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O5";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-5 1 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O6";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-7 1 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O7";
|
||||
|
||||
logicPortType[12] = 1;
|
||||
logicPortPos[12] = "7 -1 0";
|
||||
logicPortDir[12] = 2;
|
||||
logicPortUIName[12] = "Clock";
|
||||
logicPortCauseUpdate[12] = true;
|
||||
|
||||
};
|
@ -1,103 +0,0 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom8x4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 8x4.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 8x4";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
uiName = "ROM 8x4";
|
||||
logicUIName = "ROM 8x4";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 4 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 31 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 7)~=0 then " @
|
||||
" Gate.setportstate(gate, 6, gate.romdata[( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" )]) " @
|
||||
" else " @
|
||||
" Gate.setportstate(gate, 6, 0) " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 7;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 4;
|
||||
logicRomX = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 -3 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 -3 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 -3 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -3 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 -3 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Addr4";
|
||||
|
||||
logicPortType[5] = 0;
|
||||
logicPortPos[5] = "7 3 0";
|
||||
logicPortDir[5] = 1;
|
||||
logicPortUIName[5] = "Out";
|
||||
|
||||
logicPortType[6] = 1;
|
||||
logicPortPos[6] = "7 -3 0";
|
||||
logicPortDir[6] = 2;
|
||||
logicPortUIName[6] = "In";
|
||||
logicPortCauseUpdate[6] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom8x4_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
@ -1,10 +1,10 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom8x8_Data){
|
||||
datablock fxDtsBrickData(LogicGate_Rom8x8x1_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 8x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 8x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "Special I/O";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 8x8";
|
||||
logicUIName = "ROM 8x8";
|
||||
logicUIDesc = "";
|
||||
@ -59,51 +59,48 @@ datablock fxDtsBrickData(LogicGate_Rom8x8_Data){
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 8;
|
||||
logicRomZ = 1;
|
||||
logicRomX = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 -7 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "Addr0";
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 -7 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "Addr1";
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 -7 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "Addr2";
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -7 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "Addr3";
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 -7 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "Addr4";
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 -7 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "Addr5";
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "7 7 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "Out";
|
||||
logicPortUIName[6] = "O0";
|
||||
|
||||
logicPortType[7] = 1;
|
||||
logicPortPos[7] = "7 -7 0";
|
||||
logicPortDir[7] = 2;
|
||||
logicPortUIName[7] = "In";
|
||||
logicPortUIName[7] = "Clock";
|
||||
logicPortCauseUpdate[7] = true;
|
||||
|
||||
};
|
||||
|
||||
function LogicGate_Rom8x8_Data::Logic_onAdd(%data, %brick) {
|
||||
lualogic_rom_updatedata(%brick);
|
||||
}
|
||||
|
126
bricks/gen/newcode/ROM 8x8x4.cs
Normal file
126
bricks/gen/newcode/ROM 8x8x4.cs
Normal file
@ -0,0 +1,126 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom8x8x4_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 8x8x4.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 8x8x4";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 8x8x4";
|
||||
logicUIName = "ROM 8x8x4";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 8 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 255 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 11)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" ) " @
|
||||
" for i = 0, 3 do " @
|
||||
" Gate.setportstate(gate, 7+i, gate.romdata[addr+64*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 7, 10 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 11;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 8;
|
||||
logicRomZ = 4;
|
||||
logicRomX = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 -7 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 -7 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 -7 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -7 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 -7 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 -7 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "7 7 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "5 7 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "3 7 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "1 7 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O3";
|
||||
|
||||
logicPortType[10] = 1;
|
||||
logicPortPos[10] = "7 -7 0";
|
||||
logicPortDir[10] = 2;
|
||||
logicPortUIName[10] = "Clock";
|
||||
logicPortCauseUpdate[10] = true;
|
||||
|
||||
};
|
146
bricks/gen/newcode/ROM 8x8x8.cs
Normal file
146
bricks/gen/newcode/ROM 8x8x8.cs
Normal file
@ -0,0 +1,146 @@
|
||||
|
||||
datablock fxDtsBrickData(LogicGate_Rom8x8x8_Data){
|
||||
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 8x8x8.blb";
|
||||
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 8x8x8";
|
||||
|
||||
category = "Logic Bricks";
|
||||
subCategory = "ROM";
|
||||
uiName = "ROM 8x8x8";
|
||||
logicUIName = "ROM 8x8x8";
|
||||
logicUIDesc = "";
|
||||
|
||||
hasPrint = 1;
|
||||
printAspectRatio = "Logic";
|
||||
|
||||
logicBrickSize = "8 8 1";
|
||||
orientationFix = 3;
|
||||
|
||||
isLogic = true;
|
||||
isLogicGate = true;
|
||||
isLogicInput = false;
|
||||
|
||||
logicInit =
|
||||
"return function(gate) " @
|
||||
" gate.romdata = {} " @
|
||||
" for i = 0, 511 do " @
|
||||
" gate.romdata[i] = 0 " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicInput =
|
||||
"return function(gate, args) " @
|
||||
" local data = args[1] " @
|
||||
" for i = 1, #data do " @
|
||||
" local c = data:sub(i, i) " @
|
||||
" gate.romdata[i-1] = (c==\"1\") and 1 or 0 " @
|
||||
" end " @
|
||||
" Gate.queue(gate, 0) " @
|
||||
"end"
|
||||
;
|
||||
logicUpdate =
|
||||
"return function(gate) " @
|
||||
" if Gate.getportstate(gate, 15)~=0 then " @
|
||||
" local addr = ( " @
|
||||
" (Gate.getportstate(gate, 1)) " @
|
||||
" + (Gate.getportstate(gate, 2) * 2) " @
|
||||
" + (Gate.getportstate(gate, 3) * 4) " @
|
||||
" + (Gate.getportstate(gate, 4) * 8) " @
|
||||
" + (Gate.getportstate(gate, 5) * 16) " @
|
||||
" + (Gate.getportstate(gate, 6) * 32) " @
|
||||
" ) " @
|
||||
" for i = 0, 7 do " @
|
||||
" Gate.setportstate(gate, 7+i, gate.romdata[addr+64*i]) " @
|
||||
" end " @
|
||||
" else " @
|
||||
" for i = 7, 14 do " @
|
||||
" Gate.setportstate(gate, i, 0) " @
|
||||
" end " @
|
||||
" end " @
|
||||
"end"
|
||||
;
|
||||
logicGlobal = "";
|
||||
|
||||
numLogicPorts = 15;
|
||||
|
||||
isLogicRom = true;
|
||||
logicRomY = 8;
|
||||
logicRomZ = 8;
|
||||
logicRomX = 8;
|
||||
|
||||
logicPortType[0] = 1;
|
||||
logicPortPos[0] = "7 -7 0";
|
||||
logicPortDir[0] = 3;
|
||||
logicPortUIName[0] = "A0";
|
||||
|
||||
logicPortType[1] = 1;
|
||||
logicPortPos[1] = "5 -7 0";
|
||||
logicPortDir[1] = 3;
|
||||
logicPortUIName[1] = "A1";
|
||||
|
||||
logicPortType[2] = 1;
|
||||
logicPortPos[2] = "3 -7 0";
|
||||
logicPortDir[2] = 3;
|
||||
logicPortUIName[2] = "A2";
|
||||
|
||||
logicPortType[3] = 1;
|
||||
logicPortPos[3] = "1 -7 0";
|
||||
logicPortDir[3] = 3;
|
||||
logicPortUIName[3] = "A3";
|
||||
|
||||
logicPortType[4] = 1;
|
||||
logicPortPos[4] = "-1 -7 0";
|
||||
logicPortDir[4] = 3;
|
||||
logicPortUIName[4] = "A4";
|
||||
|
||||
logicPortType[5] = 1;
|
||||
logicPortPos[5] = "-3 -7 0";
|
||||
logicPortDir[5] = 3;
|
||||
logicPortUIName[5] = "A5";
|
||||
|
||||
logicPortType[6] = 0;
|
||||
logicPortPos[6] = "7 7 0";
|
||||
logicPortDir[6] = 1;
|
||||
logicPortUIName[6] = "O0";
|
||||
|
||||
logicPortType[7] = 0;
|
||||
logicPortPos[7] = "5 7 0";
|
||||
logicPortDir[7] = 1;
|
||||
logicPortUIName[7] = "O1";
|
||||
|
||||
logicPortType[8] = 0;
|
||||
logicPortPos[8] = "3 7 0";
|
||||
logicPortDir[8] = 1;
|
||||
logicPortUIName[8] = "O2";
|
||||
|
||||
logicPortType[9] = 0;
|
||||
logicPortPos[9] = "1 7 0";
|
||||
logicPortDir[9] = 1;
|
||||
logicPortUIName[9] = "O3";
|
||||
|
||||
logicPortType[10] = 0;
|
||||
logicPortPos[10] = "-1 7 0";
|
||||
logicPortDir[10] = 1;
|
||||
logicPortUIName[10] = "O4";
|
||||
|
||||
logicPortType[11] = 0;
|
||||
logicPortPos[11] = "-3 7 0";
|
||||
logicPortDir[11] = 1;
|
||||
logicPortUIName[11] = "O5";
|
||||
|
||||
logicPortType[12] = 0;
|
||||
logicPortPos[12] = "-5 7 0";
|
||||
logicPortDir[12] = 1;
|
||||
logicPortUIName[12] = "O6";
|
||||
|
||||
logicPortType[13] = 0;
|
||||
logicPortPos[13] = "-7 7 0";
|
||||
logicPortDir[13] = 1;
|
||||
logicPortUIName[13] = "O7";
|
||||
|
||||
logicPortType[14] = 1;
|
||||
logicPortPos[14] = "7 -7 0";
|
||||
logicPortDir[14] = 2;
|
||||
logicPortUIName[14] = "Clock";
|
||||
logicPortCauseUpdate[14] = true;
|
||||
|
||||
};
|
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Reference in New Issue
Block a user